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firmware: xilinx: Add sysfs interface
Add firmware-ggs sysfs interface which provides read/write interface to global storage registers. Signed-off-by: Rajan Vaja <rajan.vaja@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com> Signed-off-by: Tejas Patel <tejas.patel@xilinx.com> Signed-off-by: Jolly Shah <jolly.shah@xilinx.com> Link: https://lore.kernel.org/r/1587761887-4279-23-git-send-email-jolly.shah@xilinx.com Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
This commit is contained in:
Rajan Vaja
Greg Kroah-Hartman
parent
4f680b72ea
commit
ae5c961da6
3 changed files with 218 additions and 1 deletions
50
Documentation/ABI/stable/sysfs-driver-firmware-zynqmp
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50
Documentation/ABI/stable/sysfs-driver-firmware-zynqmp
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@ -0,0 +1,50 @@
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What: /sys/devices/platform/firmware\:zynqmp-firmware/ggs*
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Date: March 2020
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KernelVersion: 5.6
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Contact: "Jolly Shah" <jollys@xilinx.com>
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Description:
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Read/Write PMU global general storage register value,
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GLOBAL_GEN_STORAGE{0:3}.
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Global general storage register that can be used
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by system to pass information between masters.
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The register is reset during system or power-on
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resets. Three registers are used by the FSBL and
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other Xilinx software products: GLOBAL_GEN_STORAGE{4:6}.
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Usage:
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# cat /sys/devices/platform/firmware\:zynqmp-firmware/ggs0
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# echo <value> > /sys/devices/platform/firmware\:zynqmp-firmware/ggs0
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Example:
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# cat /sys/devices/platform/firmware\:zynqmp-firmware/ggs0
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# echo 0x1234ABCD > /sys/devices/platform/firmware\:zynqmp-firmware/ggs0
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Users: Xilinx
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What: /sys/devices/platform/firmware\:zynqmp-firmware/pggs*
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Date: March 2020
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KernelVersion: 5.6
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Contact: "Jolly Shah" <jollys@xilinx.com>
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Description:
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Read/Write PMU persistent global general storage register
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value, PERS_GLOB_GEN_STORAGE{0:3}.
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Persistent global general storage register that
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can be used by system to pass information between
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masters.
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This register is only reset by the power-on reset
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and maintains its value through a system reset.
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Four registers are used by the FSBL and other Xilinx
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software products: PERS_GLOB_GEN_STORAGE{4:7}.
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Register is reset only by a POR reset.
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Usage:
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# cat /sys/devices/platform/firmware\:zynqmp-firmware/pggs0
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# echo <value> > /sys/devices/platform/firmware\:zynqmp-firmware/pggs0
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Example:
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# cat /sys/devices/platform/firmware\:zynqmp-firmware/pggs0
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# echo 0x1234ABCD > /sys/devices/platform/firmware\:zynqmp-firmware/pggs0
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Users: Xilinx
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@ -2,7 +2,7 @@
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/*
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* Xilinx Zynq MPSoC Firmware layer
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*
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* Copyright (C) 2014-2018 Xilinx, Inc.
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* Copyright (C) 2014-2020 Xilinx, Inc.
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*
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* Michal Simek <michal.simek@xilinx.com>
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* Davorin Mista <davorin.mista@aggios.com>
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@ -875,6 +875,170 @@ int zynqmp_pm_aes_engine(const u64 address, u32 *out)
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}
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EXPORT_SYMBOL_GPL(zynqmp_pm_aes_engine);
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static ssize_t ggs_show(struct device *device,
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struct device_attribute *attr,
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char *buf,
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u32 reg)
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{
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int ret;
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u32 ret_payload[PAYLOAD_ARG_CNT];
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ret = zynqmp_pm_read_ggs(reg, ret_payload);
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if (ret)
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return ret;
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return sprintf(buf, "0x%x\n", ret_payload[1]);
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}
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static ssize_t ggs_store(struct device *device,
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struct device_attribute *attr,
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const char *buf, size_t count,
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u32 reg)
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{
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long value;
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int ret;
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if (reg >= GSS_NUM_REGS)
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return -EINVAL;
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ret = kstrtol(buf, 16, &value);
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if (ret) {
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count = -EFAULT;
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goto err;
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}
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ret = zynqmp_pm_write_ggs(reg, value);
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if (ret)
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count = -EFAULT;
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err:
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return count;
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}
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/* GGS register show functions */
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#define GGS0_SHOW(N) \
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ssize_t ggs##N##_show(struct device *device, \
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struct device_attribute *attr, \
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char *buf) \
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{ \
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return ggs_show(device, attr, buf, N); \
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}
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static GGS0_SHOW(0);
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static GGS0_SHOW(1);
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static GGS0_SHOW(2);
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static GGS0_SHOW(3);
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/* GGS register store function */
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#define GGS0_STORE(N) \
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ssize_t ggs##N##_store(struct device *device, \
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struct device_attribute *attr, \
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const char *buf, \
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size_t count) \
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{ \
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return ggs_store(device, attr, buf, count, N); \
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}
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static GGS0_STORE(0);
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static GGS0_STORE(1);
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static GGS0_STORE(2);
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static GGS0_STORE(3);
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static ssize_t pggs_show(struct device *device,
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struct device_attribute *attr,
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char *buf,
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u32 reg)
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{
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int ret;
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u32 ret_payload[PAYLOAD_ARG_CNT];
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ret = zynqmp_pm_read_pggs(reg, ret_payload);
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if (ret)
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return ret;
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return sprintf(buf, "0x%x\n", ret_payload[1]);
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}
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static ssize_t pggs_store(struct device *device,
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struct device_attribute *attr,
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const char *buf, size_t count,
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u32 reg)
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{
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long value;
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int ret;
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if (reg >= GSS_NUM_REGS)
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return -EINVAL;
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ret = kstrtol(buf, 16, &value);
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if (ret) {
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count = -EFAULT;
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goto err;
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}
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ret = zynqmp_pm_write_pggs(reg, value);
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if (ret)
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count = -EFAULT;
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err:
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return count;
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}
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#define PGGS0_SHOW(N) \
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ssize_t pggs##N##_show(struct device *device, \
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struct device_attribute *attr, \
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char *buf) \
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{ \
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return pggs_show(device, attr, buf, N); \
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}
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#define PGGS0_STORE(N) \
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ssize_t pggs##N##_store(struct device *device, \
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struct device_attribute *attr, \
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const char *buf, \
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size_t count) \
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{ \
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return pggs_store(device, attr, buf, count, N); \
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}
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/* PGGS register show functions */
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static PGGS0_SHOW(0);
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static PGGS0_SHOW(1);
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static PGGS0_SHOW(2);
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static PGGS0_SHOW(3);
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/* PGGS register store functions */
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static PGGS0_STORE(0);
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static PGGS0_STORE(1);
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static PGGS0_STORE(2);
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static PGGS0_STORE(3);
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/* GGS register attributes */
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static DEVICE_ATTR_RW(ggs0);
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static DEVICE_ATTR_RW(ggs1);
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static DEVICE_ATTR_RW(ggs2);
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static DEVICE_ATTR_RW(ggs3);
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/* PGGS register attributes */
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static DEVICE_ATTR_RW(pggs0);
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static DEVICE_ATTR_RW(pggs1);
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static DEVICE_ATTR_RW(pggs2);
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static DEVICE_ATTR_RW(pggs3);
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static struct attribute *zynqmp_firmware_attrs[] = {
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&dev_attr_ggs0.attr,
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&dev_attr_ggs1.attr,
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&dev_attr_ggs2.attr,
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&dev_attr_ggs3.attr,
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&dev_attr_pggs0.attr,
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&dev_attr_pggs1.attr,
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&dev_attr_pggs2.attr,
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&dev_attr_pggs3.attr,
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NULL,
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};
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ATTRIBUTE_GROUPS(zynqmp_firmware);
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static int zynqmp_firmware_probe(struct platform_device *pdev)
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{
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struct device *dev = &pdev->dev;
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@ -952,6 +1116,7 @@ static struct platform_driver zynqmp_firmware_driver = {
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.driver = {
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.name = "zynqmp_firmware",
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.of_match_table = zynqmp_firmware_of_match,
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.dev_groups = zynqmp_firmware_groups,
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},
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.probe = zynqmp_firmware_probe,
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.remove = zynqmp_firmware_remove,
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@ -42,6 +42,8 @@
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#define ZYNQMP_PM_MAX_QOS 100U
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#define GSS_NUM_REGS (4)
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/* Node capabilities */
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#define ZYNQMP_PM_CAPABILITY_ACCESS 0x1U
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#define ZYNQMP_PM_CAPABILITY_CONTEXT 0x2U
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