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x86/platform/uv: Update for UV5 NMI MMR changes
The UV NMI MMR addresses and fields moved between UV4 and UV5 necessitating a rewrite of the UV NMI handler. Adjust references to accommodate those changes. Signed-off-by: Mike Travis <mike.travis@hpe.com> Signed-off-by: Borislav Petkov <bp@suse.de> Reviewed-by: Dimitri Sivanich <dimitri.sivanich@hpe.com> Reviewed-by: Steve Wahl <steve.wahl@hpe.com> Link: https://lkml.kernel.org/r/20201005203929.148656-13-mike.travis@hpe.com
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2 changed files with 54 additions and 23 deletions
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@ -734,19 +734,6 @@ extern void uv_nmi_setup_hubless(void);
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#define UVH_NMI_MMR_SHIFT 63
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#define UVH_NMI_MMR_TYPE "SCRATCH5"
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/* Newer SMM NMI handler, not present in all systems */
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#define UVH_NMI_MMRX UVH_EVENT_OCCURRED0
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#define UVH_NMI_MMRX_CLEAR UVH_EVENT_OCCURRED0_ALIAS
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#define UVH_NMI_MMRX_SHIFT UVH_EVENT_OCCURRED0_EXTIO_INT0_SHFT
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#define UVH_NMI_MMRX_TYPE "EXTIO_INT0"
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/* Non-zero indicates newer SMM NMI handler present */
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#define UVH_NMI_MMRX_SUPPORTED UVH_EXTIO_INT0_BROADCAST
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/* Indicates to BIOS that we want to use the newer SMM NMI handler */
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#define UVH_NMI_MMRX_REQ UVH_BIOS_KERNEL_MMR_ALIAS_2
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#define UVH_NMI_MMRX_REQ_SHIFT 62
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struct uv_hub_nmi_s {
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raw_spinlock_t nmi_lock;
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atomic_t in_nmi; /* flag this node in UV NMI IRQ */
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@ -2,8 +2,8 @@
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/*
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* SGI NMI support routines
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*
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* Copyright (c) 2009-2013 Silicon Graphics, Inc. All Rights Reserved.
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* Copyright (c) Mike Travis
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* Copyright (C) 2007-2017 Silicon Graphics, Inc. All rights reserved.
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* Copyright (c) Mike Travis
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*/
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#include <linux/cpu.h>
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@ -54,6 +54,20 @@ static struct uv_hub_nmi_s **uv_hub_nmi_list;
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DEFINE_PER_CPU(struct uv_cpu_nmi_s, uv_cpu_nmi);
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/* Newer SMM NMI handler, not present in all systems */
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static unsigned long uvh_nmi_mmrx; /* UVH_EVENT_OCCURRED0/1 */
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static unsigned long uvh_nmi_mmrx_clear; /* UVH_EVENT_OCCURRED0/1_ALIAS */
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static int uvh_nmi_mmrx_shift; /* UVH_EVENT_OCCURRED0/1_EXTIO_INT0_SHFT */
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static int uvh_nmi_mmrx_mask; /* UVH_EVENT_OCCURRED0/1_EXTIO_INT0_MASK */
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static char *uvh_nmi_mmrx_type; /* "EXTIO_INT0" */
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/* Non-zero indicates newer SMM NMI handler present */
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static unsigned long uvh_nmi_mmrx_supported; /* UVH_EXTIO_INT0_BROADCAST */
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/* Indicates to BIOS that we want to use the newer SMM NMI handler */
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static unsigned long uvh_nmi_mmrx_req; /* UVH_BIOS_KERNEL_MMR_ALIAS_2 */
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static int uvh_nmi_mmrx_req_shift; /* 62 */
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/* UV hubless values */
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#define NMI_CONTROL_PORT 0x70
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#define NMI_DUMMY_PORT 0x71
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@ -227,13 +241,43 @@ static inline bool uv_nmi_action_is(const char *action)
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/* Setup which NMI support is present in system */
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static void uv_nmi_setup_mmrs(void)
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{
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if (uv_read_local_mmr(UVH_NMI_MMRX_SUPPORTED)) {
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uv_write_local_mmr(UVH_NMI_MMRX_REQ,
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1UL << UVH_NMI_MMRX_REQ_SHIFT);
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nmi_mmr = UVH_NMI_MMRX;
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nmi_mmr_clear = UVH_NMI_MMRX_CLEAR;
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nmi_mmr_pending = 1UL << UVH_NMI_MMRX_SHIFT;
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pr_info("UV: SMI NMI support: %s\n", UVH_NMI_MMRX_TYPE);
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/* First determine arch specific MMRs to handshake with BIOS */
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if (UVH_EVENT_OCCURRED0_EXTIO_INT0_MASK) {
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uvh_nmi_mmrx = UVH_EVENT_OCCURRED0;
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uvh_nmi_mmrx_clear = UVH_EVENT_OCCURRED0_ALIAS;
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uvh_nmi_mmrx_shift = UVH_EVENT_OCCURRED0_EXTIO_INT0_SHFT;
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uvh_nmi_mmrx_mask = UVH_EVENT_OCCURRED0_EXTIO_INT0_MASK;
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uvh_nmi_mmrx_type = "OCRD0-EXTIO_INT0";
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uvh_nmi_mmrx_supported = UVH_EXTIO_INT0_BROADCAST;
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uvh_nmi_mmrx_req = UVH_BIOS_KERNEL_MMR_ALIAS_2;
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uvh_nmi_mmrx_req_shift = 62;
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} else if (UVH_EVENT_OCCURRED1_EXTIO_INT0_MASK) {
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uvh_nmi_mmrx = UVH_EVENT_OCCURRED1;
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uvh_nmi_mmrx_clear = UVH_EVENT_OCCURRED1_ALIAS;
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uvh_nmi_mmrx_shift = UVH_EVENT_OCCURRED1_EXTIO_INT0_SHFT;
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uvh_nmi_mmrx_mask = UVH_EVENT_OCCURRED1_EXTIO_INT0_MASK;
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uvh_nmi_mmrx_type = "OCRD1-EXTIO_INT0";
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uvh_nmi_mmrx_supported = UVH_EXTIO_INT0_BROADCAST;
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uvh_nmi_mmrx_req = UVH_BIOS_KERNEL_MMR_ALIAS_2;
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uvh_nmi_mmrx_req_shift = 62;
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} else {
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pr_err("UV:%s:cannot find EVENT_OCCURRED*_EXTIO_INT0\n",
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__func__);
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return;
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}
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/* Then find out if new NMI is supported */
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if (likely(uv_read_local_mmr(uvh_nmi_mmrx_supported))) {
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uv_write_local_mmr(uvh_nmi_mmrx_req,
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1UL << uvh_nmi_mmrx_req_shift);
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nmi_mmr = uvh_nmi_mmrx;
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nmi_mmr_clear = uvh_nmi_mmrx_clear;
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nmi_mmr_pending = 1UL << uvh_nmi_mmrx_shift;
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pr_info("UV: SMI NMI support: %s\n", uvh_nmi_mmrx_type);
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} else {
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nmi_mmr = UVH_NMI_MMR;
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nmi_mmr_clear = UVH_NMI_MMR_CLEAR;
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@ -1049,5 +1093,5 @@ void __init uv_nmi_setup_hubless(void)
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/* Ensure NMI enabled in Processor Interface Reg: */
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uv_reassert_nmi();
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uv_register_nmi_notifier();
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pr_info("UV: Hubless NMI enabled\n");
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pr_info("UV: PCH NMI enabled\n");
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}
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