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clk: imx: composite-8m: Add imx8m_divider_determine_rate
[ Upstream commit8208181fe5
] Currently, certain clocks are derrived as a divider from their parent clock. For some clocks, even when CLK_SET_RATE_PARENT is set, the parent clock is not properly set which can lead to some relatively inaccurate clock values. Unlike imx/clk-composite-93 and imx/clk-divider-gate, it cannot rely on calling a standard determine_rate function, because the 8m composite clocks have a pre-divider and post-divider. Because of this, a custom determine_rate function is necessary to determine the maximum clock division which is equivalent to pre-divider * the post-divider. With this added, the system can attempt to adjust the parent rate when the proper flags are set which can lead to a more precise clock value. On the imx8mplus, no clock changes are present. On the Mini and Nano, this can help achieve more accurate lcdif clocks. When trying to get a pixel clock of 31.500MHz on an imx8m Nano, the clocks divided the 594MHz down, but left the parent rate untouched which caused a calulation error. Before: video_pll 594000000 video_pll_bypass 594000000 video_pll_out 594000000 disp_pixel 31263158 disp_pixel_clk 31263158 Variance = -236842 Hz After this patch: video_pll 31500000 video_pll_bypass 31500000 video_pll_out 31500000 disp_pixel 31500000 disp_pixel_clk 31500000 Variance = 0 Hz All other clocks rates and parent were the same. Similar results on imx8mm were found. Fixes:690dccc4a0
("Revert "clk: imx: composite-8m: Add support to determine_rate"") Signed-off-by: Adam Ford <aford173@gmail.com> Reviewed-by: Abel Vesa <abel.vesa@linaro.org> Tested-by: Fabio Estevam <festevam@gmail.com> Link: https://lore.kernel.org/r/20230506195325.876871-1-aford173@gmail.com Signed-off-by: Abel Vesa <abel.vesa@linaro.org> Signed-off-by: Sasha Levin <sashal@kernel.org>
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@ -119,10 +119,41 @@ static int imx8m_clk_composite_divider_set_rate(struct clk_hw *hw,
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return ret;
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}
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static int imx8m_divider_determine_rate(struct clk_hw *hw,
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struct clk_rate_request *req)
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{
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struct clk_divider *divider = to_clk_divider(hw);
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int prediv_value;
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int div_value;
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/* if read only, just return current value */
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if (divider->flags & CLK_DIVIDER_READ_ONLY) {
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u32 val;
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val = readl(divider->reg);
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prediv_value = val >> divider->shift;
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prediv_value &= clk_div_mask(divider->width);
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prediv_value++;
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div_value = val >> PCG_DIV_SHIFT;
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div_value &= clk_div_mask(PCG_DIV_WIDTH);
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div_value++;
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return divider_ro_determine_rate(hw, req, divider->table,
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PCG_PREDIV_WIDTH + PCG_DIV_WIDTH,
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divider->flags, prediv_value * div_value);
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}
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return divider_determine_rate(hw, req, divider->table,
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PCG_PREDIV_WIDTH + PCG_DIV_WIDTH,
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divider->flags);
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}
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static const struct clk_ops imx8m_clk_composite_divider_ops = {
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.recalc_rate = imx8m_clk_composite_divider_recalc_rate,
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.round_rate = imx8m_clk_composite_divider_round_rate,
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.set_rate = imx8m_clk_composite_divider_set_rate,
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.determine_rate = imx8m_divider_determine_rate,
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};
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static u8 imx8m_clk_composite_mux_get_parent(struct clk_hw *hw)
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