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arm64: head.S: get rid of x25 and x26 with 'global' scope
Currently, x25 and x26 hold the physical addresses of idmap_pg_dir and swapper_pg_dir, respectively, when running early boot code. But having registers with 'global' scope in files that contain different sections with different lifetimes, and that are called by different CPUs at different times is a bit messy, especially since stashing the values does not buy us anything in terms of code size or clarity. So simply replace each reference to x25 or x26 with an adrp instruction referring to idmap_pg_dir or swapper_pg_dir directly. Acked-by: Mark Rutland <mark.rutland@arm.com> Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> Signed-off-by: Will Deacon <will.deacon@arm.com>
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5a9e3e156e
commit
aea73abb90
2 changed files with 13 additions and 17 deletions
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@ -214,7 +214,7 @@ ENTRY(stext)
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adrp x24, __PHYS_OFFSET
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and x23, x24, MIN_KIMG_ALIGN - 1 // KASLR offset, defaults to 0
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bl set_cpu_boot_mode_flag
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bl __create_page_tables // x25=TTBR0, x26=TTBR1
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bl __create_page_tables
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/*
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* The following calls CPU setup code, see arch/arm64/mm/proc.S for
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* details.
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@ -311,23 +311,21 @@ ENDPROC(preserve_boot_args)
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* been enabled
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*/
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__create_page_tables:
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adrp x25, idmap_pg_dir
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adrp x26, swapper_pg_dir
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mov x28, lr
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/*
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* Invalidate the idmap and swapper page tables to avoid potential
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* dirty cache lines being evicted.
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*/
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mov x0, x25
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add x1, x26, #SWAPPER_DIR_SIZE
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adrp x0, idmap_pg_dir
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adrp x1, swapper_pg_dir + SWAPPER_DIR_SIZE
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bl __inval_cache_range
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/*
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* Clear the idmap and swapper page tables.
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*/
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mov x0, x25
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add x6, x26, #SWAPPER_DIR_SIZE
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adrp x0, idmap_pg_dir
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adrp x6, swapper_pg_dir + SWAPPER_DIR_SIZE
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1: stp xzr, xzr, [x0], #16
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stp xzr, xzr, [x0], #16
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stp xzr, xzr, [x0], #16
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@ -340,7 +338,7 @@ __create_page_tables:
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/*
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* Create the identity mapping.
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*/
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mov x0, x25 // idmap_pg_dir
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adrp x0, idmap_pg_dir
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adrp x3, __idmap_text_start // __pa(__idmap_text_start)
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#ifndef CONFIG_ARM64_VA_BITS_48
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@ -390,7 +388,7 @@ __create_page_tables:
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/*
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* Map the kernel image (starting with PHYS_OFFSET).
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*/
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mov x0, x26 // swapper_pg_dir
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adrp x0, swapper_pg_dir
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mov_q x5, KIMAGE_VADDR + TEXT_OFFSET // compile time __va(_text)
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add x5, x5, x23 // add KASLR displacement
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create_pgd_entry x0, x5, x3, x6
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@ -405,8 +403,8 @@ __create_page_tables:
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* accesses (MMU disabled), invalidate the idmap and swapper page
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* tables again to remove any speculatively loaded cache lines.
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*/
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mov x0, x25
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add x1, x26, #SWAPPER_DIR_SIZE
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adrp x0, idmap_pg_dir
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adrp x1, swapper_pg_dir + SWAPPER_DIR_SIZE
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dmb sy
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bl __inval_cache_range
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@ -666,8 +664,6 @@ secondary_startup:
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/*
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* Common entry point for secondary CPUs.
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*/
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adrp x25, idmap_pg_dir
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adrp x26, swapper_pg_dir
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bl __cpu_setup // initialise processor
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adr_l x27, __secondary_switch // address to jump to after enabling the MMU
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@ -731,8 +727,10 @@ ENTRY(__enable_mmu)
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cmp x2, #ID_AA64MMFR0_TGRAN_SUPPORTED
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b.ne __no_granule_support
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update_early_cpu_boot_status 0, x1, x2
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msr ttbr0_el1, x25 // load TTBR0
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msr ttbr1_el1, x26 // load TTBR1
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adrp x1, idmap_pg_dir
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adrp x2, swapper_pg_dir
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msr ttbr0_el1, x1 // load TTBR0
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msr ttbr1_el1, x2 // load TTBR1
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isb
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msr sctlr_el1, x0
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isb
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@ -102,8 +102,6 @@ ENTRY(cpu_resume)
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/* enable the MMU early - so we can access sleep_save_stash by va */
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adr_l lr, __enable_mmu /* __cpu_setup will return here */
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adr_l x27, _resume_switched /* __enable_mmu will branch here */
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adrp x25, idmap_pg_dir
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adrp x26, swapper_pg_dir
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b __cpu_setup
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ENDPROC(cpu_resume)
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