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phy: cadence: Sierra: Modify register macro names to be in sync with Sierra user guide
No functional change. Modify register offset macro names to be in sync with Sierra user guide. Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
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1 changed files with 84 additions and 83 deletions
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@ -28,44 +28,45 @@
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#define SIERRA_LANE_CDB_OFFSET(ln, block_offset, reg_offset) \
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((0x4000 << (block_offset)) + \
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(((ln) << 9) << (reg_offset)))
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#define SIERRA_DET_STANDEC_A 0x000
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#define SIERRA_DET_STANDEC_B 0x001
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#define SIERRA_DET_STANDEC_C 0x002
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#define SIERRA_DET_STANDEC_D 0x003
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#define SIERRA_DET_STANDEC_E 0x004
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#define SIERRA_PSM_LANECAL 0x008
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#define SIERRA_PSM_DIAG 0x015
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#define SIERRA_PSC_TX_A0 0x028
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#define SIERRA_PSC_TX_A1 0x029
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#define SIERRA_PSC_TX_A2 0x02A
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#define SIERRA_PSC_TX_A3 0x02B
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#define SIERRA_PSC_RX_A0 0x030
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#define SIERRA_PSC_RX_A1 0x031
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#define SIERRA_PSC_RX_A2 0x032
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#define SIERRA_PSC_RX_A3 0x033
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#define SIERRA_PLLCTRL_SUBRATE 0x03A
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#define SIERRA_PLLCTRL_GEN_D 0x03E
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#define SIERRA_DRVCTRL_ATTEN 0x06A
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#define SIERRA_CLKPATHCTRL_TMR 0x081
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#define SIERRA_RX_CREQ_FLTR_A_MODE1 0x087
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#define SIERRA_RX_CREQ_FLTR_A_MODE0 0x088
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#define SIERRA_CREQ_CCLKDET_MODE01 0x08E
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#define SIERRA_RX_CTLE_MAINTENANCE 0x091
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#define SIERRA_CREQ_FSMCLK_SEL 0x092
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#define SIERRA_CTLELUT_CTRL 0x098
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#define SIERRA_DFE_ECMP_RATESEL 0x0C0
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#define SIERRA_DFE_SMP_RATESEL 0x0C1
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#define SIERRA_DEQ_VGATUNE_CTRL 0x0E1
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#define SIERRA_TMRVAL_MODE3 0x16E
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#define SIERRA_TMRVAL_MODE2 0x16F
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#define SIERRA_TMRVAL_MODE1 0x170
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#define SIERRA_TMRVAL_MODE0 0x171
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#define SIERRA_PICNT_MODE1 0x174
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#define SIERRA_CPI_OUTBUF_RATESEL 0x17C
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#define SIERRA_LFPSFILT_NS 0x18A
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#define SIERRA_LFPSFILT_RD 0x18B
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#define SIERRA_LFPSFILT_MP 0x18C
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#define SIERRA_SDFILT_H2L_A 0x191
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#define SIERRA_DET_STANDEC_A_PREG 0x000
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#define SIERRA_DET_STANDEC_B_PREG 0x001
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#define SIERRA_DET_STANDEC_C_PREG 0x002
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#define SIERRA_DET_STANDEC_D_PREG 0x003
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#define SIERRA_DET_STANDEC_E_PREG 0x004
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#define SIERRA_PSM_LANECAL_PREG 0x008
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#define SIERRA_PSM_DIAG_PREG 0x015
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#define SIERRA_PSC_TX_A0_PREG 0x028
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#define SIERRA_PSC_TX_A1_PREG 0x029
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#define SIERRA_PSC_TX_A2_PREG 0x02A
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#define SIERRA_PSC_TX_A3_PREG 0x02B
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#define SIERRA_PSC_RX_A0_PREG 0x030
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#define SIERRA_PSC_RX_A1_PREG 0x031
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#define SIERRA_PSC_RX_A2_PREG 0x032
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#define SIERRA_PSC_RX_A3_PREG 0x033
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#define SIERRA_PLLCTRL_SUBRATE_PREG 0x03A
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#define SIERRA_PLLCTRL_GEN_D_PREG 0x03E
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#define SIERRA_DRVCTRL_ATTEN_PREG 0x06A
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#define SIERRA_CLKPATHCTRL_TMR_PREG 0x081
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#define SIERRA_RX_CREQ_FLTR_A_MODE1_PREG 0x087
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#define SIERRA_RX_CREQ_FLTR_A_MODE0_PREG 0x088
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#define SIERRA_CREQ_CCLKDET_MODE01_PREG 0x08E
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#define SIERRA_RX_CTLE_MAINTENANCE_PREG 0x091
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#define SIERRA_CREQ_FSMCLK_SEL_PREG 0x092
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#define SIERRA_CTLELUT_CTRL_PREG 0x098
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#define SIERRA_DFE_ECMP_RATESEL_PREG 0x0C0
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#define SIERRA_DFE_SMP_RATESEL_PREG 0x0C1
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#define SIERRA_DEQ_VGATUNE_CTRL_PREG 0x0E1
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#define SIERRA_TMRVAL_MODE3_PREG 0x16E
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#define SIERRA_TMRVAL_MODE2_PREG 0x16F
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#define SIERRA_TMRVAL_MODE1_PREG 0x170
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#define SIERRA_TMRVAL_MODE0_PREG 0x171
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#define SIERRA_PICNT_MODE1_PREG 0x174
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#define SIERRA_CPI_OUTBUF_RATESEL_PREG 0x17C
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#define SIERRA_LFPSFILT_NS_PREG 0x18A
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#define SIERRA_LFPSFILT_RD_PREG 0x18B
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#define SIERRA_LFPSFILT_MP_PREG 0x18C
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#define SIERRA_SDFILT_H2L_A_PREG 0x191
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#define SIERRA_PHY_CONFIG_CTRL_OFFSET(block_offset) \
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(0xc000 << (block_offset))
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@ -496,42 +497,42 @@ static struct cdns_reg_pairs cdns_usb_regs[] = {
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* These values are specific to this specific hardware
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* configuration.
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*/
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{0xFE0A, SIERRA_DET_STANDEC_A},
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{0x000F, SIERRA_DET_STANDEC_B},
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{0x55A5, SIERRA_DET_STANDEC_C},
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{0x69AD, SIERRA_DET_STANDEC_D},
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{0x0241, SIERRA_DET_STANDEC_E},
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{0x0110, SIERRA_PSM_LANECAL},
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{0xCF00, SIERRA_PSM_DIAG},
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{0x001F, SIERRA_PSC_TX_A0},
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{0x0007, SIERRA_PSC_TX_A1},
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{0x0003, SIERRA_PSC_TX_A2},
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{0x0003, SIERRA_PSC_TX_A3},
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{0x0FFF, SIERRA_PSC_RX_A0},
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{0x0003, SIERRA_PSC_RX_A1},
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{0x0003, SIERRA_PSC_RX_A2},
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{0x0001, SIERRA_PSC_RX_A3},
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{0x0001, SIERRA_PLLCTRL_SUBRATE},
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{0x0406, SIERRA_PLLCTRL_GEN_D},
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{0x0000, SIERRA_DRVCTRL_ATTEN},
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{0x823E, SIERRA_CLKPATHCTRL_TMR},
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{0x078F, SIERRA_RX_CREQ_FLTR_A_MODE1},
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{0x078F, SIERRA_RX_CREQ_FLTR_A_MODE0},
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{0x7B3C, SIERRA_CREQ_CCLKDET_MODE01},
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{0x023C, SIERRA_RX_CTLE_MAINTENANCE},
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{0x3232, SIERRA_CREQ_FSMCLK_SEL},
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{0x8452, SIERRA_CTLELUT_CTRL},
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{0x4121, SIERRA_DFE_ECMP_RATESEL},
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{0x4121, SIERRA_DFE_SMP_RATESEL},
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{0x9999, SIERRA_DEQ_VGATUNE_CTRL},
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{0x0330, SIERRA_TMRVAL_MODE0},
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{0x01FF, SIERRA_PICNT_MODE1},
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{0x0009, SIERRA_CPI_OUTBUF_RATESEL},
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{0x000F, SIERRA_LFPSFILT_NS},
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{0x0009, SIERRA_LFPSFILT_RD},
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{0x0001, SIERRA_LFPSFILT_MP},
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{0x8013, SIERRA_SDFILT_H2L_A},
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{0x0400, SIERRA_TMRVAL_MODE1},
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{0xFE0A, SIERRA_DET_STANDEC_A_PREG},
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{0x000F, SIERRA_DET_STANDEC_B_PREG},
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{0x55A5, SIERRA_DET_STANDEC_C_PREG},
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{0x69AD, SIERRA_DET_STANDEC_D_PREG},
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{0x0241, SIERRA_DET_STANDEC_E_PREG},
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{0x0110, SIERRA_PSM_LANECAL_PREG},
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{0xCF00, SIERRA_PSM_DIAG_PREG},
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{0x001F, SIERRA_PSC_TX_A0_PREG},
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{0x0007, SIERRA_PSC_TX_A1_PREG},
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{0x0003, SIERRA_PSC_TX_A2_PREG},
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{0x0003, SIERRA_PSC_TX_A3_PREG},
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{0x0FFF, SIERRA_PSC_RX_A0_PREG},
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{0x0003, SIERRA_PSC_RX_A1_PREG},
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{0x0003, SIERRA_PSC_RX_A2_PREG},
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{0x0001, SIERRA_PSC_RX_A3_PREG},
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{0x0001, SIERRA_PLLCTRL_SUBRATE_PREG},
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{0x0406, SIERRA_PLLCTRL_GEN_D_PREG},
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{0x0000, SIERRA_DRVCTRL_ATTEN_PREG},
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{0x823E, SIERRA_CLKPATHCTRL_TMR_PREG},
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{0x078F, SIERRA_RX_CREQ_FLTR_A_MODE1_PREG},
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{0x078F, SIERRA_RX_CREQ_FLTR_A_MODE0_PREG},
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{0x7B3C, SIERRA_CREQ_CCLKDET_MODE01_PREG},
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{0x023C, SIERRA_RX_CTLE_MAINTENANCE_PREG},
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{0x3232, SIERRA_CREQ_FSMCLK_SEL_PREG},
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{0x8452, SIERRA_CTLELUT_CTRL_PREG},
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{0x4121, SIERRA_DFE_ECMP_RATESEL_PREG},
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{0x4121, SIERRA_DFE_SMP_RATESEL_PREG},
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{0x9999, SIERRA_DEQ_VGATUNE_CTRL_PREG},
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{0x0330, SIERRA_TMRVAL_MODE0_PREG},
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{0x01FF, SIERRA_PICNT_MODE1_PREG},
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{0x0009, SIERRA_CPI_OUTBUF_RATESEL_PREG},
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{0x000F, SIERRA_LFPSFILT_NS_PREG},
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{0x0009, SIERRA_LFPSFILT_RD_PREG},
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{0x0001, SIERRA_LFPSFILT_MP_PREG},
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{0x8013, SIERRA_SDFILT_H2L_A_PREG},
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{0x0400, SIERRA_TMRVAL_MODE1_PREG},
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};
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static struct cdns_reg_pairs cdns_pcie_regs[] = {
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@ -540,10 +541,10 @@ static struct cdns_reg_pairs cdns_pcie_regs[] = {
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* These values are specific to this specific hardware
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* configuration.
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*/
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{0x891f, SIERRA_DET_STANDEC_D},
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{0x0053, SIERRA_DET_STANDEC_E},
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{0x0400, SIERRA_TMRVAL_MODE2},
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{0x0200, SIERRA_TMRVAL_MODE3},
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{0x891f, SIERRA_DET_STANDEC_D_PREG},
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{0x0053, SIERRA_DET_STANDEC_E_PREG},
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{0x0400, SIERRA_TMRVAL_MODE2_PREG},
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{0x0200, SIERRA_TMRVAL_MODE3_PREG},
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};
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static const struct cdns_sierra_data cdns_map_sierra = {
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