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ARM: clk-imx6q: refine clock tree for ASRC
ASRC has "asrc", "asrc_ipg", "asrc_mem" clocks, and they share the same gate bits. Signed-off-by: Shengjiu Wang <shengjiu.wang@freescale.com> Signed-off-by: Shawn Guo <shawn.guo@freescale.com>
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e37c1ad032
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2 changed files with 7 additions and 2 deletions
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@ -107,6 +107,7 @@ static struct clk_div_table video_div_table[] = {
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};
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static unsigned int share_count_esai;
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static unsigned int share_count_asrc;
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static void __init imx6q_clocks_init(struct device_node *ccm_node)
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{
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@ -317,7 +318,9 @@ static void __init imx6q_clocks_init(struct device_node *ccm_node)
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/* name parent_name reg shift */
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clk[IMX6QDL_CLK_APBH_DMA] = imx_clk_gate2("apbh_dma", "usdhc3", base + 0x68, 4);
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clk[IMX6QDL_CLK_ASRC] = imx_clk_gate2("asrc", "asrc_podf", base + 0x68, 6);
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clk[IMX6QDL_CLK_ASRC] = imx_clk_gate2_shared("asrc", "asrc_podf", base + 0x68, 6, &share_count_asrc);
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clk[IMX6QDL_CLK_ASRC_IPG] = imx_clk_gate2_shared("asrc_ipg", "ahb", base + 0x68, 6, &share_count_asrc);
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clk[IMX6QDL_CLK_ASRC_MEM] = imx_clk_gate2_shared("asrc_mem", "ahb", base + 0x68, 6, &share_count_asrc);
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clk[IMX6QDL_CLK_CAN1_IPG] = imx_clk_gate2("can1_ipg", "ipg", base + 0x68, 14);
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clk[IMX6QDL_CLK_CAN1_SERIAL] = imx_clk_gate2("can1_serial", "can_root", base + 0x68, 16);
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clk[IMX6QDL_CLK_CAN2_IPG] = imx_clk_gate2("can2_ipg", "ipg", base + 0x68, 18);
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@ -220,6 +220,8 @@
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#define IMX6QDL_CLK_LVDS2_GATE 207
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#define IMX6QDL_CLK_ESAI_IPG 208
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#define IMX6QDL_CLK_ESAI_MEM 209
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#define IMX6QDL_CLK_END 210
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#define IMX6QDL_CLK_ASRC_IPG 210
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#define IMX6QDL_CLK_ASRC_MEM 211
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#define IMX6QDL_CLK_END 212
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#endif /* __DT_BINDINGS_CLOCK_IMX6QDL_H */
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