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drm/amdgpu: apply nbio7 for Raven (v3)
nbio handles misc bus io operations. Handle differences between different nbio bus versions. v2: switch checks from RAVEN to APU (Alex) squash in raven rev id fetch squash in fix uninitalized hdp flush reg index for raven v3: add some missed RAVEN to APU checks (Alex) Signed-off-by: Chunming Zhou <David1.Zhou@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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954d5d437f
commit
aecbe64f2b
5 changed files with 54 additions and 18 deletions
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@ -33,6 +33,7 @@
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#include "soc15_common.h"
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#include "nbio_v6_1.h"
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#include "nbio_v7_0.h"
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#include "gfxhub_v1_0.h"
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#include "mmhub_v1_0.h"
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@ -215,7 +216,10 @@ static void gmc_v9_0_gart_flush_gpu_tlb(struct amdgpu_device *adev,
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unsigned i, j;
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/* flush hdp cache */
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nbio_v6_1_hdp_flush(adev);
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if (adev->flags & AMD_IS_APU)
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nbio_v7_0_hdp_flush(adev);
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else
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nbio_v6_1_hdp_flush(adev);
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spin_lock(&adev->mc.invalidate_lock);
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@ -479,7 +483,8 @@ static int gmc_v9_0_mc_init(struct amdgpu_device *adev)
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adev->mc.aper_size = pci_resource_len(adev->pdev, 0);
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/* size in MB on si */
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adev->mc.mc_vram_size =
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nbio_v6_1_get_memsize(adev) * 1024ULL * 1024ULL;
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((adev->flags & AMD_IS_APU) ? nbio_v7_0_get_memsize(adev) :
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nbio_v6_1_get_memsize(adev)) * 1024ULL * 1024ULL;
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adev->mc.real_vram_size = adev->mc.mc_vram_size;
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adev->mc.visible_vram_size = adev->mc.aper_size;
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@ -718,7 +723,10 @@ static int gmc_v9_0_gart_enable(struct amdgpu_device *adev)
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return r;
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/* After HDP is initialized, flush HDP.*/
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nbio_v6_1_hdp_flush(adev);
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if (adev->flags & AMD_IS_APU)
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nbio_v7_0_hdp_flush(adev);
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else
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nbio_v6_1_hdp_flush(adev);
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r = gfxhub_v1_0_gart_enable(adev);
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if (r)
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@ -386,7 +386,9 @@ static void sdma_v4_0_ring_emit_hdp_flush(struct amdgpu_ring *ring)
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u32 ref_and_mask = 0;
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struct nbio_hdp_flush_reg *nbio_hf_reg;
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if (ring->adev->asic_type == CHIP_VEGA10)
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if (ring->adev->flags & AMD_IS_APU)
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nbio_hf_reg = &nbio_v7_0_hdp_flush_reg;
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else
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nbio_hf_reg = &nbio_v6_1_hdp_flush_reg;
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if (ring == &ring->adev->sdma.instance[0].ring)
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@ -617,7 +619,10 @@ static int sdma_v4_0_gfx_resume(struct amdgpu_device *adev)
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}
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WREG32(sdma_v4_0_get_reg_offset(i, mmSDMA0_GFX_DOORBELL), doorbell);
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WREG32(sdma_v4_0_get_reg_offset(i, mmSDMA0_GFX_DOORBELL_OFFSET), doorbell_offset);
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nbio_v6_1_sdma_doorbell_range(adev, i, ring->use_doorbell, ring->doorbell_index);
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if (adev->flags & AMD_IS_APU)
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nbio_v7_0_sdma_doorbell_range(adev, i, ring->use_doorbell, ring->doorbell_index);
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else
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nbio_v6_1_sdma_doorbell_range(adev, i, ring->use_doorbell, ring->doorbell_index);
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if (amdgpu_sriov_vf(adev))
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sdma_v4_0_ring_set_wptr(ring);
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@ -104,10 +104,10 @@ static u32 soc15_pcie_rreg(struct amdgpu_device *adev, u32 reg)
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u32 r;
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struct nbio_pcie_index_data *nbio_pcie_id;
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if (adev->asic_type == CHIP_VEGA10)
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nbio_pcie_id = &nbio_v6_1_pcie_index_data;
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if (adev->flags & AMD_IS_APU)
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nbio_pcie_id = &nbio_v7_0_pcie_index_data;
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else
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BUG();
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nbio_pcie_id = &nbio_v6_1_pcie_index_data;
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address = nbio_pcie_id->index_offset;
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data = nbio_pcie_id->data_offset;
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@ -125,10 +125,10 @@ static void soc15_pcie_wreg(struct amdgpu_device *adev, u32 reg, u32 v)
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unsigned long flags, address, data;
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struct nbio_pcie_index_data *nbio_pcie_id;
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if (adev->asic_type == CHIP_VEGA10)
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nbio_pcie_id = &nbio_v6_1_pcie_index_data;
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if (adev->flags & AMD_IS_APU)
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nbio_pcie_id = &nbio_v7_0_pcie_index_data;
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else
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BUG();
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nbio_pcie_id = &nbio_v6_1_pcie_index_data;
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address = nbio_pcie_id->index_offset;
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data = nbio_pcie_id->data_offset;
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@ -199,7 +199,10 @@ static void soc15_didt_wreg(struct amdgpu_device *adev, u32 reg, u32 v)
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static u32 soc15_get_config_memsize(struct amdgpu_device *adev)
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{
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return nbio_v6_1_get_memsize(adev);
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if (adev->flags & AMD_IS_APU)
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return nbio_v7_0_get_memsize(adev);
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else
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return nbio_v6_1_get_memsize(adev);
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}
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static const u32 vega10_golden_init[] =
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@ -376,7 +379,10 @@ static void soc15_gpu_pci_config_reset(struct amdgpu_device *adev)
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/* wait for asic to come out of reset */
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for (i = 0; i < adev->usec_timeout; i++) {
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if (nbio_v6_1_get_memsize(adev) != 0xffffffff)
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u32 memsize = (adev->flags & AMD_IS_APU) ?
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nbio_v7_0_get_memsize(adev) :
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nbio_v6_1_get_memsize(adev);
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if (memsize != 0xffffffff)
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break;
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udelay(1);
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}
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@ -450,8 +456,12 @@ static void soc15_program_aspm(struct amdgpu_device *adev)
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static void soc15_enable_doorbell_aperture(struct amdgpu_device *adev,
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bool enable)
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{
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nbio_v6_1_enable_doorbell_aperture(adev, enable);
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nbio_v6_1_enable_doorbell_selfring_aperture(adev, enable);
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if (adev->flags & AMD_IS_APU) {
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nbio_v7_0_enable_doorbell_aperture(adev, enable);
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} else {
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nbio_v6_1_enable_doorbell_aperture(adev, enable);
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nbio_v6_1_enable_doorbell_selfring_aperture(adev, enable);
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}
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}
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static const struct amdgpu_ip_block_version vega10_common_ip_block =
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@ -506,7 +516,10 @@ int soc15_set_ip_blocks(struct amdgpu_device *adev)
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static uint32_t soc15_get_rev_id(struct amdgpu_device *adev)
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{
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return nbio_v6_1_get_rev_id(adev);
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if (adev->flags & AMD_IS_APU)
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return nbio_v7_0_get_rev_id(adev);
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else
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return nbio_v6_1_get_rev_id(adev);
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}
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@ -557,6 +570,9 @@ static int soc15_common_early_init(void *handle)
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case CHIP_VEGA10:
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nbio_v6_1_init(adev);
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break;
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case CHIP_RAVEN:
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nbio_v7_0_init(adev);
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break;
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default:
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return -EINVAL;
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}
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@ -25,6 +25,7 @@
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#define __SOC15_H__
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#include "nbio_v6_1.h"
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#include "nbio_v7_0.h"
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extern const struct amd_ip_funcs soc15_common_ip_funcs;
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@ -97,7 +97,10 @@ static int vega10_ih_irq_init(struct amdgpu_device *adev)
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/* disable irqs */
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vega10_ih_disable_interrupts(adev);
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nbio_v6_1_ih_control(adev);
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if (adev->flags & AMD_IS_APU)
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nbio_v7_0_ih_control(adev);
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else
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nbio_v6_1_ih_control(adev);
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ih_rb_cntl = RREG32(SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_CNTL));
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/* Ring Buffer base. [39:8] of 40-bit address of the beginning of the ring buffer*/
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@ -148,7 +151,10 @@ static int vega10_ih_irq_init(struct amdgpu_device *adev)
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ENABLE, 0);
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}
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WREG32(SOC15_REG_OFFSET(OSSSYS, 0, mmIH_DOORBELL_RPTR), ih_doorbell_rtpr);
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nbio_v6_1_ih_doorbell_range(adev, adev->irq.ih.use_doorbell, adev->irq.ih.doorbell_index);
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if (adev->flags & AMD_IS_APU)
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nbio_v7_0_ih_doorbell_range(adev, adev->irq.ih.use_doorbell, adev->irq.ih.doorbell_index);
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else
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nbio_v6_1_ih_doorbell_range(adev, adev->irq.ih.use_doorbell, adev->irq.ih.doorbell_index);
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tmp = RREG32(SOC15_REG_OFFSET(OSSSYS, 0, mmIH_STORM_CLIENT_LIST_CNTL));
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tmp = REG_SET_FIELD(tmp, IH_STORM_CLIENT_LIST_CNTL,
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