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drm/amdgpu/si_dpm: Limit clocks on HD86xx part
Limit clocks on a specific HD86xx part to avoid crashes (while awaiting an appropriate PP fix). Signed-off-by: Tom St Denis <tom.stdenis@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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@ -3499,6 +3499,12 @@ static void si_apply_state_adjust_rules(struct amdgpu_device *adev,
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max_sclk = 75000;
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max_mclk = 80000;
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}
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/* Limit clocks for some HD8600 parts */
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if (adev->pdev->device == 0x6660 &&
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adev->pdev->revision == 0x83) {
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max_sclk = 75000;
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max_mclk = 80000;
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}
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if (rps->vce_active) {
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rps->evclk = adev->pm.dpm.vce_states[adev->pm.dpm.vce_level].evclk;
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