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ARM64: dts: Add DTS files for bcmbca SoC BCM6858
[ Upstream commite663e06bd3
] Add DTS for ARMv8 based broadband SoC BCM6858. bcm6858.dtsi is the SoC description DTS header and bcm96858.dts is a simple DTS file for Broadcom BCM96858 Reference board that only enables the UART port. Signed-off-by: Anand Gore <anand.gore@broadcom.com> Signed-off-by: Florian Fainelli <f.fainelli@gmail.com> Stable-dep-of:5cca024494
("arm64: dts: broadcom: bcmbca: bcm4908: fix NAND interrupt name") Signed-off-by: Sasha Levin <sashal@kernel.org>
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3 changed files with 153 additions and 1 deletions
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# SPDX-License-Identifier: GPL-2.0
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dtb-$(CONFIG_ARCH_BCMBCA) += bcm94912.dtb \
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bcm963158.dtb
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bcm963158.dtb \
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bcm96858.dtb
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121
arch/arm64/boot/dts/broadcom/bcmbca/bcm6858.dtsi
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121
arch/arm64/boot/dts/broadcom/bcmbca/bcm6858.dtsi
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// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
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/*
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* Copyright 2022 Broadcom Ltd.
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*/
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#include <dt-bindings/interrupt-controller/irq.h>
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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/ {
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compatible = "brcm,bcm6858", "brcm,bcmbca";
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#address-cells = <2>;
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#size-cells = <2>;
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interrupt-parent = <&gic>;
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cpus {
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#address-cells = <2>;
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#size-cells = <0>;
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B53_0: cpu@0 {
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compatible = "brcm,brahma-b53";
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device_type = "cpu";
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reg = <0x0 0x0>;
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next-level-cache = <&L2_0>;
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enable-method = "psci";
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};
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B53_1: cpu@1 {
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compatible = "brcm,brahma-b53";
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device_type = "cpu";
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reg = <0x0 0x1>;
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next-level-cache = <&L2_0>;
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enable-method = "psci";
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};
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B53_2: cpu@2 {
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compatible = "brcm,brahma-b53";
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device_type = "cpu";
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reg = <0x0 0x2>;
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next-level-cache = <&L2_0>;
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enable-method = "psci";
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};
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B53_3: cpu@3 {
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compatible = "brcm,brahma-b53";
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device_type = "cpu";
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reg = <0x0 0x3>;
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next-level-cache = <&L2_0>;
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enable-method = "psci";
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};
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L2_0: l2-cache0 {
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compatible = "cache";
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};
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};
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timer {
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compatible = "arm,armv8-timer";
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interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
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<GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
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<GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
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<GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
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};
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pmu: pmu {
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compatible = "arm,armv8-pmuv3";
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interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-affinity = <&B53_0>, <&B53_1>,
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<&B53_2>, <&B53_3>;
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};
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clocks: clocks {
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periph_clk:periph-clk {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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clock-frequency = <200000000>;
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};
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};
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psci {
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compatible = "arm,psci-0.2";
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method = "smc";
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};
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axi@81000000 {
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compatible = "simple-bus";
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#address-cells = <1>;
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#size-cells = <1>;
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ranges = <0x0 0x0 0x81000000 0x8000>;
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gic: interrupt-controller@1000 {
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compatible = "arm,gic-400";
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#interrupt-cells = <3>;
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interrupt-controller;
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reg = <0x1000 0x1000>, /* GICD */
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<0x2000 0x2000>, /* GICC */
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<0x4000 0x2000>, /* GICH */
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<0x6000 0x2000>; /* GICV */
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interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) |
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IRQ_TYPE_LEVEL_HIGH)>;
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};
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};
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bus@ff800000 {
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compatible = "simple-bus";
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#address-cells = <1>;
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#size-cells = <1>;
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ranges = <0x0 0x0 0xff800000 0x62000>;
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uart0: serial@640 {
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compatible = "brcm,bcm6345-uart";
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reg = <0x640 0x18>;
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interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&periph_clk>;
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clock-names = "refclk";
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status = "disabled";
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};
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};
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};
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30
arch/arm64/boot/dts/broadcom/bcmbca/bcm96858.dts
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30
arch/arm64/boot/dts/broadcom/bcmbca/bcm96858.dts
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// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
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/*
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* Copyright 2022 Broadcom Ltd.
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*/
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/dts-v1/;
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#include "bcm6858.dtsi"
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/ {
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model = "Broadcom BCM96858 Reference Board";
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compatible = "brcm,bcm96858", "brcm,bcm6858", "brcm,bcmbca";
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aliases {
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serial0 = &uart0;
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};
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chosen {
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stdout-path = "serial0:115200n8";
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};
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memory@0 {
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device_type = "memory";
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reg = <0x0 0x0 0x0 0x08000000>;
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};
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};
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&uart0 {
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status = "okay";
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};
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