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Qualcomm ARM64 DeviceTree updates for v6.9 

Four variants of Samsung Galaxy Core Prime and Grand Prime, built on
 MSM8916, and the Hardware Development Kit (HDK) for SM8550, are
 introduced.
 
 On X Elite audio and compute remoteprocs, IPCC, PCIe, AOSS QMP, SMP2P,
 TCSR, USB, display, audio, and soundwire support is introduced, and
 enabled across the CRD and QCP devices.
 
 For SM8650 PCIe controllers are moved to GIC-ITS and msi-map-mask is
 defined. Missing qlink-logging reserved-memory region is added for the
 modem remoteproc. FastRPC compute contexts are marked dma-coherent.
 Audio, USB Type-C and PM8010 support is introduced across MTP and QRD
 devices.
 
 GPU cooling devices are hooked up across MSM8916, MSM8939, SC8180X,
 SDM630, SDM845, SM6115, SM8150, SM8250, SM8350, and SM8550.
 
 UFS PHY clocks are corrected across MSM8996, MSM8998, SC8180X, SC8280XP,
 SDM845, SM6115, SM6125, SM8150, SM8250, SM8350, SM8550, and SM8650.
 
 PCI MSI interrupts are wired up across SM8150, SM8250, SM8350, SM8450,
 SM8550, SM8650, SC7280, and SC8180X
 
 On IPQ6018 QUP5 I2C, tsens sand thermal zones are defined. The Inline
 Crypto Engine (ICE) is enabled for IPQ9574.
 
 On MSM8953 the GPU and its IOMMU is introduced, the reset for the
 display subsystem is also wired up.
 
 VLS CLAMP registers are specified for USB3 PHYs on MSM8998, QCM2290, and
 SM6115.
 
 USB Type-C port management is enabled on QRB4210 RB2.
 
 On the SA8295P ADP the MAX20411 regulator powering the GPU rails is
 introduced and the GPU is enabled. The first PCI instance on SA8540P
 Ride is disabled for now, as a fix for the interrupt storm produced here
 has not been presented.
 
 On SA8775P the firmware memory map has changed and is updated. Safety
 IRQ is added to the Ethernet controller.
 
 On SC7180 UFS support is introduced and the cros-ec-spi is marked as
 wakeup source.
 
 For SC7280 capacity and DPC properties are added, cryptobam definition
 is improved to work in more firmware environments, more Chrome-specific
 properties are moved out from main dtsi, and cros-ec-spi is maked as a
 wakeup source. Slimbus definition is added to the platform.
 
 A missing reserved-memory range is added to Fairphone FP5, PMIC GLINK
 and Venus are enabled. LEDs are introduced and voltage settings
 corrected on the QCM6490 IDP, and RB3gen2 sees the same voltage changes
 and GCC protected clocks are introduced to make the board boot properly.
 
 RPMh sleep stats and a variety of cleanups and fixes are introduced for
 SC8180X.
 
 On SC8280XP the additional tsens instances are introduced. Camera
 Subsystem and Camera Control Interface (CCI) are added. PMIC die-temp
 vadc channels are introduced on the CRD, to allow ADC channels to be
 tied to the shared PMIC temp-alarms, to actually report temperature.
 
 On SDM630 USB QMP PHY support is introduced and enabled on the Inforce
 IFC6560 board. On the various Sony Xperia XA2 variants WLED is enabled
 and configured.
 
 On SM6350 display subsystem interconnects and tsens-based thermal zones
 are added. On SM7125 UFS support is added.
 
 On Fairphone FP4, on SM7225, display and GPU are enabled, and firmware
 paths are corrected.
 
 SM8150 PCIe controller definitions are corrected.
 
 As with SM8650, the SM8550 the fastrpc compute contexts are marked
 dm-coherent, and PCIe controllers are moved to use GIC-ITS. The UFS
 controller frequency definition is moved to the generic opp-table.
 Touchscreen is enabled on the QRD device.
 
 As usual, a variety of smaller cleanups and corrections to match
 DeviceTree bindings and style guidelines are introduced across the
 various files.
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Merge tag 'qcom-arm64-for-6.9' of https://git.kernel.org/pub/scm/linux/kernel/git/qcom/linux into soc/dt

Qualcomm ARM64 DeviceTree updates for v6.9

Four variants of Samsung Galaxy Core Prime and Grand Prime, built on
MSM8916, and the Hardware Development Kit (HDK) for SM8550, are
introduced.

On X Elite audio and compute remoteprocs, IPCC, PCIe, AOSS QMP, SMP2P,
TCSR, USB, display, audio, and soundwire support is introduced, and
enabled across the CRD and QCP devices.

For SM8650 PCIe controllers are moved to GIC-ITS and msi-map-mask is
defined. Missing qlink-logging reserved-memory region is added for the
modem remoteproc. FastRPC compute contexts are marked dma-coherent.
Audio, USB Type-C and PM8010 support is introduced across MTP and QRD
devices.

GPU cooling devices are hooked up across MSM8916, MSM8939, SC8180X,
SDM630, SDM845, SM6115, SM8150, SM8250, SM8350, and SM8550.

UFS PHY clocks are corrected across MSM8996, MSM8998, SC8180X, SC8280XP,
SDM845, SM6115, SM6125, SM8150, SM8250, SM8350, SM8550, and SM8650.

PCI MSI interrupts are wired up across SM8150, SM8250, SM8350, SM8450,
SM8550, SM8650, SC7280, and SC8180X

On IPQ6018 QUP5 I2C, tsens sand thermal zones are defined. The Inline
Crypto Engine (ICE) is enabled for IPQ9574.

On MSM8953 the GPU and its IOMMU is introduced, the reset for the
display subsystem is also wired up.

VLS CLAMP registers are specified for USB3 PHYs on MSM8998, QCM2290, and
SM6115.

USB Type-C port management is enabled on QRB4210 RB2.

On the SA8295P ADP the MAX20411 regulator powering the GPU rails is
introduced and the GPU is enabled. The first PCI instance on SA8540P
Ride is disabled for now, as a fix for the interrupt storm produced here
has not been presented.

On SA8775P the firmware memory map has changed and is updated. Safety
IRQ is added to the Ethernet controller.

On SC7180 UFS support is introduced and the cros-ec-spi is marked as
wakeup source.

For SC7280 capacity and DPC properties are added, cryptobam definition
is improved to work in more firmware environments, more Chrome-specific
properties are moved out from main dtsi, and cros-ec-spi is maked as a
wakeup source. Slimbus definition is added to the platform.

A missing reserved-memory range is added to Fairphone FP5, PMIC GLINK
and Venus are enabled. LEDs are introduced and voltage settings
corrected on the QCM6490 IDP, and RB3gen2 sees the same voltage changes
and GCC protected clocks are introduced to make the board boot properly.

RPMh sleep stats and a variety of cleanups and fixes are introduced for
SC8180X.

On SC8280XP the additional tsens instances are introduced. Camera
Subsystem and Camera Control Interface (CCI) are added. PMIC die-temp
vadc channels are introduced on the CRD, to allow ADC channels to be
tied to the shared PMIC temp-alarms, to actually report temperature.

On SDM630 USB QMP PHY support is introduced and enabled on the Inforce
IFC6560 board. On the various Sony Xperia XA2 variants WLED is enabled
and configured.

On SM6350 display subsystem interconnects and tsens-based thermal zones
are added. On SM7125 UFS support is added.

On Fairphone FP4, on SM7225, display and GPU are enabled, and firmware
paths are corrected.

SM8150 PCIe controller definitions are corrected.

As with SM8650, the SM8550 the fastrpc compute contexts are marked
dm-coherent, and PCIe controllers are moved to use GIC-ITS. The UFS
controller frequency definition is moved to the generic opp-table.
Touchscreen is enabled on the QRD device.

As usual, a variety of smaller cleanups and corrections to match
DeviceTree bindings and style guidelines are introduced across the
various files.

* tag 'qcom-arm64-for-6.9' of https://git.kernel.org/pub/scm/linux/kernel/git/qcom/linux: (176 commits)
  arm64: dts: qcom: sm6115: fix USB PHY configuration
  arm64: dts: sm8650: Add msi-map-mask for PCIe nodes
  arm64: dts: qcom: replace underscores in node names
  dt-bindings: arm: qcom: Add Samsung Galaxy Tab 4 10.1 LTE
  arm64: dts: qcom: pm4125: define USB-C related blocks
  arm64: dts: qcom: sa8540p-ride: disable pcie2a node
  arm64: dts: qcom: sc7280: add slimbus DT node
  arm64: dts: qcom: sc7280: Add capacity and DPC properties
  arm64: dts: qcom: pmi632: Add PBS client and use in LPG node
  arm64: dts: qcom: sm8550: Use GIC-ITS for PCIe0 and PCIe1
  arm64: dts: qcom: sm8150: correct PCIe wake-gpios
  arm64: dts: qcom: sdm845-db845c: correct PCIe wake-gpios
  arm64: dts: qcom: sm7225-fairphone-fp4: Enable display and GPU
  arm64: dts: qcom: sm6350: Remove "disabled" state of GMU
  arm64: dts: qcom: msm8916-samsung-fortuna/rossa: Add fuel gauge
  arm64: dts: qcom: sm6350: Add interconnect for MDSS
  arm64: dts: qcom: msm8916-samsung-fortuna/rossa: Add initial device trees
  arm64: dts: qcom: sm8550: Switch UFS from opp-table-hz to opp-v2
  arm64: dts: qcom: sc8180x: describe all PCI MSI interrupts
  arm64: dts: qcom: minor whitespace cleanup
  ...

Link: https://lore.kernel.org/r/20240225050146.484422-1-andersson@kernel.org
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
This commit is contained in:
Arnd Bergmann 2024-03-01 11:15:59 +01:00
parent 8511eaf682 f176168bcb
commit aefe054f2c
95 changed files with 8352 additions and 587 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

58
Documentation/devicetree/bindings/arm/qcom.yaml
View File

@ -10,17 +10,10 @@ maintainers:
- Bjorn Andersson <bjorn.andersson@linaro.org>
description: |
Some qcom based bootloaders identify the dtb blob based on a set of
device properties like SoC and platform and revisions of those components.
To support this scheme, we encode this information into the board compatible
string.
Each board must specify a top-level board compatible string with the following
format:
compatible = "qcom,<SoC>[-<soc_version>][-<foundry_id>]-<board>[/<subtype>][-<board_version>]"
The 'SoC' and 'board' elements are required. All other elements are optional.
For devices using the Qualcomm SoC the "compatible" properties consists of
one or several "manufacturer,model" strings, describing the device itself,
followed by one or several "qcom,<SoC>" strings, describing the SoC used in
the device.
The 'SoC' element must be one of the following strings:
@ -90,43 +83,9 @@ description: |
sm8650
x1e80100
The 'board' element must be one of the following strings:
adp
cdp
dragonboard
idp
liquid
mtp
qcp
qrd
rb2
ride
sbc
x100
The 'soc_version' and 'board_version' elements take the form of v<Major>.<Minor>
where the minor number may be omitted when it's zero, i.e. v1.0 is the same
as v1. If all versions of the 'board_version' elements match, then a
wildcard '*' should be used, e.g. 'v*'.
The 'foundry_id' and 'subtype' elements are one or more digits from 0 to 9.
Examples:
"qcom,msm8916-v1-cdp-pm8916-v2.1"
A CDP board with an msm8916 SoC, version 1 paired with a pm8916 PMIC of version
2.1.
"qcom,apq8074-v2.0-2-dragonboard/1-v0.1"
A dragonboard board v0.1 of subtype 1 with an apq8074 SoC version 2, made in
foundry 2.
There are many devices in the list below that run the standard ChromeOS
bootloader setup and use the open source depthcharge bootloader to boot the
OS. These devices do not use the scheme described above. For details, see:
OS. These devices use the bootflow explained at
https://docs.kernel.org/arch/arm/google/chromebook-boot-flow.html
properties:
@ -187,6 +146,7 @@ properties:
- microsoft,superman-lte
- microsoft,tesla
- motorola,peregrine
- samsung,matisselte
- const: qcom,msm8926
- const: qcom,msm8226
@ -244,11 +204,15 @@ properties:
- samsung,a5u-eur
- samsung,e5
- samsung,e7
- samsung,fortuna3g
- samsung,gprimeltecan
- samsung,grandmax
- samsung,grandprimelte
- samsung,gt510
- samsung,gt58
- samsung,j5
- samsung,j5x
- samsung,rossa
- samsung,serranove
- thwc,uf896
- thwc,ufi001c
@ -988,6 +952,7 @@ properties:
- items:
- enum:
- xiaomi,curtana
- xiaomi,joyeuse
- const: qcom,sm7125
@ -1035,6 +1000,7 @@ properties:
- items:
- enum:
- qcom,sm8550-hdk
- qcom,sm8550-mtp
- qcom,sm8550-qrd
- const: qcom,sm8550

7
Documentation/devicetree/bindings/clock/qcom,gcc-sc8180x.yaml
View File

@ -31,10 +31,15 @@ properties:
- const: bi_tcxo_ao
- const: sleep_clk
power-domains:
items:
- description: CX domain
required:
- compatible
- clocks
- clock-names
- power-domains
allOf:
- $ref: qcom,gcc.yaml#
@ -44,6 +49,7 @@ unevaluatedProperties: false
examples:
- |
#include <dt-bindings/clock/qcom,rpmh.h>
#include <dt-bindings/power/qcom-rpmpd.h>
clock-controller@100000 {
compatible = "qcom,gcc-sc8180x";
reg = <0x00100000 0x1f0000>;
@ -51,6 +57,7 @@ examples:
<&rpmhcc RPMH_CXO_CLK_A>,
<&sleep_clk>;
clock-names = "bi_tcxo", "bi_tcxo_ao", "sleep_clk";
power-domains = <&rpmhpd SC8180X_CX>;
#clock-cells = <1>;
#reset-cells = <1>;
#power-domain-cells = <1>;

2
Documentation/devicetree/bindings/clock/qcom,sm8450-camcc.yaml
View File

@ -17,6 +17,7 @@ description: |
include/dt-bindings/clock/qcom,sm8450-camcc.h
include/dt-bindings/clock/qcom,sm8550-camcc.h
include/dt-bindings/clock/qcom,sc8280xp-camcc.h
include/dt-bindings/clock/qcom,x1e80100-camcc.h
allOf:
- $ref: qcom,gcc.yaml#
@ -27,6 +28,7 @@ properties:
- qcom,sc8280xp-camcc
- qcom,sm8450-camcc
- qcom,sm8550-camcc
- qcom,x1e80100-camcc
clocks:
items:

2
Documentation/devicetree/bindings/clock/qcom,sm8450-gpucc.yaml
View File

@ -18,6 +18,7 @@ description: |
include/dt-bindings/clock/qcom,sm8550-gpucc.h
include/dt-bindings/reset/qcom,sm8450-gpucc.h
include/dt-bindings/reset/qcom,sm8650-gpucc.h
include/dt-bindings/reset/qcom,x1e80100-gpucc.h
properties:
compatible:
@ -25,6 +26,7 @@ properties:
- qcom,sm8450-gpucc
- qcom,sm8550-gpucc
- qcom,sm8650-gpucc
- qcom,x1e80100-gpucc
clocks:
items:

7
Documentation/devicetree/bindings/clock/qcom,sm8550-dispcc.yaml
View File

@ -14,12 +14,17 @@ description: |
Qualcomm display clock control module provides the clocks, resets and power
domains on SM8550.
See also:: include/dt-bindings/clock/qcom,sm8550-dispcc.h
See also:
- include/dt-bindings/clock/qcom,sm8550-dispcc.h
- include/dt-bindings/clock/qcom,sm8650-dispcc.h
- include/dt-bindings/clock/qcom,x1e80100-dispcc.h
properties:
compatible:
enum:
- qcom,sm8550-dispcc
- qcom,sm8650-dispcc
- qcom,x1e80100-dispcc
clocks:
items:

1
Documentation/devicetree/bindings/clock/qcom,sm8550-tcsr.yaml
View File

@ -23,6 +23,7 @@ properties:
- enum:
- qcom,sm8550-tcsr
- qcom,sm8650-tcsr
- qcom,x1e80100-tcsr
- const: syscon
clocks:

106
Documentation/devicetree/bindings/clock/qcom,sm8650-dispcc.yaml
View File

@ -1,106 +0,0 @@
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/clock/qcom,sm8650-dispcc.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Qualcomm Display Clock & Reset Controller for SM8650
maintainers:
- Bjorn Andersson <andersson@kernel.org>
- Neil Armstrong <neil.armstrong@linaro.org>
description: |
Qualcomm display clock control module provides the clocks, resets and power
domains on SM8650.
See also:: include/dt-bindings/clock/qcom,sm8650-dispcc.h
properties:
compatible:
enum:
- qcom,sm8650-dispcc
clocks:
items:
- description: Board XO source
- description: Board Always On XO source
- description: Display's AHB clock
- description: sleep clock
- description: Byte clock from DSI PHY0
- description: Pixel clock from DSI PHY0
- description: Byte clock from DSI PHY1
- description: Pixel clock from DSI PHY1
- description: Link clock from DP PHY0
- description: VCO DIV clock from DP PHY0
- description: Link clock from DP PHY1
- description: VCO DIV clock from DP PHY1
- description: Link clock from DP PHY2
- description: VCO DIV clock from DP PHY2
- description: Link clock from DP PHY3
- description: VCO DIV clock from DP PHY3
'#clock-cells':
const: 1
'#reset-cells':
const: 1
'#power-domain-cells':
const: 1
reg:
maxItems: 1
power-domains:
description:
A phandle and PM domain specifier for the MMCX power domain.
maxItems: 1
required-opps:
description:
A phandle to an OPP node describing required MMCX performance point.
maxItems: 1
required:
- compatible
- reg
- clocks
- '#clock-cells'
- '#reset-cells'
- '#power-domain-cells'
additionalProperties: false
examples:
- |
#include <dt-bindings/clock/qcom,sm8650-gcc.h>
#include <dt-bindings/clock/qcom,rpmh.h>
#include <dt-bindings/power/qcom-rpmpd.h>
#include <dt-bindings/power/qcom,rpmhpd.h>
clock-controller@af00000 {
compatible = "qcom,sm8650-dispcc";
reg = <0x0af00000 0x10000>;
clocks = <&rpmhcc RPMH_CXO_CLK>,
<&rpmhcc RPMH_CXO_CLK_A>,
<&gcc GCC_DISP_AHB_CLK>,
<&sleep_clk>,
<&dsi0_phy 0>,
<&dsi0_phy 1>,
<&dsi1_phy 0>,
<&dsi1_phy 1>,
<&dp0_phy 0>,
<&dp0_phy 1>,
<&dp1_phy 0>,
<&dp1_phy 1>,
<&dp2_phy 0>,
<&dp2_phy 1>,
<&dp3_phy 0>,
<&dp3_phy 1>;
#clock-cells = <1>;
#reset-cells = <1>;
#power-domain-cells = <1>;
power-domains = <&rpmhpd RPMHPD_MMCX>;
required-opps = <&rpmhpd_opp_low_svs>;
};
...

14
arch/arm/boot/dts/qcom/qcom-sdx55.dtsi
View File

@ -580,12 +580,16 @@
<&gcc GCC_USB30_MASTER_CLK>;
assigned-clock-rates = <19200000>, <200000000>;
interrupts-extended = <&intc GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>,
<&pdc 51 IRQ_TYPE_LEVEL_HIGH>,
interrupts-extended = <&intc GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>,
<&intc GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>,
<&pdc 10 IRQ_TYPE_EDGE_BOTH>,
<&pdc 11 IRQ_TYPE_EDGE_BOTH>,
<&pdc 10 IRQ_TYPE_EDGE_BOTH>;
interrupt-names = "hs_phy_irq", "ss_phy_irq",
"dm_hs_phy_irq", "dp_hs_phy_irq";
<&pdc 51 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "pwr_event",
"hs_phy_irq",
"dp_hs_phy_irq",
"dm_hs_phy_irq",
"ss_phy_irq";
power-domains = <&gcc USB30_GDSC>;

14
arch/arm/boot/dts/qcom/qcom-sdx65.dtsi
View File

@ -501,14 +501,16 @@
<&gcc GCC_USB30_MASTER_CLK>;
assigned-clock-rates = <19200000>, <200000000>;
interrupts-extended = <&intc GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>,
<&pdc 76 IRQ_TYPE_LEVEL_HIGH>,
interrupts-extended = <&intc GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>,
<&intc GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>,
<&pdc 19 IRQ_TYPE_EDGE_BOTH>,
<&pdc 18 IRQ_TYPE_EDGE_BOTH>,
<&pdc 19 IRQ_TYPE_EDGE_BOTH>;
interrupt-names = "hs_phy_irq",
"ss_phy_irq",
<&pdc 76 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "pwr_event",
"hs_phy_irq",
"dp_hs_phy_irq",
"dm_hs_phy_irq",
"dp_hs_phy_irq";
"ss_phy_irq";
power-domains = <&gcc USB30_GDSC>;

6
arch/arm64/boot/dts/qcom/Makefile
View File

@ -23,6 +23,7 @@ dtb-$(CONFIG_ARCH_QCOM) += ipq9574-rdp433.dtb
dtb-$(CONFIG_ARCH_QCOM) += ipq9574-rdp449.dtb
dtb-$(CONFIG_ARCH_QCOM) += ipq9574-rdp453.dtb
dtb-$(CONFIG_ARCH_QCOM) += ipq9574-rdp454.dtb
dtb-$(CONFIG_ARCH_QCOM) += msm8216-samsung-fortuna3g.dtb
dtb-$(CONFIG_ARCH_QCOM) += msm8916-acer-a1-724.dtb
dtb-$(CONFIG_ARCH_QCOM) += msm8916-alcatel-idol347.dtb
dtb-$(CONFIG_ARCH_QCOM) += msm8916-asus-z00l.dtb
@ -35,11 +36,14 @@ dtb-$(CONFIG_ARCH_QCOM) += msm8916-samsung-a3u-eur.dtb
dtb-$(CONFIG_ARCH_QCOM) += msm8916-samsung-a5u-eur.dtb
dtb-$(CONFIG_ARCH_QCOM) += msm8916-samsung-e5.dtb
dtb-$(CONFIG_ARCH_QCOM) += msm8916-samsung-e7.dtb
dtb-$(CONFIG_ARCH_QCOM) += msm8916-samsung-gprimeltecan.dtb
dtb-$(CONFIG_ARCH_QCOM) += msm8916-samsung-grandmax.dtb
dtb-$(CONFIG_ARCH_QCOM) += msm8916-samsung-grandprimelte.dtb
dtb-$(CONFIG_ARCH_QCOM) += msm8916-samsung-gt510.dtb
dtb-$(CONFIG_ARCH_QCOM) += msm8916-samsung-gt58.dtb
dtb-$(CONFIG_ARCH_QCOM) += msm8916-samsung-j5.dtb
dtb-$(CONFIG_ARCH_QCOM) += msm8916-samsung-j5x.dtb
dtb-$(CONFIG_ARCH_QCOM) += msm8916-samsung-rossa.dtb
dtb-$(CONFIG_ARCH_QCOM) += msm8916-samsung-serranove.dtb
dtb-$(CONFIG_ARCH_QCOM) += msm8916-thwc-uf896.dtb
dtb-$(CONFIG_ARCH_QCOM) += msm8916-thwc-ufi001c.dtb
@ -210,6 +214,7 @@ dtb-$(CONFIG_ARCH_QCOM) += sm6125-sony-xperia-seine-pdx201.dtb
dtb-$(CONFIG_ARCH_QCOM) += sm6125-xiaomi-laurel-sprout.dtb
dtb-$(CONFIG_ARCH_QCOM) += sm6350-sony-xperia-lena-pdx213.dtb
dtb-$(CONFIG_ARCH_QCOM) += sm6375-sony-xperia-murray-pdx225.dtb
dtb-$(CONFIG_ARCH_QCOM) += sm7125-xiaomi-curtana.dtb
dtb-$(CONFIG_ARCH_QCOM) += sm7125-xiaomi-joyeuse.dtb
dtb-$(CONFIG_ARCH_QCOM) += sm7225-fairphone-fp4.dtb
dtb-$(CONFIG_ARCH_QCOM) += sm8150-hdk.dtb
@ -233,6 +238,7 @@ dtb-$(CONFIG_ARCH_QCOM) += sm8450-hdk.dtb
dtb-$(CONFIG_ARCH_QCOM) += sm8450-qrd.dtb
dtb-$(CONFIG_ARCH_QCOM) += sm8450-sony-xperia-nagara-pdx223.dtb
dtb-$(CONFIG_ARCH_QCOM) += sm8450-sony-xperia-nagara-pdx224.dtb
dtb-$(CONFIG_ARCH_QCOM) += sm8550-hdk.dtb
dtb-$(CONFIG_ARCH_QCOM) += sm8550-mtp.dtb
dtb-$(CONFIG_ARCH_QCOM) += sm8550-qrd.dtb
dtb-$(CONFIG_ARCH_QCOM) += sm8650-mtp.dtb

8
arch/arm64/boot/dts/qcom/apq8016-sbc-d3-camera-mezzanine.dts
View File

@ -9,7 +9,7 @@
#include "apq8016-sbc.dts"
/ {
camera_vdddo_1v8: camera-vdddo-1v8 {
camera_vdddo_1v8: regulator-camera-vdddo {
compatible = "regulator-fixed";
regulator-name = "camera_vdddo";
regulator-min-microvolt = <1800000>;
@ -17,7 +17,7 @@
regulator-always-on;
};
camera_vdda_2v8: camera-vdda-2v8 {
camera_vdda_2v8: regulator-camera-vdda {
compatible = "regulator-fixed";
regulator-name = "camera_vdda";
regulator-min-microvolt = <2800000>;
@ -25,7 +25,7 @@
regulator-always-on;
};
camera_vddd_1v5: camera-vddd-1v5 {
camera_vddd_1v5: regulator-camera-vddd {
compatible = "regulator-fixed";
regulator-name = "camera_vddd";
regulator-min-microvolt = <1500000>;
@ -53,7 +53,7 @@
};
&cci_i2c0 {
camera_rear@3b {
camera@3b {
compatible = "ovti,ov5640";
reg = <0x3b>;

8
arch/arm64/boot/dts/qcom/ipq5332.dtsi
View File

@ -320,8 +320,12 @@
compatible = "qcom,ipq5332-dwc3", "qcom,dwc3";
reg = <0x08af8800 0x400>;
interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "hs_phy_irq";
interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 53 IRQ_TYPE_EDGE_BOTH>,
<GIC_SPI 52 IRQ_TYPE_EDGE_BOTH>;
interrupt-names = "pwr_event",
"dp_hs_phy_irq",
"dm_hs_phy_irq";
clocks = <&gcc GCC_USB0_MASTER_CLK>,
<&gcc GCC_SNOC_USB_CLK>,

159
arch/arm64/boot/dts/qcom/ipq6018.dtsi
View File

@ -9,6 +9,7 @@
#include <dt-bindings/clock/qcom,gcc-ipq6018.h>
#include <dt-bindings/reset/qcom,gcc-ipq6018.h>
#include <dt-bindings/clock/qcom,apss-ipq.h>
#include <dt-bindings/thermal/thermal.h>
/ {
#address-cells = <2>;
@ -43,6 +44,7 @@
clock-names = "cpu";
operating-points-v2 = <&cpu_opp_table>;
cpu-supply = <&ipq6018_s2>;
#cooling-cells = <2>;
};
CPU1: cpu@1 {
@ -55,6 +57,7 @@
clock-names = "cpu";
operating-points-v2 = <&cpu_opp_table>;
cpu-supply = <&ipq6018_s2>;
#cooling-cells = <2>;
};
CPU2: cpu@2 {
@ -67,6 +70,7 @@
clock-names = "cpu";
operating-points-v2 = <&cpu_opp_table>;
cpu-supply = <&ipq6018_s2>;
#cooling-cells = <2>;
};
CPU3: cpu@3 {
@ -79,6 +83,7 @@
clock-names = "cpu";
operating-points-v2 = <&cpu_opp_table>;
cpu-supply = <&ipq6018_s2>;
#cooling-cells = <2>;
};
L2_0: l2-cache {
@ -330,6 +335,16 @@
clock-names = "core";
};
tsens: thermal-sensor@4a9000 {
compatible = "qcom,ipq6018-tsens", "qcom,ipq8074-tsens";
reg = <0x0 0x004a9000 0x0 0x1000>,
<0x0 0x004a8000 0x0 0x1000>;
interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "combined";
#qcom,sensors = <16>;
#thermal-sensor-cells = <1>;
};
cryptobam: dma-controller@704000 {
compatible = "qcom,bam-v1.7.0";
reg = <0x0 0x00704000 0x0 0x20000>;
@ -418,6 +433,12 @@
<&gcc GCC_USB1_MOCK_UTMI_CLK>;
assigned-clock-rates = <133330000>,
<24000000>;
interrupts = <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "pwr_event",
"qusb2_phy";
resets = <&gcc GCC_USB1_BCR>;
status = "disabled";
@ -578,6 +599,21 @@
status = "disabled";
};
blsp1_i2c6: i2c@78ba000 {
compatible = "qcom,i2c-qup-v2.2.1";
#address-cells = <1>;
#size-cells = <0>;
reg = <0x0 0x078ba000 0x0 0x600>;
interrupts = <GIC_SPI 300 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&gcc GCC_BLSP1_QUP6_I2C_APPS_CLK>,
<&gcc GCC_BLSP1_AHB_CLK>;
clock-names = "core", "iface";
clock-frequency = <400000>;
dmas = <&blsp_dma 22>, <&blsp_dma 23>;
dma-names = "tx", "rx";
status = "disabled";
};
qpic_bam: dma-controller@7984000 {
compatible = "qcom,bam-v1.7.0";
reg = <0x0 0x07984000 0x0 0x1a000>;
@ -630,6 +666,13 @@
<133330000>,
<24000000>;
interrupts = <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "pwr_event",
"qusb2_phy",
"ss_phy_irq";
resets = <&gcc GCC_USB0_BCR>;
status = "disabled";
@ -867,6 +910,122 @@
};
};
thermal-zones {
nss-top-thermal {
polling-delay-passive = <250>;
polling-delay = <1000>;
thermal-sensors = <&tsens 4>;
trips {
nss-top-critical {
temperature = <125000>;
hysteresis = <1000>;
type = "critical";
};
};
};
nss-thermal {
polling-delay-passive = <250>;
polling-delay = <1000>;
thermal-sensors = <&tsens 5>;
trips {
nss-critical {
temperature = <125000>;
hysteresis = <1000>;
type = "critical";
};
};
};
wcss-phya0-thermal {
polling-delay-passive = <250>;
polling-delay = <1000>;
thermal-sensors = <&tsens 7>;
trips {
wcss-phya0-critical {
temperature = <125000>;
hysteresis = <1000>;
type = "critical";
};
};
};
wcss-phya1-thermal {
polling-delay-passive = <250>;
polling-delay = <1000>;
thermal-sensors = <&tsens 8>;
trips {
wcss-phya1-critical {
temperature = <125000>;
hysteresis = <1000>;
type = "critical";
};
};
};
cpu-thermal {
polling-delay-passive = <250>;
polling-delay = <1000>;
thermal-sensors = <&tsens 13>;
trips {
cpu-critical {
temperature = <125000>;
hysteresis = <1000>;
type = "critical";
};
cpu_alert: cpu-passive {
temperature = <110000>;
hysteresis = <1000>;
type = "passive";
};
};
cooling-maps {
map0 {
trip = <&cpu_alert>;
cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
};
};
};
lpass-thermal {
polling-delay-passive = <250>;
polling-delay = <1000>;
thermal-sensors = <&tsens 14>;
trips {
lpass-critical {
temperature = <125000>;
hysteresis = <1000>;
type = "critical";
};
};
};
ddrss-top-thermal {
polling-delay-passive = <250>;
polling-delay = <1000>;
thermal-sensors = <&tsens 15>;
trips {
ddrss-top-critical {
temperature = <125000>;
hysteresis = <1000>;
type = "critical";
};
};
};
};
timer {
compatible = "arm,armv8-timer";
interrupts = <GIC_PPI 2 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,

16
arch/arm64/boot/dts/qcom/ipq8074.dtsi
View File

@ -252,6 +252,8 @@
clocks = <&gcc GCC_MDIO_AHB_CLK>;
clock-names = "gcc_mdio_ahb_clk";
clock-frequency = <6250000>;
status = "disabled";
};
@ -627,6 +629,13 @@
<133330000>,
<19200000>;
interrupts = <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "pwr_event",
"qusb2_phy",
"ss_phy_irq";
power-domains = <&gcc USB0_GDSC>;
resets = <&gcc GCC_USB0_BCR>;
@ -669,6 +678,13 @@
<133330000>,
<19200000>;
interrupts = <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 225 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "pwr_event",
"qusb2_phy",
"ss_phy_irq";
power-domains = <&gcc USB1_GDSC>;
resets = <&gcc GCC_USB1_BCR>;

12
arch/arm64/boot/dts/qcom/ipq9574.dtsi
View File

@ -321,8 +321,10 @@
sdhc_1: mmc@7804000 {
compatible = "qcom,ipq9574-sdhci", "qcom,sdhci-msm-v5";
reg = <0x07804000 0x1000>, <0x07805000 0x1000>;
reg-names = "hc", "cqhci";
reg = <0x07804000 0x1000>,
<0x07805000 0x1000>,
<0x07808000 0x2000>;
reg-names = "hc", "cqhci", "ice";
interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>;
@ -330,9 +332,11 @@
clocks = <&gcc GCC_SDCC1_AHB_CLK>,
<&gcc GCC_SDCC1_APPS_CLK>,
<&xo_board_clk>;
clock-names = "iface", "core", "xo";
<&xo_board_clk>,
<&gcc GCC_SDCC1_ICE_CORE_CLK>;
clock-names = "iface", "core", "xo", "ice";
non-removable;
supports-cqe;
status = "disabled";
};

11
arch/arm64/boot/dts/qcom/msm8216-samsung-fortuna3g.dts Normal file
View File

@ -0,0 +1,11 @@
// SPDX-License-Identifier: GPL-2.0-only
/dts-v1/;
#include "msm8916-samsung-fortuna-common.dtsi"
/ {
model = "Samsung Galaxy Grand Prime (SM-G530H)";
compatible = "samsung,fortuna3g", "qcom,msm8916";
chassis-type = "handset";
};

203
arch/arm64/boot/dts/qcom/msm8916-samsung-fortuna-common.dtsi Normal file
View File

@ -0,0 +1,203 @@
// SPDX-License-Identifier: GPL-2.0-only
#include "msm8916-pm8916.dtsi"
#include "msm8916-modem-qdsp6.dtsi"
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/input/input.h>
#include <dt-bindings/interrupt-controller/irq.h>
/ {
aliases {
mmc0 = &sdhc_1; /* eMMC */
mmc1 = &sdhc_2; /* SD card */
serial0 = &blsp_uart2;
};
chosen {
stdout-path = "serial0";
};
reserved-memory {
/* Additional memory used by Samsung firmware modifications */
tz-apps@85a00000 {
reg = <0x0 0x85a00000 0x0 0x600000>;
no-map;
};
};
gpio-keys {
compatible = "gpio-keys";
pinctrl-0 = <&gpio_keys_default>;
pinctrl-names = "default";
label = "GPIO Buttons";
button-volume-up {
label = "Volume Up";
gpios = <&tlmm 107 GPIO_ACTIVE_LOW>;
linux,code = <KEY_VOLUMEUP>;
};
button-home {
label = "Home";
gpios = <&tlmm 109 GPIO_ACTIVE_LOW>;
linux,code = <KEY_HOMEPAGE>;
};
};
haptic {
compatible = "regulator-haptic";
haptic-supply = <&reg_motor_vdd>;
min-microvolt = <3300000>;
max-microvolt = <3300000>;
};
reg_motor_vdd: regulator-motor-vdd {
compatible = "regulator-fixed";
regulator-name = "motor_vdd";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
gpio = <&tlmm 72 GPIO_ACTIVE_HIGH>;
enable-active-high;
pinctrl-0 = <&motor_en_default>;
pinctrl-names = "default";
};
};
&blsp_i2c1 {
status = "okay";
muic: extcon@25 {
compatible = "siliconmitus,sm5502-muic";
reg = <0x25>;
interrupts-extended = <&tlmm 12 IRQ_TYPE_EDGE_FALLING>;
pinctrl-0 = <&muic_int_default>;
pinctrl-names = "default";
};
};
&blsp_i2c4 {
status = "okay";
fuel-gauge@35 {
compatible = "richtek,rt5033-battery";
reg = <0x35>;
interrupts-extended = <&tlmm 121 IRQ_TYPE_EDGE_FALLING>;
pinctrl-0 = <&fg_alert_default>;
pinctrl-names = "default";
};
};
&blsp_uart2 {
status = "okay";
};
&mpss_mem {
reg = <0x0 0x86800000 0x0 0x5000000>;
};
&pm8916_resin {
linux,code = <KEY_VOLUMEDOWN>;
status = "okay";
};
&pm8916_rpm_regulators {
pm8916_l17: l17 {
regulator-min-microvolt = <2850000>;
regulator-max-microvolt = <2850000>;
};
};
&sdhc_1 {
status = "okay";
};
&sdhc_2 {
pinctrl-0 = <&sdc2_default &sdc2_cd_default>;
pinctrl-1 = <&sdc2_sleep &sdc2_cd_default>;
pinctrl-names = "default", "sleep";
cd-gpios = <&tlmm 38 GPIO_ACTIVE_LOW>;
status = "okay";
};
&sound {
model = "msm8916-1mic";
audio-routing =
"AMIC1", "MIC BIAS External1",
"AMIC2", "MIC BIAS Internal2",
"AMIC3", "MIC BIAS External1";
};
&usb {
extcon = <&muic>, <&muic>;
status = "okay";
};
&usb_hs_phy {
extcon = <&muic>;
};
&venus {
status = "okay";
};
&venus_mem {
status = "okay";
};
&wcnss {
status = "okay";
};
&wcnss_iris {
compatible = "qcom,wcn3620";
};
&wcnss_mem {
status = "okay";
};
&tlmm {
fg_alert_default: fg-alert-default-state {
pins = "gpio121";
function = "gpio";
drive-strength = <2>;
bias-disable;
};
gpio_keys_default: gpio-keys-default-state {
pins = "gpio107", "gpio109";
function = "gpio";
drive-strength = <2>;
bias-pull-up;
};
motor_en_default: motor-en-default-state {
pins = "gpio72";
function = "gpio";
drive-strength = <2>;
bias-disable;
};
muic_int_default: muic-int-default-state {
pins = "gpio12";
function = "gpio";
drive-strength = <2>;
bias-disable;
};
sdc2_cd_default: sdc2-cd-default-state {
pins = "gpio38";
function = "gpio";
drive-strength = <2>;
bias-disable;
};
};

27
arch/arm64/boot/dts/qcom/msm8916-samsung-gprimeltecan.dts Normal file
View File

@ -0,0 +1,27 @@
// SPDX-License-Identifier: GPL-2.0-only
/dts-v1/;
#include "msm8916-samsung-fortuna-common.dtsi"
/ {
model = "Samsung Galaxy Grand Prime (SM-G530W)";
compatible = "samsung,gprimeltecan", "qcom,msm8916";
chassis-type = "handset";
reserved-memory {
/* Firmware for gprimeltecan needs more space */
/delete-node/ tz-apps@85a00000;
/* Additional memory used by Samsung firmware modifications */
tz-apps@85500000 {
reg = <0x0 0x85500000 0x0 0xb00000>;
no-map;
};
};
};
&mpss_mem {
/* Firmware for gprimeltecan needs more space */
reg = <0x0 0x86800000 0x0 0x5400000>;
};

16
arch/arm64/boot/dts/qcom/msm8916-samsung-grandprimelte.dts Normal file
View File

@ -0,0 +1,16 @@
// SPDX-License-Identifier: GPL-2.0-only
/dts-v1/;
#include "msm8916-samsung-fortuna-common.dtsi"
/ {
model = "Samsung Galaxy Grand Prime (SM-G530FZ)";
compatible = "samsung,grandprimelte", "qcom,msm8916";
chassis-type = "handset";
};
&mpss_mem {
/* Firmware for grandprimelte needs more space */
reg = <0x0 0x86800000 0x0 0x5400000>;
};

16
arch/arm64/boot/dts/qcom/msm8916-samsung-rossa-common.dtsi Normal file
View File

@ -0,0 +1,16 @@
// SPDX-License-Identifier: GPL-2.0-only
#include "msm8916-samsung-fortuna-common.dtsi"
/* SM5504 MUIC instead of SM5502 */
/delete-node/ &muic;
&blsp_i2c1 {
muic: extcon@14 {
compatible = "siliconmitus,sm5504-muic";
reg = <0x14>;
interrupts-extended = <&tlmm 12 IRQ_TYPE_EDGE_FALLING>;
pinctrl-0 = <&muic_int_default>;
pinctrl-names = "default";
};
};

16
arch/arm64/boot/dts/qcom/msm8916-samsung-rossa.dts Normal file
View File

@ -0,0 +1,16 @@
// SPDX-License-Identifier: GPL-2.0-only
/dts-v1/;
#include "msm8916-samsung-rossa-common.dtsi"
/ {
model = "Samsung Galaxy Core Prime LTE";
compatible = "samsung,rossa", "qcom,msm8916";
chassis-type = "handset";
};
&mpss_mem {
/* Firmware for rossa needs more space */
reg = <0x0 0x86800000 0x0 0x5800000>;
};

9
arch/arm64/boot/dts/qcom/msm8916.dtsi
View File

@ -1785,6 +1785,8 @@
power-domains = <&gcc OXILI_GDSC>;
operating-points-v2 = <&gpu_opp_table>;
iommus = <&gpu_iommu 1>, <&gpu_iommu 2>;
#cooling-cells = <2>;
status = "disabled";
gpu_opp_table: opp-table {
@ -2688,6 +2690,13 @@
thermal-sensors = <&tsens 2>;
cooling-maps {
map0 {
trip = <&gpu_alert0>;
cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
};
};
trips {
gpu_alert0: trip-point0 {
temperature = <75000>;

11
arch/arm64/boot/dts/qcom/msm8939.dtsi
View File

@ -1427,6 +1427,8 @@
power-domains = <&gcc OXILI_GDSC>;
operating-points-v2 = <&opp_table>;
iommus = <&gpu_iommu 1>, <&gpu_iommu 2>;
#cooling-cells = <2>;
status = "disabled";
opp_table: opp-table {
@ -2456,6 +2458,13 @@
thermal-sensors = <&tsens 3>;
cooling-maps {
map0 {
trip = <&gpu_alert0>;
cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
};
};
trips {
gpu_alert0: trip-point0 {
temperature = <75000>;
@ -2463,7 +2472,7 @@
type = "passive";
};
gpu_crit: gpu_crit {
gpu_crit: gpu-crit {
temperature = <95000>;
hysteresis = <2000>;
type = "critical";

155
arch/arm64/boot/dts/qcom/msm8953.dtsi
View File

@ -859,6 +859,8 @@
"vsync",
"core";
resets = <&gcc GCC_MDSS_BCR>;
#address-cells = <1>;
#size-cells = <1>;
ranges;
@ -1044,6 +1046,125 @@
};
};
gpu: gpu@1c00000 {
compatible = "qcom,adreno-506.0", "qcom,adreno";
reg = <0x01c00000 0x40000>;
reg-names = "kgsl_3d0_reg_memory";
interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&gcc GCC_OXILI_GFX3D_CLK>,
<&gcc GCC_OXILI_AHB_CLK>,
<&gcc GCC_BIMC_GFX_CLK>,
<&gcc GCC_BIMC_GPU_CLK>,
<&gcc GCC_OXILI_TIMER_CLK>,
<&gcc GCC_OXILI_AON_CLK>;
clock-names = "core",
"iface",
"mem_iface",
"alt_mem_iface",
"rbbmtimer",
"alwayson";
power-domains = <&gcc OXILI_GX_GDSC>;
iommus = <&gpu_iommu 0>;
operating-points-v2 = <&gpu_opp_table>;
#cooling-cells = <2>;
status = "disabled";
zap-shader {
memory-region = <&zap_shader_region>;
};
gpu_opp_table: opp-table {
compatible = "operating-points-v2";
opp-19200000 {
opp-hz = /bits/ 64 <19200000>;
opp-supported-hw = <0xff>;
required-opps = <&rpmpd_opp_min_svs>;
};
opp-133300000 {
opp-hz = /bits/ 64 <133300000>;
opp-supported-hw = <0xff>;
required-opps = <&rpmpd_opp_min_svs>;
};
opp-216000000 {
opp-hz = /bits/ 64 <216000000>;
opp-supported-hw = <0xff>;
required-opps = <&rpmpd_opp_low_svs>;
};
opp-320000000 {
opp-hz = /bits/ 64 <320000000>;
opp-supported-hw = <0xff>;
required-opps = <&rpmpd_opp_svs>;
};
opp-400000000 {
opp-hz = /bits/ 64 <400000000>;
opp-supported-hw = <0xff>;
required-opps = <&rpmpd_opp_svs_plus>;
};
opp-510000000 {
opp-hz = /bits/ 64 <510000000>;
opp-supported-hw = <0xff>;
required-opps = <&rpmpd_opp_nom>;
};
opp-560000000 {
opp-hz = /bits/ 64 <560000000>;
opp-supported-hw = <0xff>;
required-opps = <&rpmpd_opp_nom_plus>;
};
/*
* This opp is only available on msm8953 and
* sdm632, the max for sdm450 is 600MHz.
*/
opp-650000000 {
opp-hz = /bits/ 64 <650000000>;
opp-supported-hw = <0xff>;
required-opps = <&rpmpd_opp_turbo>;
};
};
};
gpu_iommu: iommu@1c48000 {
compatible = "qcom,msm8953-iommu", "qcom,msm-iommu-v2";
ranges = <0 0x01c48000 0x8000>;
clocks = <&gcc GCC_OXILI_AHB_CLK>,
<&gcc GCC_BIMC_GFX_CLK>;
clock-names = "iface", "bus";
power-domains = <&gcc OXILI_CX_GDSC>;
qcom,iommu-secure-id = <18>;
#address-cells = <1>;
#iommu-cells = <1>;
#size-cells = <1>;
/* gfx3d_user */
iommu-ctx@0 {
compatible = "qcom,msm-iommu-v2-ns";
reg = <0x0000 0x1000>;
interrupts = <GIC_SPI 225 IRQ_TYPE_LEVEL_HIGH>;
};
/* gfx3d_secure */
iommu-ctx@2000 {
compatible = "qcom,msm-iommu-v2-sec";
reg = <0x2000 0x1000>;
interrupts = <GIC_SPI 233 IRQ_TYPE_LEVEL_HIGH>;
};
};
apps_iommu: iommu@1e20000 {
compatible = "qcom,msm8953-iommu", "qcom,msm-iommu-v1";
ranges = <0 0x01e20000 0x20000>;
@ -1160,9 +1281,12 @@
#size-cells = <1>;
ranges;
interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>,
interrupts = <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "hs_phy_irq", "ss_phy_irq";
interrupt-names = "pwr_event",
"qusb2_phy",
"ss_phy_irq";
clocks = <&gcc GCC_USB_PHY_CFG_AHB_CLK>,
<&gcc GCC_USB30_MASTER_CLK>,
@ -2012,6 +2136,33 @@
};
};
};
gpu-thermal {
polling-delay-passive = <250>;
polling-delay = <1000>;
thermal-sensors = <&tsens0 15>;
trips {
gpu_alert: trip-point0 {
temperature = <70000>;
hysteresis = <2000>;
type = "passive";
};
gpu_crit: crit {
temperature = <90000>;
hysteresis = <2000>;
type = "critical";
};
};
cooling-maps {
map0 {
trip = <&gpu_alert>;
cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
};
};
};
};
timer {

2
arch/arm64/boot/dts/qcom/msm8994-msft-lumia-octagon.dtsi
View File

@ -377,7 +377,7 @@
&blsp2_i2c1 {
status = "okay";
sideinteraction: ad7147_captouch@2c {
sideinteraction: touch@2c {
compatible = "ad,ad7147_captouch";
reg = <0x2c>;

2
arch/arm64/boot/dts/qcom/msm8994-sony-xperia-kitakami.dtsi
View File

@ -79,7 +79,7 @@
pmsg-size = <0x80000>;
};
fb_region: fb_region@40000000 {
fb_region: fb@40000000 {
reg = <0 0x40000000 0 0x1000000>;
no-map;
};

4
arch/arm64/boot/dts/qcom/msm8994.dtsi
View File

@ -233,7 +233,7 @@
#size-cells = <2>;
ranges;
dfps_data_mem: dfps_data_mem@3400000 {
dfps_data_mem: dfps-data@3400000 {
reg = <0 0x03400000 0 0x1000>;
no-map;
};
@ -243,7 +243,7 @@
no-map;
};
smem_mem: smem_region@6a00000 {
smem_mem: smem@6a00000 {
reg = <0 0x06a00000 0 0x200000>;
no-map;
};

18
arch/arm64/boot/dts/qcom/msm8996.dtsi
View File

@ -782,12 +782,12 @@
#address-cells = <1>;
#size-cells = <1>;
qusb2p_hstx_trim: hstx_trim@24e {
qusb2p_hstx_trim: hstx-trim@24e {
reg = <0x24e 0x2>;
bits = <5 4>;
};
qusb2s_hstx_trim: hstx_trim@24f {
qusb2s_hstx_trim: hstx-trim@24f {
reg = <0x24f 0x1>;
bits = <1 4>;
};
@ -2104,7 +2104,7 @@
<0 0>,
<0 0>,
<150000000 300000000>,
<0 0>,
<75000000 150000000>,
<0 0>,
<0 0>,
<0 0>,
@ -2123,8 +2123,8 @@
compatible = "qcom,msm8996-qmp-ufs-phy";
reg = <0x00627000 0x1000>;
clocks = <&gcc GCC_UFS_CLKREF_CLK>;
clock-names = "ref";
clocks = <&rpmcc RPM_SMD_LN_BB_CLK>, <&gcc GCC_UFS_CLKREF_CLK>;
clock-names = "ref", "qref";
resets = <&ufshc 0>;
reset-names = "ufsphy";
@ -3408,8 +3408,12 @@
#size-cells = <1>;
ranges;
interrupts = <GIC_SPI 352 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "hs_phy_irq";
interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 352 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "pwr_event",
"qusb2_phy",
"hs_phy_irq";
clocks = <&gcc GCC_PERIPH_NOC_USB20_AHB_CLK>,
<&gcc GCC_USB20_MASTER_CLK>,

26
arch/arm64/boot/dts/qcom/msm8998.dtsi
View File

@ -1047,12 +1047,12 @@
compatible = "qcom,msm8998-qmp-ufs-phy";
reg = <0x01da7000 0x1000>;
clock-names =
"ref",
"ref_aux";
clocks =
<&gcc GCC_UFS_CLKREF_CLK>,
<&gcc GCC_UFS_PHY_AUX_CLK>;
clocks = <&rpmcc RPM_SMD_LN_BB_CLK1>,
<&gcc GCC_UFS_PHY_AUX_CLK>,
<&gcc GCC_UFS_CLKREF_CLK>;
clock-names = "ref",
"ref_aux",
"qref";
reset-names = "ufsphy";
resets = <&ufshc 0>;
@ -1072,6 +1072,11 @@
reg = <0x01f60000 0x20000>;
};
tcsr_regs_2: syscon@1fc0000 {
compatible = "qcom,msm8998-tcsr", "syscon";
reg = <0x01fc0000 0x26000>;
};
tlmm: pinctrl@3400000 {
compatible = "qcom,msm8998-pinctrl";
reg = <0x03400000 0xc00000>;
@ -2132,9 +2137,12 @@
<&gcc GCC_USB30_MASTER_CLK>;
assigned-clock-rates = <19200000>, <120000000>;
interrupts = <GIC_SPI 347 IRQ_TYPE_LEVEL_HIGH>,
interrupts = <GIC_SPI 180 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 347 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 243 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "hs_phy_irq", "ss_phy_irq";
interrupt-names = "pwr_event",
"qusb2_phy",
"ss_phy_irq";
power-domains = <&gcc USB_30_GDSC>;
@ -2174,6 +2182,8 @@
reset-names = "phy",
"phy_phy";
qcom,tcsr-reg = <&tcsr_regs_2 0xb244>;
status = "disabled";
};

38
arch/arm64/boot/dts/qcom/pm2250.dtsi → arch/arm64/boot/dts/qcom/pm4125.dtsi
View File

@ -19,7 +19,7 @@
compatible = "qcom,pm8916-pon";
reg = <0x800>;
pm2250_pwrkey: pwrkey {
pm4125_pwrkey: pwrkey {
compatible = "qcom,pm8941-pwrkey";
interrupts-extended = <&spmi_bus 0x0 0x8 0 IRQ_TYPE_EDGE_BOTH>;
linux,code = <KEY_POWER>;
@ -27,7 +27,7 @@
bias-pull-up;
};
pm2250_resin: resin {
pm4125_resin: resin {
compatible = "qcom,pm8941-resin";
interrupts-extended = <&spmi_bus 0x0 0x8 1 IRQ_TYPE_EDGE_BOTH>;
debounce = <15625>;
@ -36,6 +36,36 @@
};
};
pm4125_vbus: usb-vbus-regulator@1100 {
compatible = "qcom,pm4125-vbus-reg", "qcom,pm8150b-vbus-reg";
reg = <0x1100>;
status = "disabled";
};
pm4125_typec: typec@1500 {
compatible = "qcom,pm4125-typec", "qcom,pmi632-typec";
reg = <0x1500>;
interrupts = <0x0 0x15 0x00 IRQ_TYPE_EDGE_RISING>,
<0x0 0x15 0x01 IRQ_TYPE_EDGE_BOTH>,
<0x0 0x15 0x02 IRQ_TYPE_EDGE_RISING>,
<0x0 0x15 0x03 IRQ_TYPE_EDGE_BOTH>,
<0x0 0x15 0x04 IRQ_TYPE_EDGE_RISING>,
<0x0 0x15 0x05 IRQ_TYPE_EDGE_RISING>,
<0x0 0x15 0x06 IRQ_TYPE_EDGE_BOTH>,
<0x0 0x15 0x07 IRQ_TYPE_EDGE_RISING>;
interrupt-names = "or-rid-detect-change",
"vpd-detect",
"cc-state-change",
"vconn-oc",
"vbus-change",
"attach-detach",
"legacy-cable-detect",
"try-snk-src-detect";
vdd-vbus-supply = <&pm4125_vbus>;
status = "disabled";
};
rtc@6000 {
compatible = "qcom,pm8941-rtc";
reg = <0x6000>, <0x6100>;
@ -43,11 +73,11 @@
interrupts-extended = <&spmi_bus 0x0 0x61 0x1 IRQ_TYPE_EDGE_RISING>;
};
pm2250_gpios: gpio@c000 {
pm4125_gpios: gpio@c000 {
compatible = "qcom,pm2250-gpio", "qcom,spmi-gpio";
reg = <0xc000>;
gpio-controller;
gpio-ranges = <&pm2250_gpios 0 0 10>;
gpio-ranges = <&pm4125_gpios 0 0 10>;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;

39
arch/arm64/boot/dts/qcom/pmi632.dtsi
View File

@ -45,6 +45,36 @@
#address-cells = <1>;
#size-cells = <0>;
pmi632_vbus: usb-vbus-regulator@1100 {
compatible = "qcom,pmi632-vbus-reg", "qcom,pm8150b-vbus-reg";
reg = <0x1100>;
status = "disabled";
};
pmi632_typec: typec@1500 {
compatible = "qcom,pmi632-typec";
reg = <0x1500>;
interrupts = <0x2 0x15 0x00 IRQ_TYPE_EDGE_RISING>,
<0x2 0x15 0x01 IRQ_TYPE_EDGE_BOTH>,
<0x2 0x15 0x02 IRQ_TYPE_EDGE_RISING>,
<0x2 0x15 0x03 IRQ_TYPE_EDGE_BOTH>,
<0x2 0x15 0x04 IRQ_TYPE_EDGE_RISING>,
<0x2 0x15 0x05 IRQ_TYPE_EDGE_RISING>,
<0x2 0x15 0x06 IRQ_TYPE_EDGE_BOTH>,
<0x2 0x15 0x07 IRQ_TYPE_EDGE_RISING>;
interrupt-names = "or-rid-detect-change",
"vpd-detect",
"cc-state-change",
"vconn-oc",
"vbus-change",
"attach-detach",
"legacy-cable-detect",
"try-snk-src-detect";
vdd-vbus-supply = <&pmi632_vbus>;
status = "disabled";
};
pmi632_temp: temp-alarm@2400 {
compatible = "qcom,spmi-temp-alarm";
reg = <0x2400>;
@ -127,6 +157,11 @@
status = "disabled";
};
pmi632_pbs_client3: pbs@7400 {
compatible = "qcom,pmi632-pbs", "qcom,pbs";
reg = <0x7400>;
};
pmi632_sdam_7: nvram@b600 {
compatible = "qcom,spmi-sdam";
reg = <0xb600>;
@ -155,6 +190,10 @@
pmi632_lpg: pwm {
compatible = "qcom,pmi632-lpg";
nvmem = <&pmi632_sdam_7>;
nvmem-names = "lpg_chan_sdam";
qcom,pbs = <&pmi632_pbs_client3>;
#address-cells = <1>;
#size-cells = <0>;
#pwm-cells = <2>;

7
arch/arm64/boot/dts/qcom/qcm2290.dtsi
View File

@ -442,6 +442,11 @@
#hwlock-cells = <1>;
};
tcsr_regs: syscon@3c0000 {
compatible = "qcom,qcm2290-tcsr", "syscon";
reg = <0x0 0x003c0000 0x0 0x40000>;
};
tlmm: pinctrl@500000 {
compatible = "qcom,qcm2290-tlmm";
reg = <0x0 0x00500000 0x0 0x300000>;
@ -690,6 +695,8 @@
#phy-cells = <0>;
qcom,tcsr-reg = <&tcsr_regs 0xb244>;
status = "disabled";
};

56
arch/arm64/boot/dts/qcom/qcm6490-fairphone-fp5.dts
View File

@ -71,6 +71,41 @@
};
};
pmic-glink {
compatible = "qcom,qcm6490-pmic-glink", "qcom,pmic-glink";
#address-cells = <1>;
#size-cells = <0>;
connector@0 {
compatible = "usb-c-connector";
reg = <0>;
power-role = "dual";
data-role = "dual";
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
pmic_glink_hs_in: endpoint {
remote-endpoint = <&usb_1_dwc3_hs>;
};
};
port@1 {
reg = <1>;
pmic_glink_ss_in: endpoint {
remote-endpoint = <&usb_1_dwc3_ss>;
};
};
};
};
};
reserved-memory {
cont_splash_mem: cont-splash@e1000000 {
reg = <0x0 0xe1000000 0x0 0x2300000>;
@ -82,6 +117,11 @@
no-map;
};
removed_mem: removed@c0000000 {
reg = <0x0 0xc0000000 0x0 0x5100000>;
no-map;
};
rmtfs_mem: memory@f8500000 {
compatible = "qcom,rmtfs-mem";
reg = <0x0 0xf8500000 0x0 0x600000>;
@ -886,7 +926,16 @@
};
&usb_1_dwc3 {
dr_mode = "peripheral";
dr_mode = "otg";
usb-role-switch;
};
&usb_1_dwc3_hs {
remote-endpoint = <&pmic_glink_hs_in>;
};
&usb_1_dwc3_ss {
remote-endpoint = <&pmic_glink_ss_in>;
};
&usb_1_hsphy {
@ -915,6 +964,11 @@
status = "okay";
};
&venus {
firmware-name = "qcom/qcm6490/fairphone5/venus.mbn";
status = "okay";
};
&wifi {
qcom,ath11k-calibration-variant = "Fairphone_5";
status = "okay";

39
arch/arm64/boot/dts/qcom/qcm6490-idp.dts
View File

@ -5,8 +5,14 @@
/dts-v1/;
/* PM7250B is configured to use SID8/9 */
#define PM7250B_SID 8
#define PM7250B_SID1 9
#include <dt-bindings/leds/common.h>
#include <dt-bindings/regulator/qcom,rpmh-regulator.h>
#include "sc7280.dtsi"
#include "pm7250b.dtsi"
#include "pm7325.dtsi"
#include "pm8350c.dtsi"
#include "pmk8350.dtsi"
@ -109,7 +115,7 @@
no-map;
};
trusted_apps_mem: trusted_apps@c1800000 {
trusted_apps_mem: trusted-apps@c1800000 {
reg = <0x0 0xc1800000 0x0 0x1c00000>;
no-map;
};
@ -123,8 +129,8 @@
vph_pwr: vph-pwr-regulator {
compatible = "regulator-fixed";
regulator-name = "vph_pwr";
regulator-min-microvolt = <2500000>;
regulator-max-microvolt = <4350000>;
regulator-min-microvolt = <3700000>;
regulator-max-microvolt = <3700000>;
};
};
@ -415,6 +421,33 @@
};
};
&pm8350c_pwm {
status = "okay";
multi-led {
color = <LED_COLOR_ID_RGB>;
function = LED_FUNCTION_STATUS;
#address-cells = <1>;
#size-cells = <0>;
led@1 {
reg = <1>;
color = <LED_COLOR_ID_RED>;
};
led@2 {
reg = <2>;
color = <LED_COLOR_ID_GREEN>;
};
led@3 {
reg = <3>;
color = <LED_COLOR_ID_BLUE>;
};
};
};
&qupv3_id_0 {
status = "okay";
};

16
arch/arm64/boot/dts/qcom/qcs404.dtsi
View File

@ -675,6 +675,14 @@
assigned-clocks = <&gcc GCC_USB20_MOCK_UTMI_CLK>,
<&gcc GCC_USB30_MASTER_CLK>;
assigned-clock-rates = <19200000>, <200000000>;
interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "pwr_event",
"hs_phy_irq",
"qusb2_phy";
status = "disabled";
usb3_dwc3: usb@7580000 {
@ -704,6 +712,14 @@
assigned-clocks = <&gcc GCC_USB20_MOCK_UTMI_CLK>,
<&gcc GCC_USB_HS_SYSTEM_CLK>;
assigned-clock-rates = <19200000>, <133333333>;
interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "pwr_event",
"hs_phy_irq",
"qusb2_phy";
status = "disabled";
usb@78c0000 {

23
arch/arm64/boot/dts/qcom/qcs6490-rb3gen2.dts
View File

@ -110,7 +110,7 @@
no-map;
};
trusted_apps_mem: trusted_apps@c1800000 {
trusted_apps_mem: trusted-apps@c1800000 {
reg = <0x0 0xc1800000 0x0 0x1c00000>;
no-map;
};
@ -124,8 +124,8 @@
vph_pwr: vph-pwr-regulator {
compatible = "regulator-fixed";
regulator-name = "vph_pwr";
regulator-min-microvolt = <2500000>;
regulator-max-microvolt = <4350000>;
regulator-min-microvolt = <3700000>;
regulator-max-microvolt = <3700000>;
};
};
@ -413,6 +413,23 @@
};
};
&gcc {
protected-clocks = <GCC_CFG_NOC_LPASS_CLK>,
<GCC_MSS_CFG_AHB_CLK>,
<GCC_MSS_GPLL0_MAIN_DIV_CLK_SRC>,
<GCC_MSS_OFFLINE_AXI_CLK>,
<GCC_MSS_Q6SS_BOOT_CLK_SRC>,
<GCC_MSS_Q6_MEMNOC_AXI_CLK>,
<GCC_MSS_SNOC_AXI_CLK>,
<GCC_QSPI_CNOC_PERIPH_AHB_CLK>,
<GCC_QSPI_CORE_CLK>,
<GCC_QSPI_CORE_CLK_SRC>,
<GCC_SEC_CTRL_CLK_SRC>,
<GCC_WPSS_AHB_BDG_MST_CLK>,
<GCC_WPSS_AHB_CLK>,
<GCC_WPSS_RSCP_CLK>;
};
&qupv3_id_0 {
status = "okay";
};

96
arch/arm64/boot/dts/qcom/qrb2210-rb1.dts
View File

@ -7,7 +7,7 @@
#include <dt-bindings/leds/common.h>
#include "qcm2290.dtsi"
#include "pm2250.dtsi"
#include "pm4125.dtsi"
/ {
model = "Qualcomm Technologies, Inc. Robotics RB1";
@ -177,6 +177,24 @@
};
};
&CPU_PD0 {
/delete-property/ power-domains;
};
&CPU_PD1 {
/delete-property/ power-domains;
};
&CPU_PD2 {
/delete-property/ power-domains;
};
&CPU_PD3 {
/delete-property/ power-domains;
};
/delete-node/ &CLUSTER_PD;
&gpi_dma0 {
status = "okay";
};
@ -226,7 +244,7 @@
};
&mdss_dsi0 {
vdda-supply = <&pm2250_l5>;
vdda-supply = <&pm4125_l5>;
status = "okay";
};
@ -239,7 +257,7 @@
status = "okay";
};
&pm2250_resin {
&pm4125_resin {
linux,code = <KEY_VOLUMEDOWN>;
status = "okay";
};
@ -263,23 +281,23 @@
compatible = "qcom,rpm-pm2250-regulators";
vdd_s3-supply = <&vph_pwr>;
vdd_s4-supply = <&vph_pwr>;
vdd_l1_l2_l3_l5_l6_l7_l8_l9_l10_l11_l12-supply = <&pm2250_s3>;
vdd_l1_l2_l3_l5_l6_l7_l8_l9_l10_l11_l12-supply = <&pm4125_s3>;
vdd_l4_l17_l18_l19_l20_l21_l22-supply = <&vph_pwr>;
vdd_l13_l14_l15_l16-supply = <&pm2250_s4>;
vdd_l13_l14_l15_l16-supply = <&pm4125_s4>;
/*
* S1 - VDD_APC
* S2 - VDD_CX
*/
pm2250_s3: s3 {
pm4125_s3: s3 {
/* 0.4V-1.6625V -> 1.3V (Power tree requirements) */
regulator-min-microvolt = <1352000>;
regulator-max-microvolt = <1352000>;
regulator-boot-on;
};
pm2250_s4: s4 {
pm4125_s4: s4 {
/* 1.2V-2.35V -> 2.05V (Power tree requirements) */
regulator-min-microvolt = <2072000>;
regulator-max-microvolt = <2072000>;
@ -288,7 +306,7 @@
/* L1 - VDD_MX */
pm2250_l2: l2 {
pm4125_l2: l2 {
/* LPDDR4X VDD2 */
regulator-min-microvolt = <1136000>;
regulator-max-microvolt = <1136000>;
@ -296,7 +314,7 @@
regulator-boot-on;
};
pm2250_l3: l3 {
pm4125_l3: l3 {
/* LPDDR4X VDDQ */
regulator-min-microvolt = <616000>;
regulator-max-microvolt = <616000>;
@ -304,14 +322,14 @@
regulator-boot-on;
};
pm2250_l4: l4 {
pm4125_l4: l4 {
/* max = 3.05V -> max = 2.7 to disable 3V signaling (SDHCI2) */
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <2700000>;
regulator-allow-set-load;
};
pm2250_l5: l5 {
pm4125_l5: l5 {
/* CSI/DSI */
regulator-min-microvolt = <1232000>;
regulator-max-microvolt = <1232000>;
@ -319,7 +337,7 @@
regulator-boot-on;
};
pm2250_l6: l6 {
pm4125_l6: l6 {
/* DRAM PLL */
regulator-min-microvolt = <928000>;
regulator-max-microvolt = <928000>;
@ -327,7 +345,7 @@
regulator-boot-on;
};
pm2250_l7: l7 {
pm4125_l7: l7 {
/* Wi-Fi CX/MX */
regulator-min-microvolt = <664000>;
regulator-max-microvolt = <664000>;
@ -338,20 +356,20 @@
* L9 - VDD_LPI_MX
*/
pm2250_l10: l10 {
pm4125_l10: l10 {
/* Wi-Fi RFA */
regulator-min-microvolt = <1304000>;
regulator-max-microvolt = <1304000>;
};
pm2250_l11: l11 {
pm4125_l11: l11 {
/* GPS RF1 */
regulator-min-microvolt = <1000000>;
regulator-max-microvolt = <1000000>;
regulator-boot-on;
};
pm2250_l12: l12 {
pm4125_l12: l12 {
/* USB PHYs */
regulator-min-microvolt = <928000>;
regulator-max-microvolt = <928000>;
@ -359,7 +377,7 @@
regulator-boot-on;
};
pm2250_l13: l13 {
pm4125_l13: l13 {
/* USB/QFPROM/PLLs */
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
@ -367,7 +385,7 @@
regulator-boot-on;
};
pm2250_l14: l14 {
pm4125_l14: l14 {
/* SDHCI1 VQMMC */
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
@ -376,7 +394,7 @@
regulator-always-on;
};
pm2250_l15: l15 {
pm4125_l15: l15 {
/* WCD/DSI/BT VDDIO */
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
@ -385,38 +403,38 @@
regulator-boot-on;
};
pm2250_l16: l16 {
pm4125_l16: l16 {
/* GPS RF2 */
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-boot-on;
};
pm2250_l17: l17 {
pm4125_l17: l17 {
regulator-min-microvolt = <3000000>;
regulator-max-microvolt = <3000000>;
};
pm2250_l18: l18 {
pm4125_l18: l18 {
/* VDD_PXn */
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
};
pm2250_l19: l19 {
pm4125_l19: l19 {
/* VDD_PXn */
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
};
pm2250_l20: l20 {
pm4125_l20: l20 {
/* SDHCI1 VMMC */
regulator-min-microvolt = <2400000>;
regulator-max-microvolt = <3600000>;
regulator-allow-set-load;
};
pm2250_l21: l21 {
pm4125_l21: l21 {
/* SDHCI2 VMMC */
regulator-min-microvolt = <2960000>;
regulator-max-microvolt = <3300000>;
@ -424,7 +442,7 @@
regulator-boot-on;
};
pm2250_l22: l22 {
pm4125_l22: l22 {
/* Wi-Fi */
regulator-min-microvolt = <3312000>;
regulator-max-microvolt = <3312000>;
@ -433,8 +451,8 @@
};
&sdhc_1 {
vmmc-supply = <&pm2250_l20>;
vqmmc-supply = <&pm2250_l14>;
vmmc-supply = <&pm4125_l20>;
vqmmc-supply = <&pm4125_l14>;
pinctrl-0 = <&sdc1_state_on>;
pinctrl-1 = <&sdc1_state_off>;
pinctrl-names = "default", "sleep";
@ -446,8 +464,8 @@
};
&sdhc_2 {
vmmc-supply = <&pm2250_l21>;
vqmmc-supply = <&pm2250_l4>;
vmmc-supply = <&pm4125_l21>;
vqmmc-supply = <&pm4125_l4>;
cd-gpios = <&tlmm 88 GPIO_ACTIVE_LOW>;
pinctrl-0 = <&sdc2_state_on &sd_det_in_on>;
pinctrl-1 = <&sdc2_state_off &sd_det_in_off>;
@ -518,8 +536,8 @@
};
&usb_qmpphy {
vdda-phy-supply = <&pm2250_l12>;
vdda-pll-supply = <&pm2250_l13>;
vdda-phy-supply = <&pm4125_l12>;
vdda-pll-supply = <&pm4125_l13>;
status = "okay";
};
@ -528,17 +546,17 @@
};
&usb_hsphy {
vdd-supply = <&pm2250_l12>;
vdda-pll-supply = <&pm2250_l13>;
vdda-phy-dpdm-supply = <&pm2250_l21>;
vdd-supply = <&pm4125_l12>;
vdda-pll-supply = <&pm4125_l13>;
vdda-phy-dpdm-supply = <&pm4125_l21>;
status = "okay";
};
&wifi {
vdd-0.8-cx-mx-supply = <&pm2250_l7>;
vdd-1.8-xo-supply = <&pm2250_l13>;
vdd-1.3-rfa-supply = <&pm2250_l10>;
vdd-3.3-ch0-supply = <&pm2250_l22>;
vdd-0.8-cx-mx-supply = <&pm4125_l7>;
vdd-1.8-xo-supply = <&pm4125_l13>;
vdd-1.3-rfa-supply = <&pm4125_l10>;
vdd-3.3-ch0-supply = <&pm4125_l22>;
qcom,ath10k-calibration-variant = "Thundercomm_RB1";
status = "okay";
};

50
arch/arm64/boot/dts/qcom/qrb4210-rb2.dts
View File

@ -6,8 +6,10 @@
/dts-v1/;
#include <dt-bindings/leds/common.h>
#include <dt-bindings/usb/pd.h>
#include "sm4250.dtsi"
#include "pm6125.dtsi"
#include "pmi632.dtsi"
/ {
model = "Qualcomm Technologies, Inc. QRB4210 RB2";
@ -256,6 +258,46 @@
};
};
&pmi632_typec {
status = "okay";
connector {
compatible = "usb-c-connector";
power-role = "dual";
data-role = "dual";
self-powered;
typec-power-opmode = "default";
pd-disable;
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
pmi632_hs_in: endpoint {
remote-endpoint = <&usb_dwc3_hs>;
};
};
port@1 {
reg = <1>;
pmi632_ss_in: endpoint {
remote-endpoint = <&usb_qmpphy_out>;
};
};
};
};
};
&pmi632_vbus {
regulator-min-microamp = <500000>;
regulator-max-microamp = <3000000>;
status = "okay";
};
&pon_pwrkey {
status = "okay";
};
@ -607,8 +649,8 @@
status = "okay";
};
&usb_dwc3 {
maximum-speed = "super-speed";
&usb_dwc3_hs {
remote-endpoint = <&pmi632_hs_in>;
};
&usb_hsphy {
@ -626,6 +668,10 @@
status = "okay";
};
&usb_qmpphy_out {
remote-endpoint = <&pmi632_ss_in>;
};
&wifi {
vdd-0.8-cx-mx-supply = <&vreg_l8a_0p664>;
vdd-1.8-xo-supply = <&vreg_l16a_1p3>;

68
arch/arm64/boot/dts/qcom/sa8295p-adp.dts
View File

@ -108,6 +108,13 @@
};
};
};
reserved-memory {
gpu_mem: gpu-mem@8bf00000 {
reg = <0 0x8bf00000 0 0x2000>;
no-map;
};
};
};
&apps_rsc {
@ -266,6 +273,48 @@
status = "okay";
};
&i2c12 {
pinctrl-0 = <&qup1_i2c4_state>;
pinctrl-names = "default";
status = "okay";
vdd_gfx: regulator@39 {
compatible = "maxim,max20411";
reg = <0x39>;
regulator-min-microvolt = <800000>;
regulator-max-microvolt = <800000>;
enable-gpios = <&pmm8540a_gpios 2 GPIO_ACTIVE_HIGH>;
pinctrl-0 = <&max20411_en>;
pinctrl-names = "default";
};
};
&gpucc {
vdd-gfx-supply = <&vdd_gfx>;
status = "okay";
};
&gmu {
status = "okay";
};
&gpu {
status = "okay";
zap-shader {
memory-region = <&gpu_mem>;
firmware-name = "qcom/sa8295p/a690_zap.mbn";
};
};
&gpu_smmu {
status = "okay";
};
&mdss0 {
status = "okay";
};
@ -476,6 +525,10 @@
status = "okay";
};
&qup1 {
status = "okay";
};
&qup2 {
status = "okay";
};
@ -636,6 +689,14 @@
/* PINCTRL */
&pmm8540a_gpios {
max20411_en: max20411-en-state {
pins = "gpio2";
function = "normal";
output-enable;
};
};
&tlmm {
pcie2a_default: pcie2a-default-state {
clkreq-n-pins {
@ -728,4 +789,11 @@
bias-pull-up;
};
};
qup1_i2c4_state: qup1-i2c4-state {
pins = "gpio0", "gpio1";
function = "qup12";
drive-strength = <2>;
bias-pull-up;
};
};

4
arch/arm64/boot/dts/qcom/sa8540p-ride.dts
View File

@ -376,14 +376,14 @@
pinctrl-names = "default";
pinctrl-0 = <&pcie2a_default>;
status = "okay";
status = "disabled";
};
&pcie2a_phy {
vdda-phy-supply = <&vreg_l11a>;
vdda-pll-supply = <&vreg_l3a>;
status = "okay";
status = "disabled";
};
&pcie3a {

3
arch/arm64/boot/dts/qcom/sa8540p.dtsi
View File

@ -168,6 +168,9 @@
};
&gpucc {
/* SA8295P and SA8540P doesn't provide gfx.lvl */
/delete-property/ power-domains;
status = "disabled";
};

121
arch/arm64/boot/dts/qcom/sa8775p.dtsi
View File

@ -356,13 +356,18 @@
no-map;
};
reserved_mem: reserved@908f0000 {
reg = <0x0 0x908f0000 0x0 0xf000>;
ddr_training_checksum: ddr-training-checksum@908c0000 {
reg = <0x0 0x908c0000 0x0 0x1000>;
no-map;
};
secdata_apss_mem: secdata-apss@908ff000 {
reg = <0x0 0x908ff000 0x0 0x1000>;
reserved_mem: reserved@908f0000 {
reg = <0x0 0x908f0000 0x0 0xe000>;
no-map;
};
secdata_apss_mem: secdata-apss@908fe000 {
reg = <0x0 0x908fe000 0x0 0x2000>;
no-map;
};
@ -373,8 +378,43 @@
hwlocks = <&tcsr_mutex 3>;
};
cpucp_fw_mem: cpucp-fw@90b00000 {
reg = <0x0 0x90b00000 0x0 0x100000>;
tz_sail_mailbox_mem: tz-sail-mailbox@90c00000 {
reg = <0x0 0x90c00000 0x0 0x100000>;
no-map;
};
sail_mailbox_mem: sail-ss@90d00000 {
reg = <0x0 0x90d00000 0x0 0x100000>;
no-map;
};
sail_ota_mem: sail-ss@90e00000 {
reg = <0x0 0x90e00000 0x0 0x300000>;
no-map;
};
aoss_backup_mem: aoss-backup@91b00000 {
reg = <0x0 0x91b00000 0x0 0x40000>;
no-map;
};
cpucp_backup_mem: cpucp-backup@91b40000 {
reg = <0x0 0x91b40000 0x0 0x40000>;
no-map;
};
tz_config_backup_mem: tz-config-backup@91b80000 {
reg = <0x0 0x91b80000 0x0 0x10000>;
no-map;
};
ddr_training_data_mem: ddr-training-data@91b90000 {
reg = <0x0 0x91b90000 0x0 0x10000>;
no-map;
};
cdt_data_backup_mem: cdt-data-backup@91ba0000 {
reg = <0x0 0x91ba0000 0x0 0x1000>;
no-map;
};
@ -433,13 +473,43 @@
no-map;
};
audio_mdf_mem: audio-mdf-region@ae000000 {
reg = <0x0 0xae000000 0x0 0x1000000>;
no-map;
};
firmware_mem: firmware-region@b0000000 {
reg = <0x0 0xb0000000 0x0 0x800000>;
no-map;
};
hyptz_reserved_mem: hyptz-reserved@beb00000 {
reg = <0x0 0xbeb00000 0x0 0x11500000>;
no-map;
};
tz_stat_mem: tz-stat@d0000000 {
reg = <0x0 0xd0000000 0x0 0x100000>;
scmi_mem: scmi-region@d0000000 {
reg = <0x0 0xd0000000 0x0 0x40000>;
no-map;
};
firmware_logs_mem: firmware-logs@d0040000 {
reg = <0x0 0xd0040000 0x0 0x10000>;
no-map;
};
firmware_audio_mem: firmware-audio@d0050000 {
reg = <0x0 0xd0050000 0x0 0x4000>;
no-map;
};
firmware_reserved_mem: firmware-reserved@d0054000 {
reg = <0x0 0xd0054000 0x0 0x9c000>;
no-map;
};
firmware_quantum_test_mem: firmware-quantum-test@d00f0000 {
reg = <0x0 0xd00f0000 0x0 0x10000>;
no-map;
};
@ -453,8 +523,23 @@
no-map;
};
trusted_apps_mem: trusted-apps@d1800000 {
reg = <0x0 0xd1800000 0x0 0x3900000>;
deepsleep_backup_mem: deepsleep-backup@d1800000 {
reg = <0x0 0xd1800000 0x0 0x100000>;
no-map;
};
trusted_apps_mem: trusted-apps@d1900000 {
reg = <0x0 0xd1900000 0x0 0x3800000>;
no-map;
};
tz_stat_mem: tz-stat@db100000 {
reg = <0x0 0xdb100000 0x0 0x100000>;
no-map;
};
cpucp_fw_mem: cpucp-fw@db200000 {
reg = <0x0 0xdb200000 0x0 0x100000>;
no-map;
};
};
@ -1615,10 +1700,12 @@
assigned-clock-rates = <19200000>, <200000000>;
interrupts-extended = <&intc GIC_SPI 287 IRQ_TYPE_LEVEL_HIGH>,
<&intc GIC_SPI 261 IRQ_TYPE_LEVEL_HIGH>,
<&pdc 14 IRQ_TYPE_EDGE_BOTH>,
<&pdc 15 IRQ_TYPE_EDGE_BOTH>,
<&pdc 12 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "pwr_event",
"hs_phy_irq",
"dp_hs_phy_irq",
"dm_hs_phy_irq",
"ss_phy_irq";
@ -1702,10 +1789,12 @@
assigned-clock-rates = <19200000>, <200000000>;
interrupts-extended = <&intc GIC_SPI 352 IRQ_TYPE_LEVEL_HIGH>,
<&intc GIC_SPI 351 IRQ_TYPE_LEVEL_HIGH>,
<&pdc 8 IRQ_TYPE_EDGE_BOTH>,
<&pdc 7 IRQ_TYPE_EDGE_BOTH>,
<&pdc 13 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "pwr_event",
"hs_phy_irq",
"dp_hs_phy_irq",
"dm_hs_phy_irq",
"ss_phy_irq";
@ -1765,9 +1854,11 @@
assigned-clock-rates = <19200000>, <200000000>;
interrupts-extended = <&intc GIC_SPI 444 IRQ_TYPE_LEVEL_HIGH>,
<&intc GIC_SPI 443 IRQ_TYPE_LEVEL_HIGH>,
<&pdc 10 IRQ_TYPE_EDGE_BOTH>,
<&pdc 9 IRQ_TYPE_EDGE_BOTH>;
interrupt-names = "pwr_event",
"hs_phy_irq",
"dp_hs_phy_irq",
"dm_hs_phy_irq";
@ -2394,8 +2485,9 @@
<0x0 0x23016000 0x0 0x100>;
reg-names = "stmmaceth", "rgmii";
interrupts = <GIC_SPI 929 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "macirq";
interrupts = <GIC_SPI 929 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 781 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "macirq", "sfty";
clocks = <&gcc GCC_EMAC1_AXI_CLK>,
<&gcc GCC_EMAC1_SLV_AHB_CLK>,
@ -2427,8 +2519,9 @@
<0x0 0x23056000 0x0 0x100>;
reg-names = "stmmaceth", "rgmii";
interrupts = <GIC_SPI 946 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "macirq";
interrupts = <GIC_SPI 946 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 782 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "macirq", "sfty";
clocks = <&gcc GCC_EMAC0_AXI_CLK>,
<&gcc GCC_EMAC0_SLV_AHB_CLK>,

1
arch/arm64/boot/dts/qcom/sc7180-trogdor.dtsi
View File

@ -649,6 +649,7 @@ ap_ec_spi: &spi6 {
pinctrl-names = "default";
pinctrl-0 = <&ap_ec_int_l>;
spi-max-frequency = <3000000>;
wakeup-source;
cros_ec_pwm: pwm {
compatible = "google,cros-ec-pwm";

86
arch/arm64/boot/dts/qcom/sc7180.dtsi
View File

@ -817,7 +817,7 @@
bits = <1 3>;
};
gpu_speed_bin: gpu_speed_bin@1d2 {
gpu_speed_bin: gpu-speed-bin@1d2 {
reg = <0x1d2 0x2>;
bits = <5 8>;
};
@ -1532,6 +1532,76 @@
qcom,bcm-voters = <&apps_bcm_voter>;
};
ufs_mem_hc: ufshc@1d84000 {
compatible = "qcom,sc7180-ufshc", "qcom,ufshc",
"jedec,ufs-2.0";
reg = <0 0x01d84000 0 0x3000>;
interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>;
phys = <&ufs_mem_phy>;
phy-names = "ufsphy";
lanes-per-direction = <1>;
#reset-cells = <1>;
resets = <&gcc GCC_UFS_PHY_BCR>;
reset-names = "rst";
power-domains = <&gcc UFS_PHY_GDSC>;
iommus = <&apps_smmu 0xa0 0x0>;
clock-names = "core_clk",
"bus_aggr_clk",
"iface_clk",
"core_clk_unipro",
"ref_clk",
"tx_lane0_sync_clk",
"rx_lane0_sync_clk";
clocks = <&gcc GCC_UFS_PHY_AXI_CLK>,
<&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>,
<&gcc GCC_UFS_PHY_AHB_CLK>,
<&gcc GCC_UFS_PHY_UNIPRO_CORE_CLK>,
<&rpmhcc RPMH_CXO_CLK>,
<&gcc GCC_UFS_PHY_TX_SYMBOL_0_CLK>,
<&gcc GCC_UFS_PHY_RX_SYMBOL_0_CLK>;
freq-table-hz = <50000000 200000000>,
<0 0>,
<0 0>,
<37500000 150000000>,
<0 0>,
<0 0>,
<0 0>;
interconnects = <&aggre1_noc MASTER_UFS_MEM QCOM_ICC_TAG_ALWAYS
&mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>,
<&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
&config_noc SLAVE_UFS_MEM_CFG QCOM_ICC_TAG_ALWAYS>;
interconnect-names = "ufs-ddr", "cpu-ufs";
qcom,ice = <&ice>;
status = "disabled";
};
ufs_mem_phy: phy@1d87000 {
compatible = "qcom,sc7180-qmp-ufs-phy",
"qcom,sm7150-qmp-ufs-phy";
reg = <0 0x01d87000 0 0x1000>;
clocks = <&gcc GCC_UFS_MEM_CLKREF_CLK>,
<&gcc GCC_UFS_PHY_PHY_AUX_CLK>;
clock-names = "ref", "ref_aux";
power-domains = <&gcc UFS_PHY_GDSC>;
resets = <&ufs_mem_hc 0>;
reset-names = "ufsphy";
#phy-cells = <0>;
status = "disabled";
};
ice: crypto@1d90000 {
compatible = "qcom,sc7180-inline-crypto-engine",
"qcom,inline-crypto-engine";
reg = <0 0x01d90000 0 0x8000>;
clocks = <&gcc GCC_UFS_PHY_ICE_CORE_CLK>;
};
ipa: ipa@1e40000 {
compatible = "qcom,sc7180-ipa";
@ -2964,12 +3034,16 @@
<&gcc GCC_USB30_PRIM_MASTER_CLK>;
assigned-clock-rates = <19200000>, <150000000>;
interrupts-extended = <&intc GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>,
<&pdc 6 IRQ_TYPE_LEVEL_HIGH>,
interrupts-extended = <&intc GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>,
<&intc GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>,
<&pdc 9 IRQ_TYPE_EDGE_BOTH>,
<&pdc 8 IRQ_TYPE_EDGE_BOTH>,
<&pdc 9 IRQ_TYPE_EDGE_BOTH>;
interrupt-names = "hs_phy_irq", "ss_phy_irq",
"dm_hs_phy_irq", "dp_hs_phy_irq";
<&pdc 6 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "pwr_event",
"hs_phy_irq",
"dp_hs_phy_irq",
"dm_hs_phy_irq",
"ss_phy_irq";
power-domains = <&gcc USB30_PRIM_GDSC>;
required-opps = <&rpmhpd_opp_nom>;

28
arch/arm64/boot/dts/qcom/sc7280-chrome-common.dtsi
View File

@ -18,6 +18,7 @@
*/
/delete-node/ &cdsp_mem;
/delete-node/ &domain_idle_states;
/delete-node/ &gpu_zap_mem;
/delete-node/ &gpu_zap_shader;
/delete-node/ &hyp_mem;
@ -26,6 +27,18 @@
/delete-node/ &sec_apps_mem;
/ {
cpus {
domain_idle_states: domain-idle-states {
CLUSTER_SLEEP_0: cluster-sleep-0 {
compatible = "domain-idle-state";
arm,psci-suspend-param = <0x40003444>;
entry-latency-us = <2752>;
exit-latency-us = <6562>;
min-residency-us = <9926>;
};
};
};
reserved-memory {
camera_mem: memory@8ad00000 {
reg = <0x0 0x8ad00000 0x0 0x500000>;
@ -39,6 +52,10 @@
};
};
&CLUSTER_PD {
domain-idle-states = <&CLUSTER_SLEEP_0>;
};
&lpass_aon {
status = "okay";
};
@ -119,6 +136,17 @@
dma-coherent;
};
&venus {
iommus = <&apps_smmu 0x2180 0x20>,
<&apps_smmu 0x2184 0x20>;
status = "okay";
video-firmware {
iommus = <&apps_smmu 0x21a2 0x0>;
};
};
&watchdog {
status = "okay";
};

1
arch/arm64/boot/dts/qcom/sc7280-herobrine.dtsi
View File

@ -548,6 +548,7 @@ ap_ec_spi: &spi10 {
pinctrl-names = "default";
pinctrl-0 = <&ap_ec_int_l>;
spi-max-frequency = <3000000>;
wakeup-source;
cros_ec_pwm: pwm {
compatible = "google,cros-ec-pwm";

1
arch/arm64/boot/dts/qcom/sc7280-idp-ec-h1.dtsi
View File

@ -19,6 +19,7 @@ ap_ec_spi: &spi10 {
pinctrl-names = "default";
pinctrl-0 = <&ap_ec_int_l>;
spi-max-frequency = <3000000>;
wakeup-source;
cros_ec_pwm: pwm {
compatible = "google,cros-ec-pwm";

125
arch/arm64/boot/dts/qcom/sc7280.dtsi
View File

@ -202,6 +202,8 @@
power-domain-names = "psci";
next-level-cache = <&L2_0>;
operating-points-v2 = <&cpu0_opp_table>;
capacity-dmips-mhz = <1024>;
dynamic-power-coefficient = <100>;
interconnects = <&gem_noc MASTER_APPSS_PROC 3 &mc_virt SLAVE_EBI1 3>,
<&epss_l3 MASTER_EPSS_L3_APPS &epss_l3 SLAVE_EPSS_L3_SHARED>;
qcom,freq-domain = <&cpufreq_hw 0>;
@ -229,6 +231,8 @@
power-domain-names = "psci";
next-level-cache = <&L2_100>;
operating-points-v2 = <&cpu0_opp_table>;
capacity-dmips-mhz = <1024>;
dynamic-power-coefficient = <100>;
interconnects = <&gem_noc MASTER_APPSS_PROC 3 &mc_virt SLAVE_EBI1 3>,
<&epss_l3 MASTER_EPSS_L3_APPS &epss_l3 SLAVE_EPSS_L3_SHARED>;
qcom,freq-domain = <&cpufreq_hw 0>;
@ -251,6 +255,8 @@
power-domain-names = "psci";
next-level-cache = <&L2_200>;
operating-points-v2 = <&cpu0_opp_table>;
capacity-dmips-mhz = <1024>;
dynamic-power-coefficient = <100>;
interconnects = <&gem_noc MASTER_APPSS_PROC 3 &mc_virt SLAVE_EBI1 3>,
<&epss_l3 MASTER_EPSS_L3_APPS &epss_l3 SLAVE_EPSS_L3_SHARED>;
qcom,freq-domain = <&cpufreq_hw 0>;
@ -273,6 +279,8 @@
power-domain-names = "psci";
next-level-cache = <&L2_300>;
operating-points-v2 = <&cpu0_opp_table>;
capacity-dmips-mhz = <1024>;
dynamic-power-coefficient = <100>;
interconnects = <&gem_noc MASTER_APPSS_PROC 3 &mc_virt SLAVE_EBI1 3>,
<&epss_l3 MASTER_EPSS_L3_APPS &epss_l3 SLAVE_EPSS_L3_SHARED>;
qcom,freq-domain = <&cpufreq_hw 0>;
@ -295,6 +303,8 @@
power-domain-names = "psci";
next-level-cache = <&L2_400>;
operating-points-v2 = <&cpu4_opp_table>;
capacity-dmips-mhz = <1946>;
dynamic-power-coefficient = <520>;
interconnects = <&gem_noc MASTER_APPSS_PROC 3 &mc_virt SLAVE_EBI1 3>,
<&epss_l3 MASTER_EPSS_L3_APPS &epss_l3 SLAVE_EPSS_L3_SHARED>;
qcom,freq-domain = <&cpufreq_hw 1>;
@ -317,6 +327,8 @@
power-domain-names = "psci";
next-level-cache = <&L2_500>;
operating-points-v2 = <&cpu4_opp_table>;
capacity-dmips-mhz = <1946>;
dynamic-power-coefficient = <520>;
interconnects = <&gem_noc MASTER_APPSS_PROC 3 &mc_virt SLAVE_EBI1 3>,
<&epss_l3 MASTER_EPSS_L3_APPS &epss_l3 SLAVE_EPSS_L3_SHARED>;
qcom,freq-domain = <&cpufreq_hw 1>;
@ -339,6 +351,8 @@
power-domain-names = "psci";
next-level-cache = <&L2_600>;
operating-points-v2 = <&cpu4_opp_table>;
capacity-dmips-mhz = <1946>;
dynamic-power-coefficient = <520>;
interconnects = <&gem_noc MASTER_APPSS_PROC 3 &mc_virt SLAVE_EBI1 3>,
<&epss_l3 MASTER_EPSS_L3_APPS &epss_l3 SLAVE_EPSS_L3_SHARED>;
qcom,freq-domain = <&cpufreq_hw 1>;
@ -361,6 +375,8 @@
power-domain-names = "psci";
next-level-cache = <&L2_700>;
operating-points-v2 = <&cpu7_opp_table>;
capacity-dmips-mhz = <1985>;
dynamic-power-coefficient = <552>;
interconnects = <&gem_noc MASTER_APPSS_PROC 3 &mc_virt SLAVE_EBI1 3>,
<&epss_l3 MASTER_EPSS_L3_APPS &epss_l3 SLAVE_EPSS_L3_SHARED>;
qcom,freq-domain = <&cpufreq_hw 2>;
@ -453,15 +469,29 @@
};
};
domain-idle-states {
CLUSTER_SLEEP_0: cluster-sleep-0 {
domain_idle_states: domain-idle-states {
CLUSTER_SLEEP_APSS_OFF: cluster-sleep-0 {
compatible = "domain-idle-state";
idle-state-name = "cluster-power-down";
arm,psci-suspend-param = <0x40003444>;
arm,psci-suspend-param = <0x41000044>;
entry-latency-us = <2752>;
exit-latency-us = <3048>;
min-residency-us = <6118>;
};
CLUSTER_SLEEP_CX_RET: cluster-sleep-1 {
compatible = "domain-idle-state";
arm,psci-suspend-param = <0x41001344>;
entry-latency-us = <3263>;
exit-latency-us = <4562>;
min-residency-us = <8467>;
};
CLUSTER_SLEEP_LLCC_OFF: cluster-sleep-2 {
compatible = "domain-idle-state";
arm,psci-suspend-param = <0x4100b344>;
entry-latency-us = <3638>;
exit-latency-us = <6562>;
min-residency-us = <9926>;
local-timer-stop;
min-residency-us = <9826>;
};
};
};
@ -872,7 +902,7 @@
CLUSTER_PD: power-domain-cluster {
#power-domain-cells = <0>;
domain-idle-states = <&CLUSTER_SLEEP_0>;
domain-idle-states = <&CLUSTER_SLEEP_APSS_OFF &CLUSTER_SLEEP_CX_RET &CLUSTER_SLEEP_LLCC_OFF>;
};
};
@ -966,7 +996,7 @@
#address-cells = <1>;
#size-cells = <1>;
gpu_speed_bin: gpu_speed_bin@1e9 {
gpu_speed_bin: gpu-speed-bin@1e9 {
reg = <0x1e9 0x2>;
bits = <5 8>;
};
@ -2178,8 +2208,16 @@
ranges = <0x01000000 0x0 0x00000000 0x0 0x40200000 0x0 0x100000>,
<0x02000000 0x0 0x40300000 0x0 0x40300000 0x0 0x1fd00000>;
interrupts = <GIC_SPI 307 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "msi";
interrupts = <GIC_SPI 307 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 313 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 314 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 374 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 375 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "msi0", "msi1", "msi2", "msi3",
"msi4", "msi5", "msi6", "msi7";
#interrupt-cells = <1>;
interrupt-map-mask = <0 0 0 0x7>;
interrupt-map = <0 0 0 1 &intc 0 0 0 434 IRQ_TYPE_LEVEL_HIGH>,
@ -2345,6 +2383,8 @@
<&apps_smmu 0x4e6 0x0011>;
qcom,ee = <0>;
qcom,controlled-remotely;
num-channels = <16>;
qcom,num-ees = <4>;
};
crypto: crypto@1dfa000 {
@ -2648,6 +2688,31 @@
status = "disabled";
};
slimbam: dma-controller@3a84000 {
compatible = "qcom,bam-v1.7.0";
reg = <0 0x03a84000 0 0x20000>;
interrupts = <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>;
#dma-cells = <1>;
qcom,controlled-remotely;
num-channels = <31>;
qcom,ee = <1>;
qcom,num-ees = <2>;
iommus = <&apps_smmu 0x1826 0x0>;
status = "disabled";
};
slim: slim-ngd@3ac0000 {
compatible = "qcom,slim-ngd-v1.5.0";
reg = <0 0x03ac0000 0 0x2c000>;
interrupts = <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>;
dmas = <&slimbam 3>, <&slimbam 4>;
dma-names = "rx", "tx";
iommus = <&apps_smmu 0x1826 0x0>;
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
lpass_hm: clock-controller@3c00000 {
compatible = "qcom,sc7280-lpasshm";
reg = <0 0x03c00000 0 0x28>;
@ -3582,10 +3647,12 @@
<&gcc GCC_USB30_SEC_MASTER_CLK>;
assigned-clock-rates = <19200000>, <200000000>;
interrupts-extended = <&intc GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
interrupts-extended = <&intc GIC_SPI 241 IRQ_TYPE_LEVEL_HIGH>,
<&intc GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
<&pdc 12 IRQ_TYPE_EDGE_BOTH>,
<&pdc 13 IRQ_TYPE_EDGE_BOTH>;
interrupt-names = "hs_phy_irq",
interrupt-names = "pwr_event",
"hs_phy_irq",
"dp_hs_phy_irq",
"dm_hs_phy_irq";
@ -4035,11 +4102,13 @@
<&gcc GCC_USB30_PRIM_MASTER_CLK>;
assigned-clock-rates = <19200000>, <200000000>;
interrupts-extended = <&intc GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>,
interrupts-extended = <&intc GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>,
<&intc GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>,
<&pdc 14 IRQ_TYPE_EDGE_BOTH>,
<&pdc 15 IRQ_TYPE_EDGE_BOTH>,
<&pdc 17 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "hs_phy_irq",
interrupt-names = "pwr_event",
"hs_phy_irq",
"dp_hs_phy_irq",
"dm_hs_phy_irq",
"ss_phy_irq";
@ -4065,6 +4134,25 @@
phys = <&usb_1_hsphy>, <&usb_1_qmpphy QMP_USB43DP_USB3_PHY>;
phy-names = "usb2-phy", "usb3-phy";
maximum-speed = "super-speed";
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
usb_1_dwc3_hs: endpoint {
};
};
port@1 {
reg = <1>;
usb_1_dwc3_ss: endpoint {
};
};
};
};
};
@ -4091,10 +4179,11 @@
<&mmss_noc MASTER_VIDEO_P0 0 &mc_virt SLAVE_EBI1 0>;
interconnect-names = "cpu-cfg", "video-mem";
iommus = <&apps_smmu 0x2180 0x20>,
<&apps_smmu 0x2184 0x20>;
iommus = <&apps_smmu 0x2180 0x20>;
memory-region = <&video_mem>;
status = "disabled";
video-decoder {
compatible = "venus-decoder";
};
@ -4103,10 +4192,6 @@
compatible = "venus-encoder";
};
video-firmware {
iommus = <&apps_smmu 0x21a2 0x0>;
};
venus_opp_table: opp-table {
compatible = "operating-points-v2";

141
arch/arm64/boot/dts/qcom/sc8180x.dtsi
View File

@ -290,7 +290,7 @@
BIG_CPU_SLEEP_0: cpu-sleep-1-0 {
compatible = "arm,idle-state";
arm,psci-suspend-param = <0x40000004>;
entry-latency-us = <241>;
entry-latency-us = <2411>;
exit-latency-us = <1461>;
min-residency-us = <4488>;
local-timer-stop;
@ -298,7 +298,15 @@
};
domain-idle-states {
CLUSTER_SLEEP_0: cluster-sleep-0 {
CLUSTER_SLEEP_APSS_OFF: cluster-sleep-0 {
compatible = "domain-idle-state";
arm,psci-suspend-param = <0x41000044>;
entry-latency-us = <3300>;
exit-latency-us = <3300>;
min-residency-us = <6000>;
};
CLUSTER_SLEEP_AOSS_SLEEP: cluster-sleep-1 {
compatible = "domain-idle-state";
arm,psci-suspend-param = <0x4100a344>;
entry-latency-us = <3263>;
@ -582,7 +590,7 @@
CLUSTER_PD: power-domain-cpu-cluster0 {
#power-domain-cells = <0>;
domain-idle-states = <&CLUSTER_SLEEP_0>;
domain-idle-states = <&CLUSTER_SLEEP_APSS_OFF &CLUSTER_SLEEP_AOSS_SLEEP>;
};
};
@ -782,6 +790,7 @@
clock-names = "bi_tcxo",
"bi_tcxo_ao",
"sleep_clk";
power-domains = <&rpmhpd SC8180X_CX>;
};
qupv3_id_0: geniqup@8c0000 {
@ -1708,8 +1717,22 @@
ranges = <0x01000000 0x0 0x60200000 0x0 0x60200000 0x0 0x100000>,
<0x02000000 0x0 0x60300000 0x0 0x60300000 0x0 0x3d00000>;
interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "msi";
interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "msi0",
"msi1",
"msi2",
"msi3",
"msi4",
"msi5",
"msi6",
"msi7";
#interrupt-cells = <1>;
interrupt-map-mask = <0 0 0 0x7>;
interrupt-map = <0 0 0 1 &intc 0 149 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
@ -1805,8 +1828,22 @@
ranges = <0x01000000 0x0 0x40200000 0x0 0x40200000 0x0 0x100000>,
<0x02000000 0x0 0x40300000 0x0 0x40300000 0x0 0x1fd00000>;
interrupts = <GIC_SPI 307 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "msi";
interrupts = <GIC_SPI 307 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 313 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 314 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 374 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 375 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "msi0",
"msi1",
"msi2",
"msi3",
"msi4",
"msi5",
"msi6",
"msi7";
#interrupt-cells = <1>;
interrupt-map-mask = <0 0 0 0x7>;
interrupt-map = <0 0 0 1 &intc 0 434 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
@ -1903,8 +1940,22 @@
ranges = <0x01000000 0x0 0x68200000 0x0 0x68200000 0x0 0x100000>,
<0x02000000 0x0 0x68300000 0x0 0x68300000 0x0 0x3d00000>;
interrupts = <GIC_SPI 755 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "msi";
interrupts = <GIC_SPI 756 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 755 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 754 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 753 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 752 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 751 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 750 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 749 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "msi0",
"msi1",
"msi2",
"msi3",
"msi4",
"msi5",
"msi6",
"msi7";
#interrupt-cells = <1>;
interrupt-map-mask = <0 0 0 0x7>;
interrupt-map = <0 0 0 1 &intc 0 747 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
@ -2001,8 +2052,22 @@
ranges = <0x01000000 0x0 0x70200000 0x0 0x70200000 0x0 0x100000>,
<0x02000000 0x0 0x70300000 0x0 0x70300000 0x0 0x3d00000>;
interrupts = <GIC_SPI 671 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "msi";
interrupts = <GIC_SPI 672 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 671 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 670 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 669 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 668 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 667 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 666 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 665 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "msi0",
"msi1",
"msi2",
"msi3",
"msi4",
"msi5",
"msi6",
"msi7";
#interrupt-cells = <1>;
interrupt-map-mask = <0 0 0 0x7>;
interrupt-map = <0 0 0 1 &intc 0 663 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
@ -2131,9 +2196,11 @@
reg = <0 0x01d87000 0 0x1000>;
clocks = <&rpmhcc RPMH_CXO_CLK>,
<&gcc GCC_UFS_PHY_PHY_AUX_CLK>;
<&gcc GCC_UFS_PHY_PHY_AUX_CLK>,
<&gcc GCC_UFS_MEM_CLKREF_EN>;
clock-names = "ref",
"ref_aux";
"ref_aux",
"qref";
resets = <&ufs_mem_hc 0>;
reset-names = "ufsphy";
@ -2173,6 +2240,8 @@
interconnect-names = "gfx-mem";
qcom,gmu = <&gmu>;
#cooling-cells = <2>;
status = "disabled";
gpu_opp_table: opp-table {
@ -2692,9 +2761,15 @@
interrupt-controller;
#interrupt-cells = <1>;
interconnects = <&mmss_noc MASTER_MDP_PORT0 0 &mc_virt SLAVE_EBI_CH0 0>,
<&mmss_noc MASTER_MDP_PORT1 0 &mc_virt SLAVE_EBI_CH0 0>;
interconnect-names = "mdp0-mem", "mdp1-mem";
interconnects = <&mmss_noc MASTER_MDP_PORT0 QCOM_ICC_TAG_ALWAYS
&mc_virt SLAVE_EBI_CH0 QCOM_ICC_TAG_ALWAYS>,
<&mmss_noc MASTER_MDP_PORT1 QCOM_ICC_TAG_ALWAYS
&mc_virt SLAVE_EBI_CH0 QCOM_ICC_TAG_ALWAYS>,
<&gem_noc MASTER_AMPSS_M0 QCOM_ICC_TAG_ALWAYS
&config_noc SLAVE_DISPLAY_CFG QCOM_ICC_TAG_ALWAYS>;
interconnect-names = "mdp0-mem",
"mdp1-mem",
"cpu-cfg";
iommus = <&apps_smmu 0x800 0x420>;
@ -2723,10 +2798,8 @@
"rot",
"lut";
assigned-clocks = <&dispcc DISP_CC_MDSS_MDP_CLK>,
<&dispcc DISP_CC_MDSS_VSYNC_CLK>;
assigned-clock-rates = <460000000>,
<19200000>;
assigned-clocks = <&dispcc DISP_CC_MDSS_VSYNC_CLK>;
assigned-clock-rates = <19200000>;
operating-points-v2 = <&mdp_opp_table>;
power-domains = <&rpmhpd SC8180X_MMCX>;
@ -3184,7 +3257,7 @@
<&dispcc DISP_CC_MDSS_AHB_CLK>;
clock-names = "aux", "cfg_ahb";
power-domains = <&dispcc MDSS_GDSC>;
power-domains = <&rpmhpd SC8180X_MX>;
#clock-cells = <1>;
#phy-cells = <0>;
@ -3210,6 +3283,7 @@
"edp_phy_pll_link_clk",
"edp_phy_pll_vco_div_clk";
power-domains = <&rpmhpd SC8180X_MMCX>;
required-opps = <&rpmhpd_opp_low_svs>;
#clock-cells = <1>;
#reset-cells = <1>;
#power-domain-cells = <1>;
@ -3248,7 +3322,7 @@
aoss_qmp: power-controller@c300000 {
compatible = "qcom,sc8180x-aoss-qmp", "qcom,aoss-qmp";
reg = <0x0 0x0c300000 0x0 0x100000>;
reg = <0x0 0x0c300000 0x0 0x400>;
interrupts = <GIC_SPI 389 IRQ_TYPE_EDGE_RISING>;
mboxes = <&apss_shared 0>;
@ -3256,6 +3330,11 @@
#power-domain-cells = <1>;
};
sram@c3f0000 {
compatible = "qcom,rpmh-stats";
reg = <0x0 0x0c3f0000 0x0 0x400>;
};
spmi_bus: spmi@c440000 {
compatible = "qcom,spmi-pmic-arb";
reg = <0x0 0x0c440000 0x0 0x0001100>,
@ -3880,8 +3959,15 @@
thermal-sensors = <&tsens0 15>;
cooling-maps {
map0 {
trip = <&gpu_top_alert0>;
cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
};
};
trips {
trip-point0 {
gpu_top_alert0: trip-point0 {
temperature = <90000>;
hysteresis = <2000>;
type = "hot";
@ -4030,8 +4116,15 @@
thermal-sensors = <&tsens1 11>;
cooling-maps {
map0 {
trip = <&gpu_bottom_alert0>;
cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
};
};
trips {
trip-point0 {
gpu_bottom_alert0: trip-point0 {
temperature = <90000>;
hysteresis = <2000>;
type = "hot";

39
arch/arm64/boot/dts/qcom/sc8280xp-lenovo-thinkpad-x13s.dts
View File

@ -6,10 +6,8 @@
/dts-v1/;
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/iio/qcom,spmi-adc7-pm8350.h>
#include <dt-bindings/iio/qcom,spmi-adc7-pmk8350.h>
#include <dt-bindings/iio/qcom,spmi-adc7-pmr735a.h>
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/input/gpio-keys.h>
#include <dt-bindings/input/input.h>
#include <dt-bindings/leds/common.h>
@ -853,27 +851,6 @@
};
&pmk8280_vadc {
status = "okay";
channel@3 {
reg = <PMK8350_ADC7_DIE_TEMP>;
qcom,pre-scaling = <1 1>;
label = "pmk8350_die_temp";
};
channel@44 {
reg = <PMK8350_ADC7_AMUX_THM1_100K_PU>;
qcom,hw-settle-time = <200>;
qcom,ratiometric;
label = "pmk8350_xo_therm";
};
channel@103 {
reg = <PM8350_ADC7_DIE_TEMP(1)>;
qcom,pre-scaling = <1 1>;
label = "pmc8280_1_die_temp";
};
channel@144 {
reg = <PM8350_ADC7_AMUX_THM1_100K_PU(1)>;
qcom,hw-settle-time = <200>;
@ -902,12 +879,6 @@
label = "sys_therm4";
};
channel@303 {
reg = <PM8350_ADC7_DIE_TEMP(3)>;
qcom,pre-scaling = <1 1>;
label = "pmc8280_2_die_temp";
};
channel@344 {
reg = <PM8350_ADC7_AMUX_THM1_100K_PU(3)>;
qcom,hw-settle-time = <200>;
@ -935,12 +906,6 @@
qcom,ratiometric;
label = "sys_therm8";
};
channel@403 {
reg = <PMR735A_ADC7_DIE_TEMP>;
qcom,pre-scaling = <1 1>;
label = "pmr735a_die_temp";
};
};
&qup0 {
@ -1202,7 +1167,7 @@
};
&vamacro {
pinctrl-0 = <&dmic01_default>, <&dmic02_default>;
pinctrl-0 = <&dmic01_default>, <&dmic23_default>;
pinctrl-names = "default";
vdd-micb-supply = <&vreg_s10b>;

39
arch/arm64/boot/dts/qcom/sc8280xp-pmics.dtsi
View File

@ -3,6 +3,9 @@
* Copyright (c) 2022, Linaro Limited
*/
#include <dt-bindings/iio/qcom,spmi-adc7-pm8350.h>
#include <dt-bindings/iio/qcom,spmi-adc7-pmk8350.h>
#include <dt-bindings/iio/qcom,spmi-adc7-pmr735a.h>
#include <dt-bindings/input/input.h>
#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/spmi/spmi.h>
@ -84,7 +87,37 @@
#address-cells = <1>;
#size-cells = <0>;
#io-channel-cells = <1>;
status = "disabled";
channel@3 {
reg = <PMK8350_ADC7_DIE_TEMP>;
qcom,pre-scaling = <1 1>;
label = "pmk8350_die_temp";
};
channel@44 {
reg = <PMK8350_ADC7_AMUX_THM1_100K_PU>;
qcom,hw-settle-time = <200>;
qcom,ratiometric;
label = "pmk8350_xo_therm";
};
channel@103 {
reg = <PM8350_ADC7_DIE_TEMP(1)>;
qcom,pre-scaling = <1 1>;
label = "pmc8280_1_die_temp";
};
channel@303 {
reg = <PM8350_ADC7_DIE_TEMP(3)>;
qcom,pre-scaling = <1 1>;
label = "pmc8280_2_die_temp";
};
channel@403 {
reg = <PMR735A_ADC7_DIE_TEMP>;
qcom,pre-scaling = <1 1>;
label = "pmr735a_die_temp";
};
};
pmk8280_adc_tm: adc-tm@3400 {
@ -126,6 +159,8 @@
compatible = "qcom,spmi-temp-alarm";
reg = <0xa00>;
interrupts-extended = <&spmi_bus 0x1 0xa 0x0 IRQ_TYPE_EDGE_BOTH>;
io-channels = <&pmk8280_vadc PM8350_ADC7_DIE_TEMP(1)>;
io-channel-names = "thermal";
#thermal-sensor-cells = <0>;
};
@ -178,6 +213,8 @@
compatible = "qcom,spmi-temp-alarm";
reg = <0xa00>;
interrupts-extended = <&spmi_bus 0x2 0xa 0x0 IRQ_TYPE_EDGE_BOTH>;
io-channels = <&pmk8280_vadc PM8350_ADC7_DIE_TEMP(3)>;
io-channel-names = "thermal";
#thermal-sensor-cells = <0>;
};

601
arch/arm64/boot/dts/qcom/sc8280xp.dtsi
View File

@ -2257,9 +2257,12 @@
compatible = "qcom,sc8280xp-qmp-ufs-phy";
reg = <0 0x01d87000 0 0x1000>;
clocks = <&gcc GCC_UFS_CARD_CLKREF_CLK>,
<&gcc GCC_UFS_PHY_PHY_AUX_CLK>;
clock-names = "ref", "ref_aux";
clocks = <&rpmhcc RPMH_CXO_CLK>,
<&gcc GCC_UFS_PHY_PHY_AUX_CLK>,
<&gcc GCC_UFS_CARD_CLKREF_CLK>;
clock-names = "ref",
"ref_aux",
"qref";
power-domains = <&gcc UFS_PHY_GDSC>;
@ -2319,9 +2322,12 @@
compatible = "qcom,sc8280xp-qmp-ufs-phy";
reg = <0 0x01da7000 0 0x1000>;
clocks = <&gcc GCC_UFS_1_CARD_CLKREF_CLK>,
<&gcc GCC_UFS_CARD_PHY_AUX_CLK>;
clock-names = "ref", "ref_aux";
clocks = <&rpmhcc RPMH_CXO_CLK>,
<&gcc GCC_UFS_CARD_PHY_AUX_CLK>,
<&gcc GCC_UFS_1_CARD_CLKREF_CLK>;
clock-names = "ref",
"ref_aux",
"qref";
power-domains = <&gcc UFS_CARD_GDSC>;
@ -2978,7 +2984,7 @@
};
};
dmic02_default: dmic02-default-state {
dmic23_default: dmic23-default-state {
clk-pins {
pins = "gpio8";
function = "dmic2_clk";
@ -2994,7 +3000,7 @@
};
};
dmic02_sleep: dmic02-sleep-state {
dmic23_sleep: dmic23-sleep-state {
clk-pins {
pins = "gpio8";
function = "dmic2_clk";
@ -3451,6 +3457,404 @@
};
};
cci0: cci@ac4a000 {
compatible = "qcom,sc8280xp-cci", "qcom,msm8996-cci";
reg = <0 0x0ac4a000 0 0x1000>;
interrupts = <GIC_SPI 460 IRQ_TYPE_EDGE_RISING>;
clocks = <&camcc CAMCC_CAMNOC_AXI_CLK>,
<&camcc CAMCC_SLOW_AHB_CLK_SRC>,
<&camcc CAMCC_CPAS_AHB_CLK>,
<&camcc CAMCC_CCI_0_CLK>;
clock-names = "camnoc_axi",
"slow_ahb_src",
"cpas_ahb",
"cci";
power-domains = <&camcc TITAN_TOP_GDSC>;
pinctrl-0 = <&cci0_default>;
pinctrl-1 = <&cci0_sleep>;
pinctrl-names = "default", "sleep";
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
cci0_i2c0: i2c-bus@0 {
reg = <0>;
clock-frequency = <1000000>;
#address-cells = <1>;
#size-cells = <0>;
};
cci0_i2c1: i2c-bus@1 {
reg = <1>;
clock-frequency = <1000000>;
#address-cells = <1>;
#size-cells = <0>;
};
};
cci1: cci@ac4b000 {
compatible = "qcom,sc8280xp-cci", "qcom,msm8996-cci";
reg = <0 0x0ac4b000 0 0x1000>;
interrupts = <GIC_SPI 271 IRQ_TYPE_EDGE_RISING>;
clocks = <&camcc CAMCC_CAMNOC_AXI_CLK>,
<&camcc CAMCC_SLOW_AHB_CLK_SRC>,
<&camcc CAMCC_CPAS_AHB_CLK>,
<&camcc CAMCC_CCI_1_CLK>;
clock-names = "camnoc_axi",
"slow_ahb_src",
"cpas_ahb",
"cci";
power-domains = <&camcc TITAN_TOP_GDSC>;
pinctrl-0 = <&cci1_default>;
pinctrl-1 = <&cci1_sleep>;
pinctrl-names = "default", "sleep";
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
cci1_i2c0: i2c-bus@0 {
reg = <0>;
clock-frequency = <1000000>;
#address-cells = <1>;
#size-cells = <0>;
};
cci1_i2c1: i2c-bus@1 {
reg = <1>;
clock-frequency = <1000000>;
#address-cells = <1>;
#size-cells = <0>;
};
};
cci2: cci@ac4c000 {
compatible = "qcom,sc8280xp-cci", "qcom,msm8996-cci";
reg = <0 0x0ac4c000 0 0x1000>;
interrupts = <GIC_SPI 651 IRQ_TYPE_EDGE_RISING>;
clocks = <&camcc CAMCC_CAMNOC_AXI_CLK>,
<&camcc CAMCC_SLOW_AHB_CLK_SRC>,
<&camcc CAMCC_CPAS_AHB_CLK>,
<&camcc CAMCC_CCI_2_CLK>;
clock-names = "camnoc_axi",
"slow_ahb_src",
"cpas_ahb",
"cci";
power-domains = <&camcc TITAN_TOP_GDSC>;
pinctrl-0 = <&cci2_default>;
pinctrl-1 = <&cci2_sleep>;
pinctrl-names = "default", "sleep";
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
cci2_i2c0: i2c-bus@0 {
reg = <0>;
clock-frequency = <1000000>;
#address-cells = <1>;
#size-cells = <0>;
};
cci2_i2c1: i2c-bus@1 {
reg = <1>;
clock-frequency = <1000000>;
#address-cells = <1>;
#size-cells = <0>;
};
};
cci3: cci@ac4d000 {
compatible = "qcom,sc8280xp-cci", "qcom,msm8996-cci";
reg = <0 0x0ac4d000 0 0x1000>;
interrupts = <GIC_SPI 650 IRQ_TYPE_EDGE_RISING>;
clocks = <&camcc CAMCC_CAMNOC_AXI_CLK>,
<&camcc CAMCC_SLOW_AHB_CLK_SRC>,
<&camcc CAMCC_CPAS_AHB_CLK>,
<&camcc CAMCC_CCI_3_CLK>;
clock-names = "camnoc_axi",
"slow_ahb_src",
"cpas_ahb",
"cci";
power-domains = <&camcc TITAN_TOP_GDSC>;
pinctrl-0 = <&cci3_default>;
pinctrl-1 = <&cci3_sleep>;
pinctrl-names = "default", "sleep";
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
cci3_i2c0: i2c-bus@0 {
reg = <0>;
clock-frequency = <1000000>;
#address-cells = <1>;
#size-cells = <0>;
};
cci3_i2c1: i2c-bus@1 {
reg = <1>;
clock-frequency = <1000000>;
#address-cells = <1>;
#size-cells = <0>;
};
};
camss: camss@ac5a000 {
compatible = "qcom,sc8280xp-camss";
reg = <0 0x0ac5a000 0 0x2000>,
<0 0x0ac5c000 0 0x2000>,
<0 0x0ac65000 0 0x2000>,
<0 0x0ac67000 0 0x2000>,
<0 0x0acaf000 0 0x4000>,
<0 0x0acb3000 0 0x1000>,
<0 0x0acb6000 0 0x4000>,
<0 0x0acba000 0 0x1000>,
<0 0x0acbd000 0 0x4000>,
<0 0x0acc1000 0 0x1000>,
<0 0x0acc4000 0 0x4000>,
<0 0x0acc8000 0 0x1000>,
<0 0x0accb000 0 0x4000>,
<0 0x0accf000 0 0x1000>,
<0 0x0acd2000 0 0x4000>,
<0 0x0acd6000 0 0x1000>,
<0 0x0acd9000 0 0x4000>,
<0 0x0acdd000 0 0x1000>,
<0 0x0ace0000 0 0x4000>,
<0 0x0ace4000 0 0x1000>;
reg-names = "csiphy2",
"csiphy3",
"csiphy0",
"csiphy1",
"vfe0",
"csid0",
"vfe1",
"csid1",
"vfe2",
"csid2",
"vfe_lite0",
"csid0_lite",
"vfe_lite1",
"csid1_lite",
"vfe_lite2",
"csid2_lite",
"vfe_lite3",
"csid3_lite",
"vfe3",
"csid3";
interrupts = <GIC_SPI 359 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 360 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 448 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 464 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 465 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 466 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 467 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 468 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 469 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 477 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 478 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 479 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 640 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 641 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 758 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 759 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 760 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 761 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 762 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 764 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "csid1_lite",
"vfe_lite1",
"csiphy3",
"csid0",
"vfe0",
"csid1",
"vfe1",
"csid0_lite",
"vfe_lite0",
"csiphy0",
"csiphy1",
"csiphy2",
"csid2",
"vfe2",
"csid3_lite",
"csid2_lite",
"vfe_lite3",
"vfe_lite2",
"csid3",
"vfe3";
power-domains = <&camcc IFE_0_GDSC>,
<&camcc IFE_1_GDSC>,
<&camcc IFE_2_GDSC>,
<&camcc IFE_3_GDSC>,
<&camcc TITAN_TOP_GDSC>;
power-domain-names = "ife0",
"ife1",
"ife2",
"ife3",
"top";
clocks = <&camcc CAMCC_CAMNOC_AXI_CLK>,
<&camcc CAMCC_CPAS_AHB_CLK>,
<&camcc CAMCC_CSIPHY0_CLK>,
<&camcc CAMCC_CSI0PHYTIMER_CLK>,
<&camcc CAMCC_CSIPHY1_CLK>,
<&camcc CAMCC_CSI1PHYTIMER_CLK>,
<&camcc CAMCC_CSIPHY2_CLK>,
<&camcc CAMCC_CSI2PHYTIMER_CLK>,
<&camcc CAMCC_CSIPHY3_CLK>,
<&camcc CAMCC_CSI3PHYTIMER_CLK>,
<&camcc CAMCC_IFE_0_AXI_CLK>,
<&camcc CAMCC_IFE_0_CLK>,
<&camcc CAMCC_IFE_0_CPHY_RX_CLK>,
<&camcc CAMCC_IFE_0_CSID_CLK>,
<&camcc CAMCC_IFE_1_AXI_CLK>,
<&camcc CAMCC_IFE_1_CLK>,
<&camcc CAMCC_IFE_1_CPHY_RX_CLK>,
<&camcc CAMCC_IFE_1_CSID_CLK>,
<&camcc CAMCC_IFE_2_AXI_CLK>,
<&camcc CAMCC_IFE_2_CLK>,
<&camcc CAMCC_IFE_2_CPHY_RX_CLK>,
<&camcc CAMCC_IFE_2_CSID_CLK>,
<&camcc CAMCC_IFE_3_AXI_CLK>,
<&camcc CAMCC_IFE_3_CLK>,
<&camcc CAMCC_IFE_3_CPHY_RX_CLK>,
<&camcc CAMCC_IFE_3_CSID_CLK>,
<&camcc CAMCC_IFE_LITE_0_CLK>,
<&camcc CAMCC_IFE_LITE_0_CPHY_RX_CLK>,
<&camcc CAMCC_IFE_LITE_0_CSID_CLK>,
<&camcc CAMCC_IFE_LITE_1_CLK>,
<&camcc CAMCC_IFE_LITE_1_CPHY_RX_CLK>,
<&camcc CAMCC_IFE_LITE_1_CSID_CLK>,
<&camcc CAMCC_IFE_LITE_2_CLK>,
<&camcc CAMCC_IFE_LITE_2_CPHY_RX_CLK>,
<&camcc CAMCC_IFE_LITE_2_CSID_CLK>,
<&camcc CAMCC_IFE_LITE_3_CLK>,
<&camcc CAMCC_IFE_LITE_3_CPHY_RX_CLK>,
<&camcc CAMCC_IFE_LITE_3_CSID_CLK>,
<&gcc GCC_CAMERA_HF_AXI_CLK>,
<&gcc GCC_CAMERA_SF_AXI_CLK>;
clock-names = "camnoc_axi",
"cpas_ahb",
"csiphy0",
"csiphy0_timer",
"csiphy1",
"csiphy1_timer",
"csiphy2",
"csiphy2_timer",
"csiphy3",
"csiphy3_timer",
"vfe0_axi",
"vfe0",
"vfe0_cphy_rx",
"vfe0_csid",
"vfe1_axi",
"vfe1",
"vfe1_cphy_rx",
"vfe1_csid",
"vfe2_axi",
"vfe2",
"vfe2_cphy_rx",
"vfe2_csid",
"vfe3_axi",
"vfe3",
"vfe3_cphy_rx",
"vfe3_csid",
"vfe_lite0",
"vfe_lite0_cphy_rx",
"vfe_lite0_csid",
"vfe_lite1",
"vfe_lite1_cphy_rx",
"vfe_lite1_csid",
"vfe_lite2",
"vfe_lite2_cphy_rx",
"vfe_lite2_csid",
"vfe_lite3",
"vfe_lite3_cphy_rx",
"vfe_lite3_csid",
"gcc_axi_hf",
"gcc_axi_sf";
iommus = <&apps_smmu 0x2000 0x4e0>,
<&apps_smmu 0x2020 0x4e0>,
<&apps_smmu 0x2040 0x4e0>,
<&apps_smmu 0x2060 0x4e0>,
<&apps_smmu 0x2080 0x4e0>,
<&apps_smmu 0x20e0 0x4e0>,
<&apps_smmu 0x20c0 0x4e0>,
<&apps_smmu 0x20a0 0x4e0>,
<&apps_smmu 0x2400 0x4e0>,
<&apps_smmu 0x2420 0x4e0>,
<&apps_smmu 0x2440 0x4e0>,
<&apps_smmu 0x2460 0x4e0>,
<&apps_smmu 0x2480 0x4e0>,
<&apps_smmu 0x24e0 0x4e0>,
<&apps_smmu 0x24c0 0x4e0>,
<&apps_smmu 0x24a0 0x4e0>;
interconnects = <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_CAMERA_CFG 0>,
<&mmss_noc MASTER_CAMNOC_HF 0 &mc_virt SLAVE_EBI1 0>,
<&mmss_noc MASTER_CAMNOC_SF 0 &mc_virt SLAVE_EBI1 0>,
<&mmss_noc MASTER_CAMNOC_ICP 0 &mc_virt SLAVE_EBI1 0>;
interconnect-names = "cam_ahb",
"cam_hf_mnoc",
"cam_sf_mnoc",
"cam_sf_icp_mnoc";
status = "disabled";
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
#address-cells = <1>;
#size-cells = <0>;
};
port@1 {
reg = <1>;
#address-cells = <1>;
#size-cells = <0>;
};
port@2 {
reg = <2>;
#address-cells = <1>;
#size-cells = <0>;
};
port@3 {
reg = <3>;
#address-cells = <1>;
#size-cells = <0>;
};
};
};
camcc: clock-controller@ad00000 {
compatible = "qcom,sc8280xp-camcc";
reg = <0 0x0ad00000 0 0x20000>;
@ -4011,6 +4415,28 @@
interrupt-controller;
};
tsens2: thermal-sensor@c251000 {
compatible = "qcom,sc8280xp-tsens", "qcom,tsens-v2";
reg = <0 0x0c251000 0 0x1ff>,
<0 0x0c224000 0 0x8>;
#qcom,sensors = <11>;
interrupts-extended = <&pdc 122 IRQ_TYPE_LEVEL_HIGH>,
<&pdc 124 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "uplow", "critical";
#thermal-sensor-cells = <1>;
};
tsens3: thermal-sensor@c252000 {
compatible = "qcom,sc8280xp-tsens", "qcom,tsens-v2";
reg = <0 0x0c252000 0 0x1ff>,
<0 0x0c225000 0 0x8>;
#qcom,sensors = <5>;
interrupts-extended = <&pdc 123 IRQ_TYPE_LEVEL_HIGH>,
<&pdc 125 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "uplow", "critical";
#thermal-sensor-cells = <1>;
};
tsens0: thermal-sensor@c263000 {
compatible = "qcom,sc8280xp-tsens", "qcom,tsens-v2";
reg = <0 0x0c263000 0 0x1ff>, /* TM */
@ -4076,6 +4502,150 @@
#interrupt-cells = <2>;
gpio-ranges = <&tlmm 0 0 230>;
wakeup-parent = <&pdc>;
cci0_default: cci0-default-state {
cci0_i2c0_default: cci0-i2c0-default-pins {
/* cci_i2c_sda0, cci_i2c_scl0 */
pins = "gpio113", "gpio114";
function = "cci_i2c";
drive-strength = <2>;
bias-pull-up;
};
cci0_i2c1_default: cci0-i2c1-default-pins {
/* cci_i2c_sda1, cci_i2c_scl1 */
pins = "gpio115", "gpio116";
function = "cci_i2c";
drive-strength = <2>;
bias-pull-up;
};
};
cci0_sleep: cci0-sleep-state {
cci0_i2c0_sleep: cci0-i2c0-sleep-pins {
/* cci_i2c_sda0, cci_i2c_scl0 */
pins = "gpio113", "gpio114";
function = "cci_i2c";
drive-strength = <2>;
bias-pull-down;
};
cci0_i2c1_sleep: cci0-i2c1-sleep-pins {
/* cci_i2c_sda1, cci_i2c_scl1 */
pins = "gpio115", "gpio116";
function = "cci_i2c";
drive-strength = <2>;
bias-pull-down;
};
};
cci1_default: cci1-default-state {
cci1_i2c0_default: cci1-i2c0-default-pins {
/* cci_i2c_sda2, cci_i2c_scl2 */
pins = "gpio10","gpio11";
function = "cci_i2c";
drive-strength = <2>;
bias-pull-up;
};
cci1_i2c1_default: cci1-i2c1-default-pins {
/* cci_i2c_sda3, cci_i2c_scl3 */
pins = "gpio123","gpio124";
function = "cci_i2c";
drive-strength = <2>;
bias-pull-up;
};
};
cci1_sleep: cci1-sleep-state {
cci1_i2c0_sleep: cci1-i2c0-sleep-pins {
/* cci_i2c_sda2, cci_i2c_scl2 */
pins = "gpio10","gpio11";
function = "cci_i2c";
drive-strength = <2>;
bias-pull-down;
};
cci1_i2c1_sleep: cci1-i2c1-sleep-pins {
/* cci_i2c_sda3, cci_i2c_scl3 */
pins = "gpio123","gpio124";
function = "cci_i2c";
drive-strength = <2>;
bias-pull-down;
};
};
cci2_default: cci2-default-state {
cci2_i2c0_default: cci2-i2c0-default-pins {
/* cci_i2c_sda4, cci_i2c_scl4 */
pins = "gpio117","gpio118";
function = "cci_i2c";
drive-strength = <2>;
bias-pull-up;
};
cci2_i2c1_default: cci2-i2c1-default-pins {
/* cci_i2c_sda5, cci_i2c_scl5 */
pins = "gpio12","gpio13";
function = "cci_i2c";
drive-strength = <2>;
bias-pull-up;
};
};
cci2_sleep: cci2-sleep-state {
cci2_i2c0_sleep: cci2-i2c0-sleep-pins {
/* cci_i2c_sda4, cci_i2c_scl4 */
pins = "gpio117","gpio118";
function = "cci_i2c";
drive-strength = <2>;
bias-pull-down;
};
cci2_i2c1_sleep: cci2-i2c1-sleep-pins {
/* cci_i2c_sda5, cci_i2c_scl5 */
pins = "gpio12","gpio13";
function = "cci_i2c";
drive-strength = <2>;
bias-pull-down;
};
};
cci3_default: cci3-default-state {
cci3_i2c0_default: cci3-i2c0-default-pins {
/* cci_i2c_sda6, cci_i2c_scl6 */
pins = "gpio145","gpio146";
function = "cci_i2c";
drive-strength = <2>;
bias-pull-up;
};
cci3_i2c1_default: cci3-i2c1-default-pins {
/* cci_i2c_sda7, cci_i2c_scl7 */
pins = "gpio164","gpio165";
function = "cci_i2c";
drive-strength = <2>;
bias-pull-up;
};
};
cci3_sleep: cci3-sleep-state {
cci3_i2c0_sleep: cci3-i2c0-sleep-pins {
/* cci_i2c_sda6, cci_i2c_scl6 */
pins = "gpio145","gpio146";
function = "cci_i2c";
drive-strength = <2>;
bias-pull-down;
};
cci3_i2c1_sleep: cci3-i2c1-sleep-pins {
/* cci_i2c_sda7, cci_i2c_scl7 */
pins = "gpio164","gpio165";
function = "cci_i2c";
drive-strength = <2>;
bias-pull-down;
};
};
};
apps_smmu: iommu@15000000 {
@ -5212,6 +5782,21 @@
};
};
gpu-thermal {
polling-delay-passive = <0>;
polling-delay = <0>;
thermal-sensors = <&tsens2 2>;
trips {
gpu-crit {
temperature = <110000>;
hysteresis = <1000>;
type = "critical";
};
};
};
mem-thermal {
polling-delay-passive = <250>;
polling-delay = <1000>;

5
arch/arm64/boot/dts/qcom/sda660-inforce-ifc6560.dts
View File

@ -461,3 +461,8 @@
dr_mode = "peripheral";
extcon = <&extcon_usb>;
};
&usb3_qmpphy {
vdda-phy-supply = <&vreg_l1b_0p925>;
status = "okay";
};

2
arch/arm64/boot/dts/qcom/sdm450-motorola-ali.dts
View File

@ -4,7 +4,7 @@
*/
/dts-v1/;
#include "msm8953.dtsi"
#include "sdm450.dtsi"
#include "pm8953.dtsi"
#include "pmi8950.dtsi"

14
arch/arm64/boot/dts/qcom/sdm450.dtsi Normal file
View File

@ -0,0 +1,14 @@
// SPDX-License-Identifier: BSD-3-Clause
/* Copyright (c) 2023, Luca Weiss <luca@z3ntu.xyz> */
#include "msm8953.dtsi"
&gpu_opp_table {
/delete-node/ opp-650000000;
opp-600000000 {
opp-hz = /bits/ 64 <600000000>;
opp-supported-hw = <0xff>;
required-opps = <&rpmpd_opp_turbo>;
};
};

16
arch/arm64/boot/dts/qcom/sdm630-sony-xperia-nile.dtsi
View File

@ -241,6 +241,16 @@
};
};
&pm660l_wled {
status = "okay";
qcom,switching-freq = <800>;
qcom,ovp-millivolt = <29600>;
qcom,current-boost-limit = <970>;
qcom,current-limit-microamp = <17500>;
qcom,num-strings = <2>;
};
&pon_pwrkey {
status = "okay";
};
@ -658,10 +668,16 @@
};
&usb3 {
qcom,select-utmi-as-pipe-clk;
status = "okay";
};
&usb3_dwc3 {
maximum-speed = "high-speed";
phys = <&qusb2phy0>;
phy-names = "usb2-phy";
dr_mode = "peripheral";
extcon = <&extcon_usb>;
};

62
arch/arm64/boot/dts/qcom/sdm630.dtsi
View File

@ -13,6 +13,7 @@
#include <dt-bindings/power/qcom-rpmpd.h>
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/thermal/thermal.h>
#include <dt-bindings/soc/qcom,apr.h>
/ {
@ -1100,6 +1101,7 @@
interconnect-names = "gfx-mem";
operating-points-v2 = <&gpu_sdm630_opp_table>;
#cooling-cells = <2>;
status = "disabled";
@ -1281,12 +1283,16 @@
<&gcc GCC_USB30_MASTER_CLK>;
assigned-clock-rates = <19200000>, <120000000>;
interrupts = <GIC_SPI 347 IRQ_TYPE_LEVEL_HIGH>,
interrupts = <GIC_SPI 180 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 347 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 243 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "hs_phy_irq", "ss_phy_irq";
interrupt-names = "pwr_event",
"qusb2_phy",
"hs_phy_irq",
"ss_phy_irq";
power-domains = <&gcc USB_30_GDSC>;
qcom,select-utmi-as-pipe-clk;
resets = <&gcc GCC_USB_30_BCR>;
@ -1297,17 +1303,38 @@
snps,dis_u2_susphy_quirk;
snps,dis_enblslpm_quirk;
/*
* SDM630 technically supports USB3 but I
* haven't seen any devices making use of it.
*/
maximum-speed = "high-speed";
phys = <&qusb2phy0>;
phy-names = "usb2-phy";
phys = <&qusb2phy0>, <&usb3_qmpphy>;
phy-names = "usb2-phy", "usb3-phy";
snps,hird-threshold = /bits/ 8 <0>;
};
};
usb3_qmpphy: phy@c010000 {
compatible = "qcom,sdm660-qmp-usb3-phy";
reg = <0x0c010000 0x1000>;
clocks = <&gcc GCC_USB3_PHY_AUX_CLK>,
<&gcc GCC_USB3_CLKREF_CLK>,
<&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>,
<&gcc GCC_USB3_PHY_PIPE_CLK>;
clock-names = "aux",
"ref",
"cfg_ahb",
"pipe";
clock-output-names = "usb3_phy_pipe_clk_src";
#clock-cells = <0>;
#phy-cells = <0>;
resets = <&gcc GCC_USB3_PHY_BCR>,
<&gcc GCC_USB3PHY_PHY_BCR>;
reset-names = "phy",
"phy_phy";
qcom,tcsr-reg = <&tcsr_regs_1 0x6b244>;
status = "disabled";
};
qusb2phy0: phy@c012000 {
compatible = "qcom,sdm660-qusb2-phy";
reg = <0x0c012000 0x180>;
@ -1463,8 +1490,12 @@
<&gcc GCC_USB20_MASTER_CLK>;
assigned-clock-rates = <19200000>, <60000000>;
interrupts = <GIC_SPI 348 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "hs_phy_irq";
interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 348 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "pwr_event",
"qusb2_phy",
"hs_phy_irq";
qcom,select-utmi-as-pipe-clk;
@ -2551,6 +2582,13 @@
thermal-sensors = <&tsens 8>;
cooling-maps {
map0 {
trip = <&gpu_alert0>;
cooling-device = <&adreno_gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
};
};
trips {
gpu_alert0: trip-point0 {
temperature = <90000>;

8
arch/arm64/boot/dts/qcom/sdm632.dtsi
View File

@ -79,3 +79,11 @@
compatible = "qcom,kryo250";
capacity-dmips-mhz = <1980>;
};
&gpu_opp_table {
opp-725000000 {
opp-hz = /bits/ 64 <725000000>;
opp-supported-hw = <0xff>;
required-opps = <&rpmpd_opp_turbo>;
};
};

6
arch/arm64/boot/dts/qcom/sdm660-xiaomi-lavender.dts
View File

@ -413,10 +413,16 @@
};
&usb3 {
qcom,select-utmi-as-pipe-clk;
status = "okay";
};
&usb3_dwc3 {
maximum-speed = "high-speed";
phys = <&qusb2phy0>;
phy-names = "usb2-phy";
dr_mode = "peripheral";
extcon = <&extcon_usb>;
};

14
arch/arm64/boot/dts/qcom/sdm670.dtsi
View File

@ -1320,12 +1320,16 @@
<&gcc GCC_USB30_PRIM_MASTER_CLK>;
assigned-clock-rates = <19200000>, <150000000>;
interrupts-extended = <&intc GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>,
<&pdc 6 IRQ_TYPE_LEVEL_HIGH>,
interrupts-extended = <&intc GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>,
<&intc GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>,
<&pdc 9 IRQ_TYPE_EDGE_BOTH>,
<&pdc 8 IRQ_TYPE_EDGE_BOTH>,
<&pdc 9 IRQ_TYPE_EDGE_BOTH>;
interrupt-names = "hs_phy_irq", "ss_phy_irq",
"dm_hs_phy_irq", "dp_hs_phy_irq";
<&pdc 6 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "pwr_event",
"hs_phy_irq",
"dp_hs_phy_irq",
"dm_hs_phy_irq",
"ss_phy_irq";
power-domains = <&gcc USB30_PRIM_GDSC>;

1
arch/arm64/boot/dts/qcom/sdm845-cheza.dtsi
View File

@ -852,6 +852,7 @@ ap_ts_i2c: &i2c14 {
pinctrl-names = "default";
pinctrl-0 = <&ec_ap_int_l>;
spi-max-frequency = <3000000>;
wakeup-source;
cros_ec_pwm: pwm {
compatible = "google,cros-ec-pwm";

2
arch/arm64/boot/dts/qcom/sdm845-db845c.dts
View File

@ -580,7 +580,7 @@
&pcie0 {
status = "okay";
perst-gpios = <&tlmm 35 GPIO_ACTIVE_LOW>;
enable-gpio = <&tlmm 134 GPIO_ACTIVE_HIGH>;
wake-gpios = <&tlmm 134 GPIO_ACTIVE_HIGH>;
vddpe-3v3-supply = <&pcie0_3p3v_dual>;

8
arch/arm64/boot/dts/qcom/sdm845-oneplus-common.dtsi
View File

@ -508,13 +508,13 @@
};
&q6afedai {
qi2s@22 {
reg = <22>;
dai@22 {
reg = <QUATERNARY_MI2S_RX>;
qcom,sd-lines = <1>;
};
qi2s@23 {
reg = <23>;
dai@23 {
reg = <QUATERNARY_MI2S_TX>;
qcom,sd-lines = <0>;
};
};

2
arch/arm64/boot/dts/qcom/sdm845-shift-axolotl.dts
View File

@ -60,7 +60,7 @@
};
reserved-memory {
framebuffer_region@9d400000 {
framebuffer@9d400000 {
reg = <0x0 0x9d400000 0x0 (1080 * 2160 * 4)>;
no-map;
};

63
arch/arm64/boot/dts/qcom/sdm845.dtsi
View File

@ -2639,10 +2639,12 @@
compatible = "qcom,sdm845-qmp-ufs-phy";
reg = <0 0x01d87000 0 0x1000>;
clocks = <&rpmhcc RPMH_CXO_CLK>,
<&gcc GCC_UFS_PHY_PHY_AUX_CLK>,
<&gcc GCC_UFS_MEM_CLKREF_CLK>;
clock-names = "ref",
"ref_aux";
clocks = <&gcc GCC_UFS_MEM_CLKREF_CLK>,
<&gcc GCC_UFS_PHY_PHY_AUX_CLK>;
"ref_aux",
"qref";
resets = <&ufs_mem_hc 0>;
reset-names = "ufsphy";
@ -3366,8 +3368,8 @@
qcom,qmp = <&aoss_qmp>;
power-domains = <&rpmhpd SDM845_CX>,
<&rpmhpd SDM845_MX>;
power-domains = <&rpmhpd SDM845_LCX>,
<&rpmhpd SDM845_LMX>;
power-domain-names = "lcx", "lmx";
memory-region = <&slpi_mem>;
@ -4058,12 +4060,16 @@
<&gcc GCC_USB30_PRIM_MASTER_CLK>;
assigned-clock-rates = <19200000>, <150000000>;
interrupts-extended = <&intc GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>,
<&pdc_intc 6 IRQ_TYPE_LEVEL_HIGH>,
interrupts-extended = <&intc GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>,
<&intc GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>,
<&pdc_intc 9 IRQ_TYPE_EDGE_BOTH>,
<&pdc_intc 8 IRQ_TYPE_EDGE_BOTH>,
<&pdc_intc 9 IRQ_TYPE_EDGE_BOTH>;
interrupt-names = "hs_phy_irq", "ss_phy_irq",
"dm_hs_phy_irq", "dp_hs_phy_irq";
<&pdc_intc 6 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "pwr_event",
"hs_phy_irq",
"dp_hs_phy_irq",
"dm_hs_phy_irq",
"ss_phy_irq";
power-domains = <&gcc USB30_PRIM_GDSC>;
@ -4109,12 +4115,16 @@
<&gcc GCC_USB30_SEC_MASTER_CLK>;
assigned-clock-rates = <19200000>, <150000000>;
interrupts-extended = <&intc GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>,
<&pdc_intc 7 IRQ_TYPE_LEVEL_HIGH>,
interrupts-extended = <&intc GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>,
<&intc GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>,
<&pdc_intc 11 IRQ_TYPE_EDGE_BOTH>,
<&pdc_intc 10 IRQ_TYPE_EDGE_BOTH>,
<&pdc_intc 11 IRQ_TYPE_EDGE_BOTH>;
interrupt-names = "hs_phy_irq", "ss_phy_irq",
"dm_hs_phy_irq", "dp_hs_phy_irq";
<&pdc_intc 7 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "pwr_event",
"hs_phy_irq",
"dp_hs_phy_irq",
"dm_hs_phy_irq",
"ss_phy_irq";
power-domains = <&gcc USB30_SEC_GDSC>;
@ -4760,6 +4770,7 @@
operating-points-v2 = <&gpu_opp_table>;
qcom,gmu = <&gmu>;
#cooling-cells = <2>;
interconnects = <&mem_noc MASTER_GFX3D 0 &mem_noc SLAVE_EBI1 0>;
interconnect-names = "gfx-mem";
@ -5568,7 +5579,7 @@
hysteresis = <2000>;
type = "hot";
};
cluster0_crit: cluster0_crit {
cluster0_crit: cluster0-crit {
temperature = <110000>;
hysteresis = <2000>;
type = "critical";
@ -5588,7 +5599,7 @@
hysteresis = <2000>;
type = "hot";
};
cluster1_crit: cluster1_crit {
cluster1_crit: cluster1-crit {
temperature = <110000>;
hysteresis = <2000>;
type = "critical";
@ -5602,8 +5613,15 @@
thermal-sensors = <&tsens0 11>;
cooling-maps {
map0 {
trip = <&gpu_top_alert0>;
cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
};
};
trips {
gpu1_alert0: trip-point0 {
gpu_top_alert0: trip-point0 {
temperature = <90000>;
hysteresis = <2000>;
type = "hot";
@ -5617,8 +5635,15 @@
thermal-sensors = <&tsens0 12>;
cooling-maps {
map0 {
trip = <&gpu_bottom_alert0>;
cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
};
};
trips {
gpu2_alert0: trip-point0 {
gpu_bottom_alert0: trip-point0 {
temperature = <90000>;
hysteresis = <2000>;
type = "hot";

2
arch/arm64/boot/dts/qcom/sm4450.dtsi
View File

@ -17,7 +17,7 @@
chosen { };
clocks{
clocks {
xo_board: xo-board {
compatible = "fixed-clock";
clock-frequency = <76800000>;

95
arch/arm64/boot/dts/qcom/sm6115.dtsi
View File

@ -14,6 +14,7 @@
#include <dt-bindings/interconnect/qcom,sm6115.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/power/qcom-rpmpd.h>
#include <dt-bindings/thermal/thermal.h>
/ {
interrupt-parent = <&intc>;
@ -614,6 +615,11 @@
#hwlock-cells = <1>;
};
tcsr_regs: syscon@3c0000 {
compatible = "qcom,sm6115-tcsr", "syscon";
reg = <0x0 0x003c0000 0x0 0x40000>;
};
tlmm: pinctrl@500000 {
compatible = "qcom,sm6115-tlmm";
reg = <0x0 0x00500000 0x0 0x400000>,
@ -878,8 +884,31 @@
clock-output-names = "usb3_phy_pipe_clk_src";
#phy-cells = <0>;
orientation-switch;
qcom,tcsr-reg = <&tcsr_regs 0xb244>;
status = "disabled";
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
usb_qmpphy_out: endpoint {
};
};
port@1 {
reg = <1>;
usb_qmpphy_usb_ss_in: endpoint {
remote-endpoint = <&usb_dwc3_ss>;
};
};
};
};
system_noc: interconnect@1880000 {
@ -1194,8 +1223,12 @@
compatible = "qcom,sm6115-qmp-ufs-phy";
reg = <0x0 0x04807000 0x0 0x1000>;
clocks = <&gcc GCC_UFS_CLKREF_CLK>, <&gcc GCC_UFS_PHY_PHY_AUX_CLK>;
clock-names = "ref", "ref_aux";
clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>,
<&gcc GCC_UFS_PHY_PHY_AUX_CLK>,
<&gcc GCC_UFS_CLKREF_CLK>;
clock-names = "ref",
"ref_aux",
"qref";
resets = <&ufs_mem_hc 0>;
reset-names = "ufsphy";
@ -1586,9 +1619,14 @@
<&gcc GCC_USB30_PRIM_MASTER_CLK>;
assigned-clock-rates = <19200000>, <66666667>;
interrupts = <GIC_SPI 260 IRQ_TYPE_LEVEL_HIGH>,
interrupts = <GIC_SPI 302 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 260 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 254 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 422 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "hs_phy_irq", "ss_phy_irq";
interrupt-names = "pwr_event",
"qusb2_phy",
"hs_phy_irq",
"ss_phy_irq";
resets = <&gcc GCC_USB30_PRIM_BCR>;
power-domains = <&gcc GCC_USB30_PRIM_GDSC>;
@ -1600,7 +1638,6 @@
interconnect-names = "usb-ddr",
"apps-usb";
qcom,select-utmi-as-pipe-clk;
status = "disabled";
usb_dwc3: usb@4e00000 {
@ -1615,6 +1652,28 @@
snps,has-lpm-erratum;
snps,hird-threshold = /bits/ 8 <0x10>;
snps,usb3_lpm_capable;
usb-role-switch;
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
usb_dwc3_hs: endpoint {
};
};
port@1 {
reg = <1>;
usb_dwc3_ss: endpoint {
remote-endpoint = <&usb_qmpphy_usb_ss_in>;
};
};
};
};
};
@ -1646,6 +1705,7 @@
nvmem-cells = <&gpu_speed_bin>;
nvmem-cell-names = "speed_bin";
#cooling-cells = <2>;
status = "disabled";
@ -3085,7 +3145,7 @@
type = "passive";
};
cpu4_crit: cpu_crit {
cpu4_crit: cpu-crit {
temperature = <110000>;
hysteresis = <1000>;
type = "critical";
@ -3111,7 +3171,7 @@
type = "passive";
};
cpu5_crit: cpu_crit {
cpu5_crit: cpu-crit {
temperature = <110000>;
hysteresis = <1000>;
type = "critical";
@ -3137,7 +3197,7 @@
type = "passive";
};
cpu6_crit: cpu_crit {
cpu6_crit: cpu-crit {
temperature = <110000>;
hysteresis = <1000>;
type = "critical";
@ -3163,7 +3223,7 @@
type = "passive";
};
cpu7_crit: cpu_crit {
cpu7_crit: cpu-crit {
temperature = <110000>;
hysteresis = <1000>;
type = "critical";
@ -3189,7 +3249,7 @@
type = "passive";
};
cpu45_crit: cpu_crit {
cpu45_crit: cpu-crit {
temperature = <110000>;
hysteresis = <1000>;
type = "critical";
@ -3215,7 +3275,7 @@
type = "passive";
};
cpu67_crit: cpu_crit {
cpu67_crit: cpu-crit {
temperature = <110000>;
hysteresis = <1000>;
type = "critical";
@ -3241,7 +3301,7 @@
type = "passive";
};
cpu0123_crit: cpu_crit {
cpu0123_crit: cpu-crit {
temperature = <110000>;
hysteresis = <1000>;
type = "critical";
@ -3294,8 +3354,15 @@
polling-delay = <0>;
thermal-sensors = <&tsens0 15>;
cooling-maps {
map0 {
trip = <&gpu_alert0>;
cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
};
};
trips {
trip-point0 {
gpu_alert0: trip-point0 {
temperature = <115000>;
hysteresis = <5000>;
type = "passive";
@ -3304,7 +3371,7 @@
trip-point1 {
temperature = <125000>;
hysteresis = <1000>;
type = "passive";
type = "critical";
};
};
};

17
arch/arm64/boot/dts/qcom/sm6125.dtsi
View File

@ -812,10 +812,12 @@
compatible = "qcom,sm6125-qmp-ufs-phy";
reg = <0x04807000 0xdb8>;
clocks = <&gcc GCC_UFS_MEM_CLKREF_CLK>,
<&gcc GCC_UFS_PHY_PHY_AUX_CLK>;
clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>,
<&gcc GCC_UFS_PHY_PHY_AUX_CLK>,
<&gcc GCC_UFS_MEM_CLKREF_CLK>;
clock-names = "ref",
"ref_aux";
"ref_aux",
"qref";
resets = <&ufs_mem_hc 0>;
reset-names = "ufsphy";
@ -1185,9 +1187,14 @@
<&gcc GCC_USB30_PRIM_MASTER_CLK>;
assigned-clock-rates = <19200000>, <66666667>;
interrupts = <GIC_SPI 260 IRQ_TYPE_LEVEL_HIGH>,
interrupts = <GIC_SPI 302 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 260 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 254 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 422 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "hs_phy_irq", "ss_phy_irq";
interrupt-names = "pwr_event",
"qusb2_phy",
"hs_phy_irq",
"ss_phy_irq";
power-domains = <&gcc USB30_PRIM_GDSC>;
qcom,select-utmi-as-pipe-clk;

597
arch/arm64/boot/dts/qcom/sm6350.dtsi
View File

@ -19,6 +19,7 @@
#include <dt-bindings/phy/phy-qcom-qmp.h>
#include <dt-bindings/power/qcom-rpmpd.h>
#include <dt-bindings/soc/qcom,rpmh-rsc.h>
#include <dt-bindings/thermal/thermal.h>
/ {
interrupt-parent = <&intc>;
@ -1189,10 +1190,12 @@
compatible = "qcom,sm6350-qmp-ufs-phy";
reg = <0 0x01d87000 0 0x1000>;
clocks = <&rpmhcc RPMH_CXO_CLK>,
<&gcc GCC_UFS_PHY_PHY_AUX_CLK>,
<&gcc GCC_UFS_MEM_CLKREF_CLK>;
clock-names = "ref",
"ref_aux";
clocks = <&gcc GCC_UFS_MEM_CLKREF_CLK>,
<&gcc GCC_UFS_PHY_PHY_AUX_CLK>;
"ref_aux",
"qref";
resets = <&ufs_mem_hc 0>;
reset-names = "ufsphy";
@ -1325,10 +1328,11 @@
qcom,gmu = <&gmu>;
nvmem-cells = <&gpu_speed_bin>;
nvmem-cell-names = "speed_bin";
#cooling-cells = <2>;
status = "disabled";
zap-shader {
gpu_zap_shader: zap-shader {
memory-region = <&pil_gpu_mem>;
};
@ -1439,8 +1443,6 @@
operating-points-v2 = <&gmu_opp_table>;
status = "disabled";
gmu_opp_table: opp-table {
compatible = "operating-points-v2";
@ -1830,12 +1832,15 @@
"mock_utmi";
interrupts-extended = <&intc GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>,
<&pdc 17 IRQ_TYPE_LEVEL_HIGH>,
<&intc GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>,
<&pdc 14 IRQ_TYPE_EDGE_BOTH>,
<&pdc 15 IRQ_TYPE_EDGE_BOTH>,
<&pdc 14 IRQ_TYPE_EDGE_BOTH>;
interrupt-names = "hs_phy_irq", "ss_phy_irq",
"dm_hs_phy_irq", "dp_hs_phy_irq";
<&pdc 17 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "pwr_event",
"hs_phy_irq",
"dp_hs_phy_irq",
"dm_hs_phy_irq",
"ss_phy_irq";
power-domains = <&gcc USB30_PRIM_GDSC>;
@ -1966,6 +1971,13 @@
interrupt-controller;
#interrupt-cells = <1>;
interconnects = <&mmss_noc MASTER_MDP_PORT0 QCOM_ICC_TAG_ALWAYS
&clk_virt SLAVE_EBI_CH0 QCOM_ICC_TAG_ALWAYS>,
<&gem_noc MASTER_AMPSS_M0 QCOM_ICC_TAG_ACTIVE_ONLY
&config_noc SLAVE_DISPLAY_CFG QCOM_ICC_TAG_ACTIVE_ONLY>;
interconnect-names = "mdp0-mem",
"cpu-cfg";
clocks = <&gcc GCC_DISP_AHB_CLK>,
<&gcc GCC_DISP_AXI_CLK>,
<&dispcc DISP_CC_MDSS_MDP_CLK>;
@ -2698,6 +2710,569 @@
};
};
thermal-zones {
aoss0-thermal {
polling-delay-passive = <0>;
polling-delay = <0>;
thermal-sensors = <&tsens0 0>;
trips {
aoss0-crit {
temperature = <125000>;
hysteresis = <0>;
type = "critical";
};
};
};
aoss1-thermal {
polling-delay-passive = <0>;
polling-delay = <0>;
thermal-sensors = <&tsens1 0>;
trips {
aoss1-crit {
temperature = <125000>;
hysteresis = <0>;
type = "critical";
};
};
};
audio-thermal {
polling-delay-passive = <0>;
polling-delay = <0>;
thermal-sensors = <&tsens1 2>;
trips {
audio-crit {
temperature = <125000>;
hysteresis = <0>;
type = "critical";
};
};
};
camera-thermal {
polling-delay-passive = <0>;
polling-delay = <0>;
thermal-sensors = <&tsens1 5>;
trips {
camera-crit {
temperature = <125000>;
hysteresis = <0>;
type = "critical";
};
};
};
cpu0-thermal {
polling-delay-passive = <0>;
polling-delay = <0>;
thermal-sensors = <&tsens0 1>;
trips {
cpu0_alert0: trip-point0 {
temperature = <95000>;
hysteresis = <2000>;
type = "passive";
};
cpu0-crit {
temperature = <115000>;
hysteresis = <0>;
type = "critical";
};
};
cooling-maps {
map0 {
trip = <&cpu0_alert0>;
cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
};
};
};
cpu1-thermal {
polling-delay-passive = <0>;
polling-delay = <0>;
thermal-sensors = <&tsens0 2>;
trips {
cpu1_alert0: trip-point0 {
temperature = <95000>;
hysteresis = <2000>;
type = "passive";
};
cpu1-crit {
temperature = <115000>;
hysteresis = <0>;
type = "critical";
};
};
cooling-maps {
map0 {
trip = <&cpu1_alert0>;
cooling-device = <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
};
};
};
cpu2-thermal {
polling-delay-passive = <0>;
polling-delay = <0>;
thermal-sensors = <&tsens0 3>;
trips {
cpu2_alert0: trip-point0 {
temperature = <95000>;
hysteresis = <2000>;
type = "passive";
};
cpu2-crit {
temperature = <115000>;
hysteresis = <0>;
type = "critical";
};
};
cooling-maps {
map0 {
trip = <&cpu2_alert0>;
cooling-device = <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
};
};
};
cpu3-thermal {
polling-delay-passive = <0>;
polling-delay = <0>;
thermal-sensors = <&tsens0 4>;
trips {
cpu3_alert0: trip-point0 {
temperature = <95000>;
hysteresis = <2000>;
type = "passive";
};
cpu3-crit {
temperature = <115000>;
hysteresis = <0>;
type = "critical";
};
};
cooling-maps {
map0 {
trip = <&cpu3_alert0>;
cooling-device = <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
};
};
};
cpu4-thermal {
polling-delay-passive = <0>;
polling-delay = <0>;
thermal-sensors = <&tsens0 5>;
trips {
cpu4_alert0: trip-point0 {
temperature = <95000>;
hysteresis = <2000>;
type = "passive";
};
cpu4-crit {
temperature = <115000>;
hysteresis = <0>;
type = "critical";
};
};
cooling-maps {
map0 {
trip = <&cpu4_alert0>;
cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
};
};
};
cpu5-thermal {
polling-delay-passive = <0>;
polling-delay = <0>;
thermal-sensors = <&tsens0 6>;
trips {
cpu5_alert0: trip-point0 {
temperature = <95000>;
hysteresis = <2000>;
type = "passive";
};
cpu5-crit {
temperature = <115000>;
hysteresis = <0>;
type = "critical";
};
};
cooling-maps {
map0 {
trip = <&cpu5_alert0>;
cooling-device = <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
};
};
};
cpu6-left-thermal {
polling-delay-passive = <0>;
polling-delay = <0>;
thermal-sensors = <&tsens0 9>;
trips {
cpu6_left_alert0: trip-point0 {
temperature = <95000>;
hysteresis = <2000>;
type = "passive";
};
cpu6-left-crit {
temperature = <115000>;
hysteresis = <0>;
type = "critical";
};
};
cooling-maps {
map0 {
trip = <&cpu6_left_alert0>;
cooling-device = <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
};
};
};
cpu6-right-thermal {
polling-delay-passive = <0>;
polling-delay = <0>;
thermal-sensors = <&tsens0 10>;
trips {
cpu6_right_alert0: trip-point0 {
temperature = <95000>;
hysteresis = <2000>;
type = "passive";
};
cpu6-right-crit {
temperature = <115000>;
hysteresis = <0>;
type = "critical";
};
};
cooling-maps {
map0 {
trip = <&cpu6_right_alert0>;
cooling-device = <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
};
};
};
cpu7-left-thermal {
polling-delay-passive = <0>;
polling-delay = <0>;
thermal-sensors = <&tsens0 11>;
trips {
cpu7_left_alert0: trip-point0 {
temperature = <95000>;
hysteresis = <2000>;
type = "passive";
};
cpu7-left-crit {
temperature = <115000>;
hysteresis = <0>;
type = "critical";
};
};
cooling-maps {
map0 {
trip = <&cpu7_left_alert0>;
cooling-device = <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
};
};
};
cpu7-right-thermal {
polling-delay-passive = <0>;
polling-delay = <0>;
thermal-sensors = <&tsens0 12>;
trips {
cpu7_right_alert0: trip-point0 {
temperature = <95000>;
hysteresis = <2000>;
type = "passive";
};
cpu7-right-crit {
temperature = <115000>;
hysteresis = <0>;
type = "critical";
};
};
cooling-maps {
map0 {
trip = <&cpu7_right_alert0>;
cooling-device = <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
};
};
};
cpuss0-thermal {
polling-delay-passive = <0>;
polling-delay = <0>;
thermal-sensors = <&tsens0 7>;
trips {
cpuss0-crit {
temperature = <125000>;
hysteresis = <0>;
type = "critical";
};
};
};
cpuss1-thermal {
polling-delay-passive = <0>;
polling-delay = <0>;
thermal-sensors = <&tsens0 8>;
trips {
cpuss1-crit {
temperature = <125000>;
hysteresis = <0>;
type = "critical";
};
};
};
cwlan-thermal {
polling-delay-passive = <0>;
polling-delay = <0>;
thermal-sensors = <&tsens1 1>;
trips {
cwlan-crit {
temperature = <125000>;
hysteresis = <0>;
type = "critical";
};
};
};
ddr-thermal {
polling-delay-passive = <0>;
polling-delay = <0>;
thermal-sensors = <&tsens1 3>;
trips {
ddr-crit {
temperature = <125000>;
hysteresis = <0>;
type = "critical";
};
};
};
gpuss0-thermal {
polling-delay-passive = <0>;
polling-delay = <0>;
thermal-sensors = <&tsens0 13>;
trips {
gpuss0_alert0: trip-point0 {
temperature = <95000>;
hysteresis = <2000>;
type = "passive";
};
gpuss0-crit {
temperature = <115000>;
hysteresis = <0>;
type = "critical";
};
};
cooling-maps {
map0 {
trip = <&gpuss0_alert0>;
cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
};
};
};
gpuss1-thermal {
polling-delay-passive = <0>;
polling-delay = <0>;
thermal-sensors = <&tsens0 14>;
trips {
gpuss1_alert0: trip-point0 {
temperature = <95000>;
hysteresis = <2000>;
type = "passive";
};
gpuss1-crit {
temperature = <115000>;
hysteresis = <0>;
type = "critical";
};
};
cooling-maps {
map0 {
trip = <&gpuss1_alert0>;
cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
};
};
};
modem-core0-thermal {
polling-delay-passive = <0>;
polling-delay = <0>;
thermal-sensors = <&tsens1 6>;
trips {
modem-core0-crit {
temperature = <125000>;
hysteresis = <0>;
type = "critical";
};
};
};
modem-core1-thermal {
polling-delay-passive = <0>;
polling-delay = <0>;
thermal-sensors = <&tsens1 7>;
trips {
modem-core1-crit {
temperature = <125000>;
hysteresis = <0>;
type = "critical";
};
};
};
modem-scl-thermal {
polling-delay-passive = <0>;
polling-delay = <0>;
thermal-sensors = <&tsens1 9>;
trips {
modem-scl-crit {
temperature = <125000>;
hysteresis = <0>;
type = "critical";
};
};
};
modem-vec-thermal {
polling-delay-passive = <0>;
polling-delay = <0>;
thermal-sensors = <&tsens1 8>;
trips {
modem-vec-crit {
temperature = <125000>;
hysteresis = <0>;
type = "critical";
};
};
};
npu-thermal {
polling-delay-passive = <0>;
polling-delay = <0>;
thermal-sensors = <&tsens1 10>;
trips {
npu-crit {
temperature = <125000>;
hysteresis = <0>;
type = "critical";
};
};
};
q6-hvx-thermal {
polling-delay-passive = <0>;
polling-delay = <0>;
thermal-sensors = <&tsens1 4>;
trips {
q6-hvx-crit {
temperature = <125000>;
hysteresis = <0>;
type = "critical";
};
};
};
video-thermal {
polling-delay-passive = <0>;
polling-delay = <0>;
thermal-sensors = <&tsens1 11>;
trips {
video-crit {
temperature = <125000>;
hysteresis = <0>;
type = "critical";
};
};
};
};
timer {
compatible = "arm,armv8-timer";
clock-frequency = <19200000>;

12
arch/arm64/boot/dts/qcom/sm6375.dtsi
View File

@ -1431,13 +1431,15 @@
assigned-clock-rates = <19200000>, <133333333>;
interrupts-extended = <&intc GIC_SPI 302 IRQ_TYPE_LEVEL_HIGH>,
<&mpm 12 IRQ_TYPE_LEVEL_HIGH>,
<&intc GIC_SPI 254 IRQ_TYPE_LEVEL_HIGH>,
<&mpm 94 IRQ_TYPE_EDGE_BOTH>,
<&mpm 93 IRQ_TYPE_EDGE_BOTH>,
<&mpm 94 IRQ_TYPE_EDGE_BOTH>;
interrupt-names = "hs_phy_irq",
"ss_phy_irq",
<&mpm 12 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "pwr_event",
"hs_phy_irq",
"dp_hs_phy_irq",
"dm_hs_phy_irq",
"dp_hs_phy_irq";
"ss_phy_irq";
power-domains = <&gcc USB30_PRIM_GDSC>;

26
arch/arm64/boot/dts/qcom/sm7125-xiaomi-common.dtsi
View File

@ -152,6 +152,9 @@
regulator-min-microvolt = <824000>;
regulator-max-microvolt = <928000>;
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
regulator-allow-set-load;
regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
RPMH_REGULATOR_MODE_HPM>;
};
vreg_l5a_2p7: ldo5 {
@ -188,6 +191,9 @@
regulator-min-microvolt = <1696000>;
regulator-max-microvolt = <1952000>;
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
regulator-allow-set-load;
regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
RPMH_REGULATOR_MODE_HPM>;
};
vreg_l13a_1p8: ldo13 {
@ -230,6 +236,9 @@
regulator-min-microvolt = <2696000>;
regulator-max-microvolt = <3304000>;
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
regulator-allow-set-load;
regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
RPMH_REGULATOR_MODE_HPM>;
};
};
@ -258,6 +267,9 @@
regulator-min-microvolt = <1144000>;
regulator-max-microvolt = <1304000>;
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
regulator-allow-set-load;
regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
RPMH_REGULATOR_MODE_HPM>;
};
vreg_l4c_1p8: ldo4 {
@ -398,6 +410,20 @@
};
};
&ufs_mem_hc {
vcc-supply = <&vreg_l19a_3p0>;
vcc-max-microamp = <600000>;
vccq2-supply = <&vreg_l12a_1p8>;
vccq2-max-microamp = <600000>;
status = "okay";
};
&ufs_mem_phy {
vdda-phy-supply = <&vreg_l4a_0p88>;
vdda-pll-supply = <&vreg_l3c_1p23>;
status = "okay";
};
&usb_1 {
qcom,select-utmi-as-pipe-clk;
status = "okay";

16
arch/arm64/boot/dts/qcom/sm7125-xiaomi-curtana.dts Normal file
View File

@ -0,0 +1,16 @@
// SPDX-License-Identifier: GPL-2.0
/*
* Copyright (c) 2023, Joe Mason <buddyjojo06@outlook.com>
*/
/dts-v1/;
#include "sm7125-xiaomi-common.dtsi"
/ {
model = "Xiaomi Redmi Note 9S";
compatible = "xiaomi,curtana", "qcom,sm7125";
/* required for bootloader to select correct board */
qcom,board-id = <0x20022 1>;
};

61
arch/arm64/boot/dts/qcom/sm7225-fairphone-fp4.dts
View File

@ -68,6 +68,14 @@
};
};
/* Dummy regulator until PM6150L has LCDB VSP/VSN support */
lcdb_dummy: regulator-lcdb-dummy {
compatible = "regulator-fixed";
regulator-name = "lcdb_dummy";
regulator-min-microvolt = <5500000>;
regulator-max-microvolt = <5500000>;
};
reserved-memory {
/*
* The rmtfs memory region in downstream is 'dynamically allocated'
@ -116,7 +124,7 @@
};
&adsp {
firmware-name = "qcom/sm7225/fairphone4/adsp.mdt";
firmware-name = "qcom/sm7225/fairphone4/adsp.mbn";
status = "okay";
};
@ -361,7 +369,7 @@
};
&cdsp {
firmware-name = "qcom/sm7225/fairphone4/cdsp.mdt";
firmware-name = "qcom/sm7225/fairphone4/cdsp.mbn";
status = "okay";
};
@ -373,6 +381,14 @@
status = "okay";
};
&gpu {
status = "okay";
};
&gpu_zap_shader {
firmware-name = "qcom/sm7225/fairphone4/a615_zap.mbn";
};
&i2c0 {
clock-frequency = <400000>;
status = "okay";
@ -400,12 +416,49 @@
&ipa {
qcom,gsi-loader = "self";
memory-region = <&pil_ipa_fw_mem>;
firmware-name = "qcom/sm7225/fairphone4/ipa_fws.mdt";
firmware-name = "qcom/sm7225/fairphone4/ipa_fws.mbn";
status = "okay";
};
&mdss {
status = "okay";
};
&mdss_dsi0 {
vdda-supply = <&vreg_l22a>;
status = "okay";
panel@0 {
compatible = "djn,9a-3r063-1102b";
reg = <0>;
backlight = <&pm6150l_wled>;
reset-gpios = <&pm6150l_gpios 9 GPIO_ACTIVE_LOW>;
vdd1-supply = <&vreg_l1e>;
vsn-supply = <&lcdb_dummy>;
vsp-supply = <&lcdb_dummy>;
port {
panel_in: endpoint {
remote-endpoint = <&mdss_dsi0_out>;
};
};
};
};
&mdss_dsi0_out {
data-lanes = <0 1 2 3>;
remote-endpoint = <&panel_in>;
};
&mdss_dsi0_phy {
vdds-supply = <&vreg_l18a>;
status = "okay";
};
&mpss {
firmware-name = "qcom/sm7225/fairphone4/modem.mdt";
firmware-name = "qcom/sm7225/fairphone4/modem.mbn";
status = "okay";
};

115
arch/arm64/boot/dts/qcom/sm8150.dtsi
View File

@ -967,7 +967,7 @@
#address-cells = <1>;
#size-cells = <1>;
gpu_speed_bin: gpu_speed_bin@133 {
gpu_speed_bin: gpu-speed-bin@133 {
reg = <0x133 0x1>;
bits = <5 3>;
};
@ -1843,8 +1843,22 @@
ranges = <0x01000000 0x0 0x00000000 0x0 0x60200000 0x0 0x100000>,
<0x02000000 0x0 0x60300000 0x0 0x60300000 0x0 0x3d00000>;
interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "msi";
interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "msi0",
"msi1",
"msi2",
"msi3",
"msi4",
"msi5",
"msi6",
"msi7";
#interrupt-cells = <1>;
interrupt-map-mask = <0 0 0 0x7>;
interrupt-map = <0 0 0 1 &intc 0 149 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
@ -1858,14 +1872,16 @@
<&gcc GCC_PCIE_0_MSTR_AXI_CLK>,
<&gcc GCC_PCIE_0_SLV_AXI_CLK>,
<&gcc GCC_PCIE_0_SLV_Q2A_AXI_CLK>,
<&gcc GCC_AGGRE_NOC_PCIE_TBU_CLK>;
<&gcc GCC_AGGRE_NOC_PCIE_TBU_CLK>,
<&rpmhcc RPMH_CXO_CLK>;
clock-names = "pipe",
"aux",
"cfg",
"bus_master",
"bus_slave",
"slave_q2a",
"tbu";
"tbu",
"ref";
iommu-map = <0x0 &apps_smmu 0x1d80 0x1>,
<0x100 &apps_smmu 0x1d81 0x1>;
@ -1879,7 +1895,7 @@
phy-names = "pciephy";
perst-gpios = <&tlmm 35 GPIO_ACTIVE_HIGH>;
enable-gpio = <&tlmm 37 GPIO_ACTIVE_HIGH>;
wake-gpios = <&tlmm 37 GPIO_ACTIVE_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&pcie0_default_state>;
@ -1934,8 +1950,22 @@
ranges = <0x01000000 0x0 0x00000000 0x0 0x40200000 0x0 0x100000>,
<0x02000000 0x0 0x40300000 0x0 0x40300000 0x0 0x1fd00000>;
interrupts = <GIC_SPI 307 IRQ_TYPE_EDGE_RISING>;
interrupt-names = "msi";
interrupts = <GIC_SPI 307 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 313 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 314 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 374 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 375 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "msi0",
"msi1",
"msi2",
"msi3",
"msi4",
"msi5",
"msi6",
"msi7";
#interrupt-cells = <1>;
interrupt-map-mask = <0 0 0 0x7>;
interrupt-map = <0 0 0 1 &intc 0 434 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
@ -1949,14 +1979,16 @@
<&gcc GCC_PCIE_1_MSTR_AXI_CLK>,
<&gcc GCC_PCIE_1_SLV_AXI_CLK>,
<&gcc GCC_PCIE_1_SLV_Q2A_AXI_CLK>,
<&gcc GCC_AGGRE_NOC_PCIE_TBU_CLK>;
<&gcc GCC_AGGRE_NOC_PCIE_TBU_CLK>,
<&rpmhcc RPMH_CXO_CLK>;
clock-names = "pipe",
"aux",
"cfg",
"bus_master",
"bus_slave",
"slave_q2a",
"tbu";
"tbu",
"ref";
assigned-clocks = <&gcc GCC_PCIE_1_AUX_CLK>;
assigned-clock-rates = <19200000>;
@ -2063,10 +2095,12 @@
compatible = "qcom,sm8150-qmp-ufs-phy";
reg = <0 0x01d87000 0 0x1000>;
clocks = <&rpmhcc RPMH_CXO_CLK>,
<&gcc GCC_UFS_PHY_PHY_AUX_CLK>,
<&gcc GCC_UFS_MEM_CLKREF_CLK>;
clock-names = "ref",
"ref_aux";
clocks = <&gcc GCC_UFS_MEM_CLKREF_CLK>,
<&gcc GCC_UFS_PHY_PHY_AUX_CLK>;
"ref_aux",
"qref";
power-domains = <&gcc UFS_PHY_GDSC>;
@ -2198,6 +2232,7 @@
nvmem-cells = <&gpu_speed_bin>;
nvmem-cell-names = "speed_bin";
#cooling-cells = <2>;
status = "disabled";
@ -2428,7 +2463,7 @@
bias-disable;
};
qup_spi6_default: qup-spi6_default-state {
qup_spi6_default: qup-spi6-default-state {
pins = "gpio4", "gpio5", "gpio6", "gpio7";
function = "qup6";
drive-strength = <6>;
@ -2442,7 +2477,7 @@
bias-disable;
};
qup_spi7_default: qup-spi7_default-state {
qup_spi7_default: qup-spi7-default-state {
pins = "gpio98", "gpio99", "gpio100", "gpio101";
function = "qup7";
drive-strength = <6>;
@ -3573,12 +3608,16 @@
<&gcc GCC_USB30_PRIM_MASTER_CLK>;
assigned-clock-rates = <19200000>, <200000000>;
interrupts-extended = <&intc GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>,
<&pdc 6 IRQ_TYPE_LEVEL_HIGH>,
interrupts-extended = <&intc GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>,
<&intc GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>,
<&pdc 9 IRQ_TYPE_EDGE_BOTH>,
<&pdc 8 IRQ_TYPE_EDGE_BOTH>,
<&pdc 9 IRQ_TYPE_EDGE_BOTH>;
interrupt-names = "hs_phy_irq", "ss_phy_irq",
"dm_hs_phy_irq", "dp_hs_phy_irq";
<&pdc 6 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "pwr_event",
"hs_phy_irq",
"dp_hs_phy_irq",
"dm_hs_phy_irq",
"ss_phy_irq";
power-domains = <&gcc USB30_PRIM_GDSC>;
@ -3645,12 +3684,16 @@
<&gcc GCC_USB30_SEC_MASTER_CLK>;
assigned-clock-rates = <19200000>, <200000000>;
interrupts-extended = <&intc GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>,
<&pdc 7 IRQ_TYPE_LEVEL_HIGH>,
interrupts-extended = <&intc GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>,
<&intc GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>,
<&pdc 11 IRQ_TYPE_EDGE_BOTH>,
<&pdc 10 IRQ_TYPE_EDGE_BOTH>,
<&pdc 11 IRQ_TYPE_EDGE_BOTH>;
interrupt-names = "hs_phy_irq", "ss_phy_irq",
"dm_hs_phy_irq", "dp_hs_phy_irq";
<&pdc 7 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "pwr_event",
"hs_phy_irq",
"dp_hs_phy_irq",
"dm_hs_phy_irq",
"ss_phy_irq";
power-domains = <&gcc USB30_SEC_GDSC>;
@ -5067,7 +5110,7 @@
hysteresis = <2000>;
type = "hot";
};
cluster0_crit: cluster0_crit {
cluster0_crit: cluster0-crit {
temperature = <110000>;
hysteresis = <2000>;
type = "critical";
@ -5087,7 +5130,7 @@
hysteresis = <2000>;
type = "hot";
};
cluster1_crit: cluster1_crit {
cluster1_crit: cluster1-crit {
temperature = <110000>;
hysteresis = <2000>;
type = "critical";
@ -5101,8 +5144,15 @@
thermal-sensors = <&tsens0 15>;
cooling-maps {
map0 {
trip = <&gpu_top_alert0>;
cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
};
};
trips {
gpu1_alert0: trip-point0 {
gpu_top_alert0: trip-point0 {
temperature = <90000>;
hysteresis = <2000>;
type = "hot";
@ -5281,8 +5331,15 @@
thermal-sensors = <&tsens1 11>;
cooling-maps {
map0 {
trip = <&gpu_bottom_alert0>;
cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
};
};
trips {
gpu2_alert0: trip-point0 {
gpu_bottom_alert0: trip-point0 {
temperature = <90000>;
hysteresis = <2000>;
type = "hot";

107
arch/arm64/boot/dts/qcom/sm8250.dtsi
View File

@ -975,7 +975,7 @@
#address-cells = <1>;
#size-cells = <1>;
gpu_speed_bin: gpu_speed_bin@19b {
gpu_speed_bin: gpu-speed-bin@19b {
reg = <0x19b 0x1>;
bits = <5 3>;
};
@ -2152,8 +2152,14 @@
<GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "msi0", "msi1", "msi2", "msi3",
"msi4", "msi5", "msi6", "msi7";
interrupt-names = "msi0",
"msi1",
"msi2",
"msi3",
"msi4",
"msi5",
"msi6",
"msi7";
#interrupt-cells = <1>;
interrupt-map-mask = <0 0 0 0x7>;
interrupt-map = <0 0 0 1 &intc 0 149 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
@ -2248,8 +2254,22 @@
ranges = <0x01000000 0x0 0x00000000 0x0 0x40200000 0x0 0x100000>,
<0x02000000 0x0 0x40300000 0x0 0x40300000 0x0 0x1fd00000>;
interrupts = <GIC_SPI 307 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "msi";
interrupts = <GIC_SPI 307 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 313 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 314 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 374 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 375 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "msi0",
"msi1",
"msi2",
"msi3",
"msi4",
"msi5",
"msi6",
"msi7";
#interrupt-cells = <1>;
interrupt-map-mask = <0 0 0 0x7>;
interrupt-map = <0 0 0 1 &intc 0 434 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
@ -2349,8 +2369,22 @@
ranges = <0x01000000 0x0 0x00000000 0x0 0x64200000 0x0 0x100000>,
<0x02000000 0x0 0x64300000 0x0 0x64300000 0x0 0x3d00000>;
interrupts = <GIC_SPI 243 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "msi";
interrupts = <GIC_SPI 243 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 261 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 262 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 263 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 264 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 278 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 288 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 289 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "msi0",
"msi1",
"msi2",
"msi3",
"msi4",
"msi5",
"msi6",
"msi7";
#interrupt-cells = <1>;
interrupt-map-mask = <0 0 0 0x7>;
interrupt-map = <0 0 0 1 &intc 0 290 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
@ -2506,10 +2540,12 @@
compatible = "qcom,sm8250-qmp-ufs-phy";
reg = <0 0x01d87000 0 0x1000>;
clock-names = "ref",
"ref_aux";
clocks = <&rpmhcc RPMH_CXO_CLK>,
<&gcc GCC_UFS_PHY_PHY_AUX_CLK>;
<&gcc GCC_UFS_PHY_PHY_AUX_CLK>,
<&gcc GCC_UFS_1X_CLKREF_EN>;
clock-names = "ref",
"ref_aux",
"qref";
resets = <&ufs_mem_hc 0>;
reset-names = "ufsphy";
@ -2888,6 +2924,7 @@
nvmem-cells = <&gpu_speed_bin>;
nvmem-cell-names = "speed_bin";
#cooling-cells = <2>;
status = "disabled";
@ -4128,14 +4165,16 @@
<&gcc GCC_USB30_PRIM_MASTER_CLK>;
assigned-clock-rates = <19200000>, <200000000>;
interrupts-extended = <&intc GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>,
<&pdc 17 IRQ_TYPE_LEVEL_HIGH>,
interrupts-extended = <&intc GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>,
<&intc GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>,
<&pdc 14 IRQ_TYPE_EDGE_BOTH>,
<&pdc 15 IRQ_TYPE_EDGE_BOTH>,
<&pdc 14 IRQ_TYPE_EDGE_BOTH>;
interrupt-names = "hs_phy_irq",
"ss_phy_irq",
<&pdc 17 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "pwr_event",
"hs_phy_irq",
"dp_hs_phy_irq",
"dm_hs_phy_irq",
"dp_hs_phy_irq";
"ss_phy_irq";
power-domains = <&gcc USB30_PRIM_GDSC>;
wakeup-source;
@ -4197,14 +4236,16 @@
<&gcc GCC_USB30_SEC_MASTER_CLK>;
assigned-clock-rates = <19200000>, <200000000>;
interrupts-extended = <&intc GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>,
<&pdc 16 IRQ_TYPE_LEVEL_HIGH>,
interrupts-extended = <&intc GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>,
<&intc GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>,
<&pdc 12 IRQ_TYPE_EDGE_BOTH>,
<&pdc 13 IRQ_TYPE_EDGE_BOTH>,
<&pdc 12 IRQ_TYPE_EDGE_BOTH>;
interrupt-names = "hs_phy_irq",
"ss_phy_irq",
<&pdc 16 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "pwr_event",
"hs_phy_irq",
"dp_hs_phy_irq",
"dm_hs_phy_irq",
"dp_hs_phy_irq";
"ss_phy_irq";
power-domains = <&gcc USB30_SEC_GDSC>;
wakeup-source;
@ -6757,7 +6798,7 @@
hysteresis = <2000>;
type = "hot";
};
cluster0_crit: cluster0_crit {
cluster0_crit: cluster0-crit {
temperature = <110000>;
hysteresis = <2000>;
type = "critical";
@ -6777,7 +6818,7 @@
hysteresis = <2000>;
type = "hot";
};
cluster1_crit: cluster1_crit {
cluster1_crit: cluster1-crit {
temperature = <110000>;
hysteresis = <2000>;
type = "critical";
@ -6791,8 +6832,15 @@
thermal-sensors = <&tsens0 15>;
cooling-maps {
map0 {
trip = <&gpu_top_alert0>;
cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
};
};
trips {
gpu1_alert0: trip-point0 {
gpu_top_alert0: trip-point0 {
temperature = <90000>;
hysteresis = <2000>;
type = "hot";
@ -6926,8 +6974,15 @@
thermal-sensors = <&tsens1 8>;
cooling-maps {
map0 {
trip = <&gpu_bottom_alert0>;
cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
};
};
trips {
gpu2_alert0: trip-point0 {
gpu_bottom_alert0: trip-point0 {
temperature = <90000>;
hysteresis = <2000>;
type = "hot";

87
arch/arm64/boot/dts/qcom/sm8350.dtsi
View File

@ -1526,8 +1526,14 @@
<GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "msi0", "msi1", "msi2", "msi3",
"msi4", "msi5", "msi6", "msi7";
interrupt-names = "msi0",
"msi1",
"msi2",
"msi3",
"msi4",
"msi5",
"msi6",
"msi7";
#interrupt-cells = <1>;
interrupt-map-mask = <0 0 0 0x7>;
interrupt-map = <0 0 0 1 &intc 0 149 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
@ -1611,8 +1617,22 @@
ranges = <0x01000000 0x0 0x00000000 0x0 0x40200000 0x0 0x100000>,
<0x02000000 0x0 0x40300000 0x0 0x40300000 0x0 0x1fd00000>;
interrupts = <GIC_SPI 307 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "msi";
interrupts = <GIC_SPI 307 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 313 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 314 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 374 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 375 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "msi0",
"msi1",
"msi2",
"msi3",
"msi4",
"msi5",
"msi6",
"msi7";
#interrupt-cells = <1>;
interrupt-map-mask = <0 0 0 0x7>;
interrupt-map = <0 0 0 1 &intc 0 434 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
@ -1726,10 +1746,12 @@
compatible = "qcom,sm8350-qmp-ufs-phy";
reg = <0 0x01d87000 0 0x1000>;
clock-names = "ref",
"ref_aux";
clocks = <&rpmhcc RPMH_CXO_CLK>,
<&gcc GCC_UFS_PHY_PHY_AUX_CLK>;
<&gcc GCC_UFS_PHY_PHY_AUX_CLK>,
<&gcc GCC_UFS_1_CLKREF_EN>;
clock-names = "ref",
"ref_aux",
"qref";
resets = <&ufs_mem_hc 0>;
reset-names = "ufsphy";
@ -1847,6 +1869,7 @@
operating-points-v2 = <&gpu_opp_table>;
qcom,gmu = <&gmu>;
#cooling-cells = <2>;
status = "disabled";
@ -2312,14 +2335,16 @@
<&gcc GCC_USB30_PRIM_MASTER_CLK>;
assigned-clock-rates = <19200000>, <200000000>;
interrupts-extended = <&intc GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>,
<&pdc 17 IRQ_TYPE_LEVEL_HIGH>,
interrupts-extended = <&intc GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>,
<&intc GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>,
<&pdc 14 IRQ_TYPE_EDGE_BOTH>,
<&pdc 15 IRQ_TYPE_EDGE_BOTH>,
<&pdc 14 IRQ_TYPE_EDGE_BOTH>;
interrupt-names = "hs_phy_irq",
"ss_phy_irq",
<&pdc 17 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "pwr_event",
"hs_phy_irq",
"dp_hs_phy_irq",
"dm_hs_phy_irq",
"dp_hs_phy_irq";
"ss_phy_irq";
power-domains = <&gcc USB30_PRIM_GDSC>;
@ -2385,14 +2410,16 @@
<&gcc GCC_USB30_SEC_MASTER_CLK>;
assigned-clock-rates = <19200000>, <200000000>;
interrupts-extended = <&intc GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>,
<&pdc 16 IRQ_TYPE_LEVEL_HIGH>,
interrupts-extended = <&intc GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>,
<&intc GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>,
<&pdc 12 IRQ_TYPE_EDGE_BOTH>,
<&pdc 13 IRQ_TYPE_EDGE_BOTH>,
<&pdc 12 IRQ_TYPE_EDGE_BOTH>;
interrupt-names = "hs_phy_irq",
"ss_phy_irq",
<&pdc 16 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "pwr_event",
"hs_phy_irq",
"dp_hs_phy_irq",
"dm_hs_phy_irq",
"dp_hs_phy_irq";
"ss_phy_irq";
power-domains = <&gcc USB30_SEC_GDSC>;
@ -4165,7 +4192,7 @@
hysteresis = <2000>;
type = "hot";
};
cluster0_crit: cluster0_crit {
cluster0_crit: cluster0-crit {
temperature = <110000>;
hysteresis = <2000>;
type = "critical";
@ -4185,7 +4212,7 @@
hysteresis = <2000>;
type = "hot";
};
cluster1_crit: cluster1_crit {
cluster1_crit: cluster1-crit {
temperature = <110000>;
hysteresis = <2000>;
type = "critical";
@ -4214,8 +4241,15 @@
thermal-sensors = <&tsens1 1>;
cooling-maps {
map0 {
trip = <&gpu_top_alert0>;
cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
};
};
trips {
gpu1_alert0: trip-point0 {
gpu_top_alert0: trip-point0 {
temperature = <90000>;
hysteresis = <1000>;
type = "hot";
@ -4229,8 +4263,15 @@
thermal-sensors = <&tsens1 2>;
cooling-maps {
map0 {
trip = <&gpu_bottom_alert0>;
cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
};
};
trips {
gpu2_alert0: trip-point0 {
gpu_bottom_alert0: trip-point0 {
temperature = <90000>;
hysteresis = <1000>;
type = "hot";

6
arch/arm64/boot/dts/qcom/sm8450-hdk.dts
View File

@ -938,8 +938,8 @@
"TX DMIC3", "MIC BIAS1",
"TX SWR_INPUT0", "ADC1_OUTPUT",
"TX SWR_INPUT1", "ADC2_OUTPUT",
"TX SWR_INPUT2", "ADC3_OUTPUT",
"TX SWR_INPUT3", "ADC4_OUTPUT";
"TX SWR_INPUT0", "ADC3_OUTPUT",
"TX SWR_INPUT1", "ADC4_OUTPUT";
wcd-playback-dai-link {
link-name = "WCD Playback";
@ -1147,7 +1147,7 @@
};
&vamacro {
pinctrl-0 = <&dmic01_default>, <&dmic02_default>;
pinctrl-0 = <&dmic01_default>, <&dmic23_default>;
pinctrl-names = "default";
vdd-micb-supply = <&vreg_s10b_1p8>;
qcom,dmic-sample-rate = <600000>;

81
arch/arm64/boot/dts/qcom/sm8450.dtsi
View File

@ -1028,6 +1028,12 @@
pinctrl-names = "default";
pinctrl-0 = <&qup_uart20_default>;
interrupts = <GIC_SPI 587 IRQ_TYPE_LEVEL_HIGH>;
interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS
&clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>,
<&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
&config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>;
interconnect-names = "qup-core",
"qup-config";
status = "disabled";
};
@ -1420,6 +1426,12 @@
pinctrl-names = "default";
pinctrl-0 = <&qup_uart7_tx>, <&qup_uart7_rx>;
interrupts = <GIC_SPI 608 IRQ_TYPE_LEVEL_HIGH>;
interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS
&clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>,
<&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
&config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>;
interconnect-names = "qup-core",
"qup-config";
status = "disabled";
};
};
@ -1772,8 +1784,22 @@
msi-map = <0x0 &gic_its 0x5981 0x1>,
<0x100 &gic_its 0x5980 0x1>;
msi-map-mask = <0xff00>;
interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "msi";
interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "msi0",
"msi1",
"msi2",
"msi3",
"msi4",
"msi5",
"msi6",
"msi7";
#interrupt-cells = <1>;
interrupt-map-mask = <0 0 0 0x7>;
interrupt-map = <0 0 0 1 &intc 0 0 0 149 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
@ -1881,8 +1907,22 @@
msi-map = <0x0 &gic_its 0x5a01 0x1>,
<0x100 &gic_its 0x5a00 0x1>;
msi-map-mask = <0xff00>;
interrupts = <GIC_SPI 307 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "msi";
interrupts = <GIC_SPI 307 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 313 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 314 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 374 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 375 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "msi0",
"msi1",
"msi2",
"msi3",
"msi4",
"msi5",
"msi6",
"msi7";
#interrupt-cells = <1>;
interrupt-map-mask = <0 0 0 0x7>;
interrupt-map = <0 0 0 1 &intc 0 0 0 434 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
@ -2038,6 +2078,7 @@
operating-points-v2 = <&gpu_opp_table>;
qcom,gmu = <&gmu>;
#cooling-cells = <2>;
status = "disabled";
@ -3934,7 +3975,7 @@
};
};
dmic02_default: dmic02-default-state {
dmic23_default: dmic23-default-state {
clk-pins {
pins = "gpio8";
function = "dmic2_clk";
@ -4485,13 +4526,15 @@
assigned-clock-rates = <19200000>, <200000000>;
interrupts-extended = <&intc GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>,
<&pdc 17 IRQ_TYPE_LEVEL_HIGH>,
<&intc GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>,
<&pdc 14 IRQ_TYPE_EDGE_BOTH>,
<&pdc 15 IRQ_TYPE_EDGE_BOTH>,
<&pdc 14 IRQ_TYPE_EDGE_BOTH>;
interrupt-names = "hs_phy_irq",
"ss_phy_irq",
<&pdc 17 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "pwr_event",
"hs_phy_irq",
"dp_hs_phy_irq",
"dm_hs_phy_irq",
"dp_hs_phy_irq";
"ss_phy_irq";
power-domains = <&gcc USB30_PRIM_GDSC>;
@ -4890,6 +4933,13 @@
polling-delay = <0>;
thermal-sensors = <&tsens0 14>;
cooling-maps {
map0 {
trip = <&gpu_top_alert0>;
cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
};
};
trips {
thermal-engine-config {
temperature = <125000>;
@ -4909,7 +4959,7 @@
type = "passive";
};
gpu0_tj_cfg: tj-cfg {
gpu_top_alert0: trip-point0 {
temperature = <95000>;
hysteresis = <5000>;
type = "passive";
@ -4922,6 +4972,13 @@
polling-delay = <0>;
thermal-sensors = <&tsens0 15>;
cooling-maps {
map0 {
trip = <&gpu_bottom_alert0>;
cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
};
};
trips {
thermal-engine-config {
temperature = <125000>;
@ -4941,7 +4998,7 @@
type = "passive";
};
gpu1_tj_cfg: tj-cfg {
gpu_bottom_alert0: trip-point0 {
temperature = <95000>;
hysteresis = <5000>;
type = "passive";

1306
arch/arm64/boot/dts/qcom/sm8550-hdk.dts Normal file
View File

File diff suppressed because it is too large Load Diff

11
arch/arm64/boot/dts/qcom/sm8550-mtp.dts
View File

@ -106,14 +106,21 @@
"SpkrRight IN", "WSA_SPK2 OUT",
"IN1_HPHL", "HPHL_OUT",
"IN2_HPHR", "HPHR_OUT",
"AMIC1", "MIC BIAS1",
"AMIC2", "MIC BIAS2",
"AMIC3", "MIC BIAS3",
"AMIC4", "MIC BIAS3",
"AMIC5", "MIC BIAS4",
"VA DMIC0", "MIC BIAS1",
"VA DMIC1", "MIC BIAS1",
"VA DMIC2", "MIC BIAS3",
"TX DMIC0", "MIC BIAS1",
"TX DMIC1", "MIC BIAS2",
"TX DMIC2", "MIC BIAS3",
"TX SWR_ADC1", "ADC2_OUTPUT";
"TX SWR_INPUT0", "ADC1_OUTPUT",
"TX SWR_INPUT1", "ADC2_OUTPUT",
"TX SWR_INPUT0", "ADC3_OUTPUT",
"TX SWR_INPUT1", "ADC4_OUTPUT";
wcd-playback-dai-link {
link-name = "WCD Playback";
@ -874,7 +881,7 @@
wcd_tx: codec@0,3 {
compatible = "sdw20217010d00";
reg = <0 3>;
qcom,tx-port-mapping = <1 1 2 3>;
qcom,tx-port-mapping = <2 2 3 4>;
};
};

53
arch/arm64/boot/dts/qcom/sm8550-qrd.dts
View File

@ -124,14 +124,21 @@
"SpkrRight IN", "WSA_SPK2 OUT",
"IN1_HPHL", "HPHL_OUT",
"IN2_HPHR", "HPHR_OUT",
"AMIC1", "MIC BIAS1",
"AMIC2", "MIC BIAS2",
"AMIC3", "MIC BIAS3",
"AMIC4", "MIC BIAS3",
"AMIC5", "MIC BIAS4",
"VA DMIC0", "MIC BIAS1",
"VA DMIC1", "MIC BIAS1",
"VA DMIC2", "MIC BIAS3",
"TX DMIC0", "MIC BIAS1",
"TX DMIC1", "MIC BIAS2",
"TX DMIC2", "MIC BIAS3",
"TX SWR_ADC1", "ADC2_OUTPUT";
"TX SWR_INPUT0", "ADC1_OUTPUT",
"TX SWR_INPUT1", "ADC2_OUTPUT",
"TX SWR_INPUT0", "ADC3_OUTPUT",
"TX SWR_INPUT1", "ADC4_OUTPUT";
wcd-playback-dai-link {
link-name = "WCD Playback";
@ -724,6 +731,10 @@
<&usb_dp_qmpphy QMP_USB43DP_USB3_PIPE_CLK>;
};
&gpi_dma1 {
status = "okay";
};
&gpu {
status = "okay";
@ -960,6 +971,30 @@
};
};
&spi4 {
status = "okay";
touchscreen@0 {
compatible = "goodix,gt9916";
reg = <0>;
interrupt-parent = <&tlmm>;
interrupts = <25 IRQ_TYPE_LEVEL_LOW>;
reset-gpios = <&tlmm 24 GPIO_ACTIVE_LOW>;
avdd-supply = <&vreg_l14b_3p2>;
spi-max-frequency = <1000000>;
touchscreen-size-x = <1080>;
touchscreen-size-y = <2400>;
pinctrl-names = "default";
pinctrl-0 = <&ts_irq>, <&ts_reset>;
};
};
&swr1 {
status = "okay";
@ -978,7 +1013,7 @@
wcd_tx: codec@0,3 {
compatible = "sdw20217010d00";
reg = <0 3>;
qcom,tx-port-mapping = <1 1 2 3>;
qcom,tx-port-mapping = <2 2 3 4>;
};
};
@ -1028,6 +1063,20 @@
bias-pull-down;
};
ts_irq: ts-irq-state {
pins = "gpio25";
function = "gpio";
drive-strength = <8>;
bias-pull-up;
};
ts_reset: ts-reset-state {
pins = "gpio24";
function = "gpio";
drive-strength = <8>;
bias-pull-up;
};
wcd_default: wcd-reset-n-active-state {
pins = "gpio108";
function = "gpio";

187
arch/arm64/boot/dts/qcom/sm8550.dtsi
View File

@ -1713,9 +1713,22 @@
linux,pci-domain = <0>;
num-lanes = <2>;
interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "msi";
interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "msi0",
"msi1",
"msi2",
"msi3",
"msi4",
"msi5",
"msi6",
"msi7";
#interrupt-cells = <1>;
interrupt-map-mask = <0 0 0 0x7>;
interrupt-map = <0 0 0 1 &intc 0 0 0 149 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
@ -1742,6 +1755,9 @@
<&gem_noc MASTER_APPSS_PROC 0 &cnoc_main SLAVE_PCIE_0 0>;
interconnect-names = "pcie-mem", "cpu-pcie";
/* Entries are reversed due to the unusual ITS DeviceID encoding */
msi-map = <0x0 &gic_its 0x1401 0x1>,
<0x100 &gic_its 0x1400 0x1>;
iommu-map = <0x0 &apps_smmu 0x1400 0x1>,
<0x100 &apps_smmu 0x1401 0x1>;
@ -1804,9 +1820,22 @@
linux,pci-domain = <1>;
num-lanes = <2>;
interrupts = <GIC_SPI 307 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "msi";
interrupts = <GIC_SPI 307 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 313 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 314 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 374 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 375 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "msi0",
"msi1",
"msi2",
"msi3",
"msi4",
"msi5",
"msi6",
"msi7";
#interrupt-cells = <1>;
interrupt-map-mask = <0 0 0 0x7>;
interrupt-map = <0 0 0 1 &intc 0 0 0 434 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
@ -1838,6 +1867,9 @@
<&gem_noc MASTER_APPSS_PROC 0 &cnoc_main SLAVE_PCIE_1 0>;
interconnect-names = "pcie-mem", "cpu-pcie";
/* Entries are reversed due to the unusual ITS DeviceID encoding */
msi-map = <0x0 &gic_its 0x1481 0x1>,
<0x100 &gic_its 0x1480 0x1>;
iommu-map = <0x0 &apps_smmu 0x1480 0x1>,
<0x100 &apps_smmu 0x1481 0x1>;
@ -1907,9 +1939,12 @@
ufs_mem_phy: phy@1d80000 {
compatible = "qcom,sm8550-qmp-ufs-phy";
reg = <0x0 0x01d80000 0x0 0x2000>;
clocks = <&tcsr TCSR_UFS_CLKREF_EN>,
<&gcc GCC_UFS_PHY_PHY_AUX_CLK>;
clock-names = "ref", "ref_aux";
clocks = <&rpmhcc RPMH_CXO_CLK>,
<&gcc GCC_UFS_PHY_PHY_AUX_CLK>,
<&tcsr TCSR_UFS_CLKREF_EN>;
clock-names = "ref",
"ref_aux",
"qref";
power-domains = <&gcc UFS_MEM_PHY_GDSC>;
@ -1940,6 +1975,7 @@
iommus = <&apps_smmu 0x60 0x0>;
dma-coherent;
operating-points-v2 = <&ufs_opp_table>;
interconnects = <&aggre1_noc MASTER_UFS_MEM 0 &mc_virt SLAVE_EBI1 0>,
<&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_UFS_MEM_CFG 0>;
@ -1960,18 +1996,49 @@
<&gcc GCC_UFS_PHY_TX_SYMBOL_0_CLK>,
<&gcc GCC_UFS_PHY_RX_SYMBOL_0_CLK>,
<&gcc GCC_UFS_PHY_RX_SYMBOL_1_CLK>;
freq-table-hz =
<75000000 300000000>,
<0 0>,
<0 0>,
<75000000 300000000>,
<100000000 403000000>,
<0 0>,
<0 0>,
<0 0>;
qcom,ice = <&ice>;
status = "disabled";
ufs_opp_table: opp-table {
compatible = "operating-points-v2";
opp-75000000 {
opp-hz = /bits/ 64 <75000000>,
/bits/ 64 <0>,
/bits/ 64 <0>,
/bits/ 64 <75000000>,
/bits/ 64 <0>,
/bits/ 64 <0>,
/bits/ 64 <0>,
/bits/ 64 <0>;
required-opps = <&rpmhpd_opp_low_svs>;
};
opp-150000000 {
opp-hz = /bits/ 64 <150000000>,
/bits/ 64 <0>,
/bits/ 64 <0>,
/bits/ 64 <150000000>,
/bits/ 64 <0>,
/bits/ 64 <0>,
/bits/ 64 <0>,
/bits/ 64 <0>;
required-opps = <&rpmhpd_opp_svs>;
};
opp-300000000 {
opp-hz = /bits/ 64 <300000000>,
/bits/ 64 <0>,
/bits/ 64 <0>,
/bits/ 64 <300000000>,
/bits/ 64 <0>,
/bits/ 64 <0>,
/bits/ 64 <0>,
/bits/ 64 <0>;
required-opps = <&rpmhpd_opp_nom>;
};
};
};
ice: crypto@1d88000 {
@ -2012,6 +2079,7 @@
operating-points-v2 = <&gpu_opp_table>;
qcom,gmu = <&gmu>;
#cooling-cells = <2>;
status = "disabled";
@ -2507,7 +2575,7 @@
};
};
dmic02_default: dmic02-default-state {
dmic23_default: dmic23-default-state {
clk-pins {
pins = "gpio8";
function = "dmic2_clk";
@ -3133,13 +3201,15 @@
assigned-clock-rates = <19200000>, <200000000>;
interrupts-extended = <&intc GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>,
<&pdc 17 IRQ_TYPE_LEVEL_HIGH>,
<&intc GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>,
<&pdc 14 IRQ_TYPE_EDGE_BOTH>,
<&pdc 15 IRQ_TYPE_EDGE_BOTH>,
<&pdc 14 IRQ_TYPE_EDGE_BOTH>;
interrupt-names = "hs_phy_irq",
"ss_phy_irq",
<&pdc 17 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "pwr_event",
"hs_phy_irq",
"dp_hs_phy_irq",
"dm_hs_phy_irq",
"dp_hs_phy_irq";
"ss_phy_irq";
power-domains = <&gcc USB30_PRIM_GDSC>;
required-opps = <&rpmhpd_opp_nom>;
@ -4254,6 +4324,7 @@
reg = <3>;
iommus = <&apps_smmu 0x1003 0x80>,
<&apps_smmu 0x1063 0x0>;
dma-coherent;
};
compute-cb@4 {
@ -4261,6 +4332,7 @@
reg = <4>;
iommus = <&apps_smmu 0x1004 0x80>,
<&apps_smmu 0x1064 0x0>;
dma-coherent;
};
compute-cb@5 {
@ -4268,6 +4340,7 @@
reg = <5>;
iommus = <&apps_smmu 0x1005 0x80>,
<&apps_smmu 0x1065 0x0>;
dma-coherent;
};
compute-cb@6 {
@ -4275,6 +4348,7 @@
reg = <6>;
iommus = <&apps_smmu 0x1006 0x80>,
<&apps_smmu 0x1066 0x0>;
dma-coherent;
};
compute-cb@7 {
@ -4282,6 +4356,7 @@
reg = <7>;
iommus = <&apps_smmu 0x1007 0x80>,
<&apps_smmu 0x1067 0x0>;
dma-coherent;
};
};
@ -4388,6 +4463,7 @@
iommus = <&apps_smmu 0x1961 0x0>,
<&apps_smmu 0x0c01 0x20>,
<&apps_smmu 0x19c1 0x10>;
dma-coherent;
};
compute-cb@2 {
@ -4396,6 +4472,7 @@
iommus = <&apps_smmu 0x1962 0x0>,
<&apps_smmu 0x0c02 0x20>,
<&apps_smmu 0x19c2 0x10>;
dma-coherent;
};
compute-cb@3 {
@ -4404,6 +4481,7 @@
iommus = <&apps_smmu 0x1963 0x0>,
<&apps_smmu 0x0c03 0x20>,
<&apps_smmu 0x19c3 0x10>;
dma-coherent;
};
compute-cb@4 {
@ -4412,6 +4490,7 @@
iommus = <&apps_smmu 0x1964 0x0>,
<&apps_smmu 0x0c04 0x20>,
<&apps_smmu 0x19c4 0x10>;
dma-coherent;
};
compute-cb@5 {
@ -4420,6 +4499,7 @@
iommus = <&apps_smmu 0x1965 0x0>,
<&apps_smmu 0x0c05 0x20>,
<&apps_smmu 0x19c5 0x10>;
dma-coherent;
};
compute-cb@6 {
@ -4428,6 +4508,7 @@
iommus = <&apps_smmu 0x1966 0x0>,
<&apps_smmu 0x0c06 0x20>,
<&apps_smmu 0x19c6 0x10>;
dma-coherent;
};
compute-cb@7 {
@ -4436,6 +4517,7 @@
iommus = <&apps_smmu 0x1967 0x0>,
<&apps_smmu 0x0c07 0x20>,
<&apps_smmu 0x19c7 0x10>;
dma-coherent;
};
compute-cb@8 {
@ -4444,6 +4526,7 @@
iommus = <&apps_smmu 0x1968 0x0>,
<&apps_smmu 0x0c08 0x20>,
<&apps_smmu 0x19c8 0x10>;
dma-coherent;
};
/* note: secure cb9 in downstream */
@ -5304,6 +5387,13 @@
polling-delay = <0>;
thermal-sensors = <&tsens2 1>;
cooling-maps {
map0 {
trip = <&gpu0_junction_config>;
cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
};
};
trips {
thermal-engine-config {
temperature = <125000>;
@ -5336,6 +5426,13 @@
polling-delay = <0>;
thermal-sensors = <&tsens2 2>;
cooling-maps {
map0 {
trip = <&gpu1_junction_config>;
cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
};
};
trips {
thermal-engine-config {
temperature = <125000>;
@ -5368,6 +5465,13 @@
polling-delay = <0>;
thermal-sensors = <&tsens2 3>;
cooling-maps {
map0 {
trip = <&gpu2_junction_config>;
cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
};
};
trips {
thermal-engine-config {
temperature = <125000>;
@ -5400,6 +5504,13 @@
polling-delay = <0>;
thermal-sensors = <&tsens2 4>;
cooling-maps {
map0 {
trip = <&gpu3_junction_config>;
cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
};
};
trips {
thermal-engine-config {
temperature = <125000>;
@ -5432,6 +5543,13 @@
polling-delay = <0>;
thermal-sensors = <&tsens2 5>;
cooling-maps {
map0 {
trip = <&gpu4_junction_config>;
cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
};
};
trips {
thermal-engine-config {
temperature = <125000>;
@ -5464,6 +5582,13 @@
polling-delay = <0>;
thermal-sensors = <&tsens2 6>;
cooling-maps {
map0 {
trip = <&gpu5_junction_config>;
cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
};
};
trips {
thermal-engine-config {
temperature = <125000>;
@ -5496,6 +5621,13 @@
polling-delay = <0>;
thermal-sensors = <&tsens2 7>;
cooling-maps {
map0 {
trip = <&gpu6_junction_config>;
cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
};
};
trips {
thermal-engine-config {
temperature = <125000>;
@ -5528,6 +5660,13 @@
polling-delay = <0>;
thermal-sensors = <&tsens2 8>;
cooling-maps {
map0 {
trip = <&gpu7_junction_config>;
cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
};
};
trips {
thermal-engine-config {
temperature = <125000>;

155
arch/arm64/boot/dts/qcom/sm8650-mtp.dts
View File

@ -66,6 +66,29 @@
};
};
sound {
compatible = "qcom,sm8650-sndcard", "qcom,sm8450-sndcard";
model = "SM8650-MTP";
audio-routing = "SpkrLeft IN", "WSA_SPK1 OUT",
"SpkrRight IN", "WSA_SPK2 OUT";
wsa-dai-link {
link-name = "WSA Playback";
cpu {
sound-dai = <&q6apmbedai WSA_CODEC_DMA_RX_0>;
};
codec {
sound-dai = <&left_spkr>, <&right_spkr>, <&swr0 0>, <&lpass_wsamacro 0>;
};
platform {
sound-dai = <&q6apm>;
};
};
};
vph_pwr: vph-pwr-regulator {
compatible = "regulator-fixed";
@ -428,6 +451,138 @@
RPMH_REGULATOR_MODE_HPM>;
};
};
regulators-6 {
compatible = "qcom,pm8010-rpmh-regulators";
qcom,pmic-id = "m";
vdd-l1-l2-supply = <&vreg_s1c_1p2>;
vdd-l3-l4-supply = <&vreg_bob2>;
vdd-l5-supply = <&vreg_s6c_1p8>;
vdd-l6-supply = <&vreg_bob1>;
vdd-l7-supply = <&vreg_bob1>;
vreg_l1m_1p1: ldo1 {
regulator-name = "vreg_l1m_1p1";
regulator-min-microvolt = <1104000>;
regulator-max-microvolt = <1104000>;
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
regulator-allow-set-load;
regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
RPMH_REGULATOR_MODE_HPM>;
};
vreg_l2m_1p056: ldo2 {
regulator-name = "vreg_l2m_1p056";
regulator-min-microvolt = <1056000>;
regulator-max-microvolt = <1056000>;
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
regulator-allow-set-load;
regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
RPMH_REGULATOR_MODE_HPM>;
};
vreg_l3m_2p8: ldo3 {
regulator-name = "vreg_l3m_2p8";
regulator-min-microvolt = <2800000>;
regulator-max-microvolt = <2800000>;
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
};
vreg_l4m_2p8: ldo4 {
regulator-name = "vreg_l4m_2p8";
regulator-min-microvolt = <2800000>;
regulator-max-microvolt = <2800000>;
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
};
vreg_l5m_1p8: ldo5 {
regulator-name = "vreg_l5m_1p8";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
};
vreg_l6m_2p8: ldo6 {
regulator-name = "vreg_l6m_2p8";
regulator-min-microvolt = <2800000>;
regulator-max-microvolt = <2800000>;
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
};
vreg_l7m_2p96: ldo7 {
regulator-name = "vreg_l7m_2p96";
regulator-min-microvolt = <2960000>;
regulator-max-microvolt = <2960000>;
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
};
};
regulators-7 {
compatible = "qcom,pm8010-rpmh-regulators";
qcom,pmic-id = "n";
vdd-l1-l2-supply = <&vreg_s1c_1p2>;
vdd-l3-l4-supply = <&vreg_s6c_1p8>;
vdd-l5-supply = <&vreg_bob2>;
vdd-l6-supply = <&vreg_bob2>;
vdd-l7-supply = <&vreg_bob1>;
vreg_l1n_1p1: ldo1 {
regulator-name = "vreg_l1n_1p1";
regulator-min-microvolt = <1104000>;
regulator-max-microvolt = <1104000>;
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
regulator-allow-set-load;
regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
RPMH_REGULATOR_MODE_HPM>;
};
vreg_l2n_1p056: ldo2 {
regulator-name = "vreg_l2n_1p056";
regulator-min-microvolt = <1056000>;
regulator-max-microvolt = <1056000>;
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
regulator-allow-set-load;
regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
RPMH_REGULATOR_MODE_HPM>;
};
vreg_l3n_1p8: ldo3 {
regulator-name = "vreg_l3n_1p8";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
};
vreg_l4n_1p8: ldo4 {
regulator-name = "vreg_l4n_1p8";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
};
vreg_l5n_2p8: ldo5 {
regulator-name = "vreg_l5n_2p8";
regulator-min-microvolt = <2800000>;
regulator-max-microvolt = <2800000>;
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
};
vreg_l6n_2p8: ldo6 {
regulator-name = "vreg_l6n_2p8";
regulator-min-microvolt = <2800000>;
regulator-max-microvolt = <2800000>;
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
};
vreg_l7n_3p3: ldo7 {
regulator-name = "vreg_l7n_3p3";
regulator-min-microvolt = <3304000>;
regulator-max-microvolt = <3304000>;
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
};
};
};
&dispcc {

439
arch/arm64/boot/dts/qcom/sm8650-qrd.dts
View File

@ -77,9 +77,83 @@
reg = <1>;
pmic_glink_ss_in: endpoint {
remote-endpoint = <&usb_1_dwc3_ss>;
remote-endpoint = <&redriver_ss_out>;
};
};
port@2 {
reg = <2>;
pmic_glink_sbu: endpoint {
remote-endpoint = <&wcd_usbss_sbu_mux>;
};
};
};
};
};
sound {
compatible = "qcom,sm8650-sndcard", "qcom,sm8450-sndcard";
model = "SM8650-QRD";
audio-routing = "SpkrLeft IN", "WSA_SPK1 OUT",
"SpkrRight IN", "WSA_SPK2 OUT",
"IN1_HPHL", "HPHL_OUT",
"IN2_HPHR", "HPHR_OUT",
"AMIC1", "MIC BIAS1",
"AMIC2", "MIC BIAS2",
"AMIC3", "MIC BIAS3",
"AMIC4", "MIC BIAS3",
"AMIC5", "MIC BIAS4",
"TX SWR_INPUT0", "ADC1_OUTPUT",
"TX SWR_INPUT1", "ADC2_OUTPUT",
"TX SWR_INPUT2", "ADC3_OUTPUT",
"TX SWR_INPUT3", "ADC4_OUTPUT";
wcd-playback-dai-link {
link-name = "WCD Playback";
cpu {
sound-dai = <&q6apmbedai RX_CODEC_DMA_RX_0>;
};
codec {
sound-dai = <&wcd939x 0>, <&swr1 0>, <&lpass_rxmacro 0>;
};
platform {
sound-dai = <&q6apm>;
};
};
wcd-capture-dai-link {
link-name = "WCD Capture";
cpu {
sound-dai = <&q6apmbedai TX_CODEC_DMA_TX_3>;
};
codec {
sound-dai = <&wcd939x 1>, <&swr2 0>, <&lpass_txmacro 0>;
};
platform {
sound-dai = <&q6apm>;
};
};
wsa-dai-link {
link-name = "WSA Playback";
cpu {
sound-dai = <&q6apmbedai WSA_CODEC_DMA_RX_0>;
};
codec {
sound-dai = <&left_spkr>, <&right_spkr>, <&swr0 0>, <&lpass_wsamacro 0>;
};
platform {
sound-dai = <&q6apm>;
};
};
};
@ -94,6 +168,41 @@
regulator-always-on;
regulator-boot-on;
};
wcd939x: audio-codec {
compatible = "qcom,wcd9395-codec", "qcom,wcd9390-codec";
pinctrl-0 = <&wcd_default>;
pinctrl-names = "default";
qcom,micbias1-microvolt = <1800000>;
qcom,micbias2-microvolt = <1800000>;
qcom,micbias3-microvolt = <1800000>;
qcom,micbias4-microvolt = <1800000>;
qcom,mbhc-buttons-vthreshold-microvolt = <75000 150000 237000 500000 500000 500000 500000 500000>;
qcom,mbhc-headset-vthreshold-microvolt = <1700000>;
qcom,mbhc-headphone-vthreshold-microvolt = <50000>;
qcom,rx-device = <&wcd_rx>;
qcom,tx-device = <&wcd_tx>;
reset-gpios = <&tlmm 107 GPIO_ACTIVE_LOW>;
vdd-buck-supply = <&vreg_l15b_1p8>;
vdd-rxtx-supply = <&vreg_l15b_1p8>;
vdd-io-supply = <&vreg_l15b_1p8>;
vdd-mic-bias-supply = <&vreg_bob1>;
#sound-dai-cells = <1>;
mode-switch;
orientation-switch;
port {
wcd_codec_headset_in: endpoint {
remote-endpoint = <&wcd_usbss_headset_out>;
};
};
};
};
&apps_rsc {
@ -436,6 +545,138 @@
RPMH_REGULATOR_MODE_HPM>;
};
};
regulators-6 {
compatible = "qcom,pm8010-rpmh-regulators";
qcom,pmic-id = "m";
vdd-l1-l2-supply = <&vreg_s1c_1p2>;
vdd-l3-l4-supply = <&vreg_bob2>;
vdd-l5-supply = <&vreg_s6c_1p8>;
vdd-l6-supply = <&vreg_bob1>;
vdd-l7-supply = <&vreg_bob1>;
vreg_l1m_1p1: ldo1 {
regulator-name = "vreg_l1m_1p1";
regulator-min-microvolt = <1104000>;
regulator-max-microvolt = <1104000>;
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
regulator-allow-set-load;
regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
RPMH_REGULATOR_MODE_HPM>;
};
vreg_l2m_1p056: ldo2 {
regulator-name = "vreg_l2m_1p056";
regulator-min-microvolt = <1056000>;
regulator-max-microvolt = <1056000>;
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
regulator-allow-set-load;
regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
RPMH_REGULATOR_MODE_HPM>;
};
vreg_l3m_2p8: ldo3 {
regulator-name = "vreg_l3m_2p8";
regulator-min-microvolt = <2800000>;
regulator-max-microvolt = <2800000>;
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
};
vreg_l4m_2p8: ldo4 {
regulator-name = "vreg_l4m_2p8";
regulator-min-microvolt = <2800000>;
regulator-max-microvolt = <2800000>;
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
};
vreg_l5m_1p8: ldo5 {
regulator-name = "vreg_l5m_1p8";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
};
vreg_l6m_2p8: ldo6 {
regulator-name = "vreg_l6m_2p8";
regulator-min-microvolt = <2800000>;
regulator-max-microvolt = <2800000>;
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
};
vreg_l7m_2p96: ldo7 {
regulator-name = "vreg_l7m_2p96";
regulator-min-microvolt = <2960000>;
regulator-max-microvolt = <2960000>;
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
};
};
regulators-7 {
compatible = "qcom,pm8010-rpmh-regulators";
qcom,pmic-id = "n";
vdd-l1-l2-supply = <&vreg_s1c_1p2>;
vdd-l3-l4-supply = <&vreg_s6c_1p8>;
vdd-l5-supply = <&vreg_bob2>;
vdd-l6-supply = <&vreg_bob2>;
vdd-l7-supply = <&vreg_bob1>;
vreg_l1n_1p1: ldo1 {
regulator-name = "vreg_l1n_1p1";
regulator-min-microvolt = <1104000>;
regulator-max-microvolt = <1104000>;
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
regulator-allow-set-load;
regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
RPMH_REGULATOR_MODE_HPM>;
};
vreg_l2n_1p056: ldo2 {
regulator-name = "vreg_l2n_1p056";
regulator-min-microvolt = <1056000>;
regulator-max-microvolt = <1056000>;
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
regulator-allow-set-load;
regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
RPMH_REGULATOR_MODE_HPM>;
};
vreg_l3n_1p8: ldo3 {
regulator-name = "vreg_l3n_1p8";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
};
vreg_l4n_1p8: ldo4 {
regulator-name = "vreg_l4n_1p8";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
};
vreg_l5n_2p8: ldo5 {
regulator-name = "vreg_l5n_2p8";
regulator-min-microvolt = <2800000>;
regulator-max-microvolt = <2800000>;
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
};
vreg_l6n_2p8: ldo6 {
regulator-name = "vreg_l6n_2p8";
regulator-min-microvolt = <2800000>;
regulator-max-microvolt = <2800000>;
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
};
vreg_l7n_3p3: ldo7 {
regulator-name = "vreg_l7n_3p3";
regulator-min-microvolt = <3304000>;
regulator-max-microvolt = <3304000>;
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
};
};
};
&dispcc {
@ -446,6 +687,78 @@
status = "okay";
};
&i2c3 {
status = "okay";
wcd_usbss: typec-mux@e {
compatible = "qcom,wcd9395-usbss", "qcom,wcd9390-usbss";
reg = <0xe>;
vdd-supply = <&vreg_l15b_1p8>;
reset-gpios = <&tlmm 152 GPIO_ACTIVE_HIGH>;
mode-switch;
orientation-switch;
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
wcd_usbss_sbu_mux: endpoint {
remote-endpoint = <&pmic_glink_sbu>;
};
};
port@1 {
reg = <1>;
wcd_usbss_headset_out: endpoint {
remote-endpoint = <&wcd_codec_headset_in>;
};
};
};
};
};
&i2c6 {
status = "okay";
typec-mux@1c {
compatible = "onnn,nb7vpq904m";
reg = <0x1c>;
vcc-supply = <&vreg_l15b_1p8>;
retimer-switch;
orientation-switch;
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
redriver_ss_out: endpoint {
remote-endpoint = <&pmic_glink_ss_in>;
};
};
port@1 {
reg = <1>;
redriver_ss_in: endpoint {
data-lanes = <3 2 1 0>;
remote-endpoint = <&usb_dp_qmpphy_out>;
};
};
};
};
};
&ipa {
qcom,gsi-loader = "self";
memory-region = <&ipa_fw_mem>;
@ -453,6 +766,16 @@
status = "okay";
};
&lpass_tlmm {
spkr_1_sd_n_active: spkr-1-sd-n-active-state {
pins = "gpio21";
function = "gpio";
drive-strength = <16>;
bias-disable;
output-low;
};
};
&mdss {
status = "okay";
};
@ -495,6 +818,15 @@
status = "okay";
};
&mdss_dp0 {
status = "okay";
};
&mdss_dp0_out {
data-lanes = <0 1>;
remote-endpoint = <&usb_dp_qmpphy_dp_in>;
};
&mdss_mdp {
status = "okay";
};
@ -600,6 +932,11 @@
status = "okay";
};
&qup_i2c3_data_clk {
/* Use internal I2C pull-up */
bias-pull-up = <2200>;
};
&qupv3_id_0 {
status = "okay";
};
@ -657,6 +994,74 @@
};
};
&swr0 {
status = "okay";
/* WSA8845, Speaker Left */
left_spkr: speaker@0,0 {
compatible = "sdw20217020400";
reg = <0 0>;
pinctrl-0 = <&spkr_1_sd_n_active>;
pinctrl-names = "default";
powerdown-gpios = <&lpass_tlmm 21 GPIO_ACTIVE_LOW>;
#sound-dai-cells = <0>;
sound-name-prefix = "SpkrLeft";
vdd-1p8-supply = <&vreg_l15b_1p8>;
vdd-io-supply = <&vreg_l3c_1p2>;
};
/* WSA8845, Speaker Right */
right_spkr: speaker@0,1 {
compatible = "sdw20217020400";
reg = <0 1>;
pinctrl-0 = <&spkr_2_sd_n_active>;
pinctrl-names = "default";
powerdown-gpios = <&tlmm 77 GPIO_ACTIVE_LOW>;
#sound-dai-cells = <0>;
sound-name-prefix = "SpkrRight";
vdd-1p8-supply = <&vreg_l15b_1p8>;
vdd-io-supply = <&vreg_l3c_1p2>;
};
};
&swr1 {
status = "okay";
/* WCD9395 RX */
wcd_rx: codec@0,4 {
compatible = "sdw20217010e00";
reg = <0 4>;
/*
* WCD9395 RX Port 1 (HPH_L/R) <=> SWR1 Port 1 (HPH_L/R)
* WCD9395 RX Port 2 (CLSH) <=> SWR1 Port 2 (CLSH)
* WCD9395 RX Port 3 (COMP_L/R) <=> SWR1 Port 3 (COMP_L/R)
* WCD9395 RX Port 4 (LO) <=> SWR1 Port 4 (LO)
* WCD9395 RX Port 5 (DSD_L/R) <=> SWR1 Port 5 (DSD_L/R)
* WCD9395 RX Port 6 (HIFI_PCM_L/R) <=> SWR1 Port 9 (HIFI_PCM_L/R)
*/
qcom,rx-port-mapping = <1 2 3 4 5 9>;
};
};
&swr2 {
status = "okay";
/* WCD9395 TX */
wcd_tx: codec@0,3 {
compatible = "sdw20217010e00";
reg = <0 3>;
/*
* WCD9395 TX Port 1 (ADC1,2,3,4) <=> SWR2 Port 2 (TX SWR_INPUT 0,1,2,3)
* WCD9395 TX Port 2 (ADC3,4 & DMIC0,1) <=> SWR2 Port 2 (TX SWR_INPUT 0,1,2,3)
* WCD9395 TX Port 3 (DMIC0,1,2,3 & MBHC) <=> SWR2 Port 3 (TX SWR_INPUT 4,5,6,7)
* WCD9395 TX Port 4 (DMIC4,5,6,7) <=> SWR2 Port 4 (TX SWR_INPUT 8,9,10,11)
*/
qcom,tx-port-mapping = <2 2 3 4>;
};
};
&tlmm {
/* Reserved I/Os for NFC */
gpio-reserved-ranges = <32 8>;
@ -704,6 +1109,14 @@
bias-pull-down;
};
spkr_2_sd_n_active: spkr-2-sd-n-active-state {
pins = "gpio77";
function = "gpio";
drive-strength = <16>;
bias-disable;
output-low;
};
ts_irq: ts-irq-state {
pins = "gpio161";
function = "gpio";
@ -718,6 +1131,14 @@
drive-strength = <8>;
bias-pull-up;
};
wcd_default: wcd-reset-n-active-state {
pins = "gpio107";
function = "gpio";
drive-strength = <16>;
bias-disable;
output-low;
};
};
&uart14 {
@ -787,7 +1208,7 @@
};
&usb_1_dwc3_ss {
remote-endpoint = <&pmic_glink_ss_in>;
remote-endpoint = <&usb_dp_qmpphy_usb_ss_in>;
};
&usb_1_hsphy {
@ -803,9 +1224,23 @@
vdda-phy-supply = <&vreg_l3i_1p2>;
vdda-pll-supply = <&vreg_l3g_0p91>;
orientation-switch;
status = "okay";
};
&usb_dp_qmpphy_dp_in {
remote-endpoint = <&mdss_dp0_out>;
};
&usb_dp_qmpphy_out {
remote-endpoint = <&redriver_ss_in>;
};
&usb_dp_qmpphy_usb_ss_in {
remote-endpoint = <&usb_1_dwc3_ss>;
};
&xo_board {
clock-frequency = <76800000>;
};

81
arch/arm64/boot/dts/qcom/sm8650.dtsi
View File

@ -525,6 +525,11 @@
no-map;
};
qlink_logging_mem: qlink-logging@84800000 {
reg = <0 0x84800000 0 0x200000>;
no-map;
};
mpss_dsm_mem: mpss-dsm@86b00000 {
reg = <0 0x86b00000 0 0x4900000>;
no-map;
@ -1228,7 +1233,7 @@
clocks = <&gcc GCC_QUPV3_WRAP2_S6_CLK>;
clock-names = "se";
interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS
interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS
&clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>,
<&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
&config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>;
@ -1250,7 +1255,7 @@
clocks = <&gcc GCC_QUPV3_WRAP2_S7_CLK>;
clock-names = "se";
interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS
interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS
&clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>,
<&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
&config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>;
@ -2213,8 +2218,22 @@
<0 0x60100000 0 0x100000>;
reg-names = "parf", "dbi", "elbi", "atu", "config";
interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "msi";
interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "msi0",
"msi1",
"msi2",
"msi3",
"msi4",
"msi5",
"msi6",
"msi7";
clocks = <&gcc GCC_PCIE_0_AUX_CLK>,
<&gcc GCC_PCIE_0_CFG_AHB_CLK>,
@ -2255,6 +2274,11 @@
interrupt-map-mask = <0 0 0 0x7>;
#interrupt-cells = <1>;
/* Entries are reversed due to the unusual ITS DeviceID encoding */
msi-map = <0x0 &gic_its 0x1401 0x1>,
<0x100 &gic_its 0x1400 0x1>;
msi-map-mask = <0xff00>;
linux,pci-domain = <0>;
num-lanes = <2>;
bus-range = <0 0xff>;
@ -2317,8 +2341,22 @@
"atu",
"config";
interrupts = <GIC_SPI 307 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "msi";
interrupts = <GIC_SPI 307 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 313 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 314 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 374 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 375 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "msi0",
"msi1",
"msi2",
"msi3",
"msi4",
"msi5",
"msi6",
"msi7";
clocks = <&gcc GCC_PCIE_1_AUX_CLK>,
<&gcc GCC_PCIE_1_CFG_AHB_CLK>,
@ -2364,6 +2402,11 @@
interrupt-map-mask = <0 0 0 0x7>;
#interrupt-cells = <1>;
/* Entries are reversed due to the unusual ITS DeviceID encoding */
msi-map = <0x0 &gic_its 0x1481 0x1>,
<0x100 &gic_its 0x1480 0x1>;
msi-map-mask = <0xff00>;
linux,pci-domain = <1>;
num-lanes = <2>;
bus-range = <0 0xff>;
@ -2448,10 +2491,12 @@
compatible = "qcom,sm8650-qmp-ufs-phy";
reg = <0 0x01d80000 0 0x2000>;
clocks = <&tcsr TCSR_UFS_CLKREF_EN>,
<&gcc GCC_UFS_PHY_PHY_AUX_CLK>;
clocks = <&rpmhcc RPMH_CXO_CLK>,
<&gcc GCC_UFS_PHY_PHY_AUX_CLK>,
<&tcsr TCSR_UFS_CLKREF_EN>;
clock-names = "ref",
"ref_aux";
"ref_aux",
"qref";
resets = <&ufs_mem_hc 0>;
reset-names = "ufsphy";
@ -2627,7 +2672,8 @@
"mss";
memory-region = <&mpss_mem>, <&q6_mpss_dtb_mem>,
<&mpss_dsm_mem>, <&mpss_dsm_mem_2>;
<&mpss_dsm_mem>, <&mpss_dsm_mem_2>,
<&qlink_logging_mem>;
qcom,qmp = <&aoss_qmp>;
@ -2919,7 +2965,7 @@
};
};
dmic02_default: dmic02-default-state {
dmic23_default: dmic23-default-state {
clk-pins {
pins = "gpio8";
function = "dmic2_clk";
@ -4808,6 +4854,7 @@
iommus = <&apps_smmu 0x1003 0x80>,
<&apps_smmu 0x1043 0x20>;
dma-coherent;
};
compute-cb@4 {
@ -4816,6 +4863,7 @@
iommus = <&apps_smmu 0x1004 0x80>,
<&apps_smmu 0x1044 0x20>;
dma-coherent;
};
compute-cb@5 {
@ -4824,6 +4872,7 @@
iommus = <&apps_smmu 0x1005 0x80>,
<&apps_smmu 0x1045 0x20>;
dma-coherent;
};
compute-cb@6 {
@ -4832,6 +4881,7 @@
iommus = <&apps_smmu 0x1006 0x80>,
<&apps_smmu 0x1046 0x20>;
dma-coherent;
};
compute-cb@7 {
@ -4841,6 +4891,7 @@
iommus = <&apps_smmu 0x1007 0x40>,
<&apps_smmu 0x1067 0x0>,
<&apps_smmu 0x1087 0x0>;
dma-coherent;
};
};
@ -4961,6 +5012,7 @@
iommus = <&apps_smmu 0x1961 0x0>,
<&apps_smmu 0x0c01 0x20>,
<&apps_smmu 0x19c1 0x0>;
dma-coherent;
};
compute-cb@2 {
@ -4970,6 +5022,7 @@
iommus = <&apps_smmu 0x1962 0x0>,
<&apps_smmu 0x0c02 0x20>,
<&apps_smmu 0x19c2 0x0>;
dma-coherent;
};
compute-cb@3 {
@ -4979,6 +5032,7 @@
iommus = <&apps_smmu 0x1963 0x0>,
<&apps_smmu 0x0c03 0x20>,
<&apps_smmu 0x19c3 0x0>;
dma-coherent;
};
compute-cb@4 {
@ -4988,6 +5042,7 @@
iommus = <&apps_smmu 0x1964 0x0>,
<&apps_smmu 0x0c04 0x20>,
<&apps_smmu 0x19c4 0x0>;
dma-coherent;
};
compute-cb@5 {
@ -4997,6 +5052,7 @@
iommus = <&apps_smmu 0x1965 0x0>,
<&apps_smmu 0x0c05 0x20>,
<&apps_smmu 0x19c5 0x0>;
dma-coherent;
};
compute-cb@6 {
@ -5006,6 +5062,7 @@
iommus = <&apps_smmu 0x1966 0x0>,
<&apps_smmu 0x0c06 0x20>,
<&apps_smmu 0x19c6 0x0>;
dma-coherent;
};
compute-cb@7 {
@ -5015,6 +5072,7 @@
iommus = <&apps_smmu 0x1967 0x0>,
<&apps_smmu 0x0c07 0x20>,
<&apps_smmu 0x19c7 0x0>;
dma-coherent;
};
compute-cb@8 {
@ -5024,6 +5082,7 @@
iommus = <&apps_smmu 0x1968 0x0>,
<&apps_smmu 0x0c08 0x20>,
<&apps_smmu 0x19c8 0x0>;
dma-coherent;
};
};
};

450
arch/arm64/boot/dts/qcom/x1e80100-crd.dts
View File

@ -18,10 +18,124 @@
serial0 = &uart21;
};
wcd938x: audio-codec {
compatible = "qcom,wcd9385-codec";
pinctrl-names = "default";
pinctrl-0 = <&wcd_default>;
qcom,micbias1-microvolt = <1800000>;
qcom,micbias2-microvolt = <1800000>;
qcom,micbias3-microvolt = <1800000>;
qcom,micbias4-microvolt = <1800000>;
qcom,mbhc-buttons-vthreshold-microvolt = <75000 150000 237000 500000 500000 500000 500000 500000>;
qcom,mbhc-headset-vthreshold-microvolt = <1700000>;
qcom,mbhc-headphone-vthreshold-microvolt = <50000>;
qcom,rx-device = <&wcd_rx>;
qcom,tx-device = <&wcd_tx>;
reset-gpios = <&tlmm 191 GPIO_ACTIVE_LOW>;
vdd-buck-supply = <&vreg_l15b_1p8>;
vdd-rxtx-supply = <&vreg_l15b_1p8>;
vdd-io-supply = <&vreg_l15b_1p8>;
vdd-mic-bias-supply = <&vreg_bob1>;
#sound-dai-cells = <1>;
};
chosen {
stdout-path = "serial0:115200n8";
};
sound {
compatible = "qcom,x1e80100-sndcard";
model = "X1E80100-CRD";
audio-routing = "WooferLeft IN", "WSA WSA_SPK1 OUT",
"TwitterLeft IN", "WSA WSA_SPK2 OUT",
"WooferRight IN", "WSA2 WSA_SPK2 OUT",
"TwitterRight IN", "WSA2 WSA_SPK2 OUT",
"IN1_HPHL", "HPHL_OUT",
"IN2_HPHR", "HPHR_OUT",
"AMIC2", "MIC BIAS2",
"VA DMIC0", "MIC BIAS3",
"VA DMIC1", "MIC BIAS3",
"VA DMIC2", "MIC BIAS1",
"VA DMIC3", "MIC BIAS1",
"VA DMIC0", "VA MIC BIAS3",
"VA DMIC1", "VA MIC BIAS3",
"VA DMIC2", "VA MIC BIAS1",
"VA DMIC3", "VA MIC BIAS1",
"TX SWR_INPUT1", "ADC2_OUTPUT";
wcd-playback-dai-link {
link-name = "WCD Playback";
cpu {
sound-dai = <&q6apmbedai RX_CODEC_DMA_RX_0>;
};
codec {
sound-dai = <&wcd938x 0>, <&swr1 0>, <&lpass_rxmacro 0>;
};
platform {
sound-dai = <&q6apm>;
};
};
wcd-capture-dai-link {
link-name = "WCD Capture";
cpu {
sound-dai = <&q6apmbedai TX_CODEC_DMA_TX_3>;
};
codec {
sound-dai = <&wcd938x 1>, <&swr2 0>, <&lpass_txmacro 0>;
};
platform {
sound-dai = <&q6apm>;
};
};
wsa-dai-link {
link-name = "WSA Playback";
cpu {
sound-dai = <&q6apmbedai WSA_CODEC_DMA_RX_0>;
};
codec {
sound-dai = <&left_woofer>, <&left_tweeter>,
<&swr0 0>, <&lpass_wsamacro 0>,
<&right_woofer>, <&right_tweeter>,
<&swr3 0>, <&lpass_wsa2macro 0>;
};
platform {
sound-dai = <&q6apm>;
};
};
va-dai-link {
link-name = "VA Capture";
cpu {
sound-dai = <&q6apmbedai VA_CODEC_DMA_TX_0>;
};
codec {
sound-dai = <&lpass_vamacro 0>;
};
platform {
sound-dai = <&q6apm>;
};
};
};
vph_pwr: vph-pwr-regulator {
compatible = "regulator-fixed";
@ -401,10 +515,251 @@
};
};
&i2c0 {
clock-frequency = <400000>;
status = "okay";
touchpad@15 {
compatible = "hid-over-i2c";
reg = <0x15>;
hid-descr-addr = <0x1>;
interrupts-extended = <&tlmm 3 IRQ_TYPE_LEVEL_LOW>;
pinctrl-0 = <&tpad_default>;
pinctrl-names = "default";
wakeup-source;
};
keyboard@3a {
compatible = "hid-over-i2c";
reg = <0x3a>;
hid-descr-addr = <0x1>;
interrupts-extended = <&tlmm 67 IRQ_TYPE_LEVEL_LOW>;
pinctrl-0 = <&kybd_default>;
pinctrl-names = "default";
wakeup-source;
};
};
&i2c8 {
clock-frequency = <400000>;
status = "okay";
touchscreen@10 {
compatible = "hid-over-i2c";
reg = <0x10>;
hid-descr-addr = <0x1>;
interrupts-extended = <&tlmm 51 IRQ_TYPE_LEVEL_LOW>;
pinctrl-0 = <&ts0_default>;
pinctrl-names = "default";
};
};
&lpass_tlmm {
spkr_01_sd_n_active: spkr-01-sd-n-active-state {
pins = "gpio12";
function = "gpio";
drive-strength = <16>;
bias-disable;
output-low;
};
spkr_23_sd_n_active: spkr-23-sd-n-active-state {
pins = "gpio13";
function = "gpio";
drive-strength = <16>;
bias-disable;
output-low;
};
};
&lpass_vamacro {
pinctrl-0 = <&dmic01_default>, <&dmic23_default>;
pinctrl-names = "default";
vdd-micb-supply = <&vreg_l1b_1p8>;
qcom,dmic-sample-rate = <4800000>;
};
&mdss {
status = "okay";
};
&mdss_dp3 {
compatible = "qcom,x1e80100-dp";
/delete-property/ #sound-dai-cells;
data-lanes = <0 1 2 3>;
status = "okay";
aux-bus {
panel {
compatible = "edp-panel";
power-supply = <&vreg_edp_3p3>;
port {
edp_panel_in: endpoint {
remote-endpoint = <&mdss_dp3_out>;
};
};
};
};
ports {
port@1 {
reg = <1>;
mdss_dp3_out: endpoint {
remote-endpoint = <&edp_panel_in>;
};
};
};
};
&mdss_dp3_phy {
vdda-phy-supply = <&vreg_l3j_0p8>;
vdda-pll-supply = <&vreg_l2j_1p2>;
status = "okay";
};
&pcie4 {
status = "okay";
};
&pcie4_phy {
vdda-phy-supply = <&vreg_l3j_0p8>;
vdda-pll-supply = <&vreg_l3e_1p2>;
status = "okay";
};
&pcie6a {
status = "okay";
};
&pcie6a_phy {
vdda-phy-supply = <&vreg_l3j_0p8>;
vdda-pll-supply = <&vreg_l2j_1p2>;
status = "okay";
};
&qupv3_0 {
status = "okay";
};
&qupv3_1 {
status = "okay";
};
&qupv3_2 {
status = "okay";
};
&remoteproc_adsp {
firmware-name = "qcom/x1e80100/adsp.mbn",
"qcom/x1e80100/adsp_dtb.mbn";
status = "okay";
};
&remoteproc_cdsp {
firmware-name = "qcom/x1e80100/cdsp.mbn",
"qcom/x1e80100/cdsp_dtb.mbn";
status = "okay";
};
&swr0 {
status = "okay";
/* WSA8845, Left Woofer */
left_woofer: speaker@0,0 {
compatible = "sdw20217020400";
reg = <0 0>;
pinctrl-0 = <&spkr_01_sd_n_active>;
pinctrl-names = "default";
powerdown-gpios = <&lpass_tlmm 12 GPIO_ACTIVE_LOW>;
#sound-dai-cells = <0>;
sound-name-prefix = "WooferLeft";
vdd-1p8-supply = <&vreg_l15b_1p8>;
vdd-io-supply = <&vreg_l12b_1p2>;
};
/* WSA8845, Left Tweeter */
left_tweeter: speaker@0,1 {
compatible = "sdw20217020400";
reg = <0 1>;
/* pinctrl in left_woofer node because of sharing the GPIO*/
powerdown-gpios = <&lpass_tlmm 12 GPIO_ACTIVE_LOW>;
#sound-dai-cells = <0>;
sound-name-prefix = "TwitterLeft";
vdd-1p8-supply = <&vreg_l15b_1p8>;
vdd-io-supply = <&vreg_l12b_1p2>;
};
};
&swr1 {
status = "okay";
/* WCD9385 RX */
wcd_rx: codec@0,4 {
compatible = "sdw20217010d00";
reg = <0 4>;
qcom,rx-port-mapping = <1 2 3 4 5>;
};
};
&swr2 {
status = "okay";
/* WCD9385 TX */
wcd_tx: codec@0,3 {
compatible = "sdw20217010d00";
reg = <0 3>;
qcom,tx-port-mapping = <1 1 2 3>;
};
};
&swr3 {
status = "okay";
/* WSA8845, Right Woofer */
right_woofer: speaker@0,0 {
compatible = "sdw20217020400";
reg = <0 0>;
pinctrl-0 = <&spkr_23_sd_n_active>;
pinctrl-names = "default";
powerdown-gpios = <&lpass_tlmm 13 GPIO_ACTIVE_LOW>;
#sound-dai-cells = <0>;
sound-name-prefix = "WooferRight";
vdd-1p8-supply = <&vreg_l15b_1p8>;
vdd-io-supply = <&vreg_l12b_1p2>;
};
/* WSA8845, Right Tweeter */
right_tweeter: speaker@0,1 {
compatible = "sdw20217020400";
reg = <0 1>;
/* pinctrl in right_woofer node because of sharing the GPIO*/
powerdown-gpios = <&lpass_tlmm 13 GPIO_ACTIVE_LOW>;
#sound-dai-cells = <0>;
sound-name-prefix = "TwitterRight";
vdd-1p8-supply = <&vreg_l15b_1p8>;
vdd-io-supply = <&vreg_l12b_1p2>;
};
};
&tlmm {
gpio-reserved-ranges = <34 2>, /* Unused */
<44 4>, /* SPI (TPM) */
@ -416,9 +771,104 @@
drive-strength = <16>;
bias-disable;
};
kybd_default: kybd-default-state {
pins = "gpio67";
function = "gpio";
bias-disable;
};
tpad_default: tpad-default-state {
pins = "gpio3";
function = "gpio";
bias-disable;
};
ts0_default: ts0-default-state {
int-n-pins {
pins = "gpio51";
function = "gpio";
bias-disable;
};
reset-n-pins {
pins = "gpio48";
function = "gpio";
output-high;
drive-strength = <16>;
};
};
wcd_default: wcd-reset-n-active-state {
pins = "gpio191";
function = "gpio";
drive-strength = <16>;
bias-disable;
output-low;
};
};
&uart21 {
compatible = "qcom,geni-debug-uart";
status = "okay";
};
&usb_1_ss0_hsphy {
vdd-supply = <&vreg_l2e_0p8>;
vdda12-supply = <&vreg_l3e_1p2>;
status = "okay";
};
&usb_1_ss0_qmpphy {
status = "okay";
};
&usb_1_ss0 {
status = "okay";
};
&usb_1_ss0_dwc3 {
dr_mode = "host";
usb-role-switch;
};
&usb_1_ss1_hsphy {
vdd-supply = <&vreg_l2e_0p8>;
vdda12-supply = <&vreg_l3e_1p2>;
status = "okay";
};
&usb_1_ss1_qmpphy {
status = "okay";
};
&usb_1_ss1 {
status = "okay";
};
&usb_1_ss1_dwc3 {
dr_mode = "host";
usb-role-switch;
};
&usb_1_ss2_hsphy {
vdd-supply = <&vreg_l2e_0p8>;
vdda12-supply = <&vreg_l3e_1p2>;
status = "okay";
};
&usb_1_ss2_qmpphy {
status = "okay";
};
&usb_1_ss2 {
status = "okay";
};
&usb_1_ss2_dwc3 {
dr_mode = "host";
usb-role-switch;
};

175
arch/arm64/boot/dts/qcom/x1e80100-qcp.dts
View File

@ -5,6 +5,7 @@
/dts-v1/;
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/regulator/qcom,rpmh-regulator.h>
#include "x1e80100.dtsi"
@ -31,6 +32,23 @@
regulator-always-on;
regulator-boot-on;
};
vreg_edp_3p3: regulator-edp-3p3 {
compatible = "regulator-fixed";
regulator-name = "VREG_EDP_3P3";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
gpio = <&tlmm 70 GPIO_ACTIVE_HIGH>;
enable-active-high;
pinctrl-0 = <&edp_reg_en>;
pinctrl-names = "default";
regulator-always-on;
regulator-boot-on;
};
};
&apps_rsc {
@ -243,7 +261,7 @@
qcom,pmic-id = "e";
vdd-l2-supply = <&vreg_s1f_0p7>;
vdd-l3-supply = <&vph_pwr>;
vdd-l3-supply = <&vreg_s5j_1p2>;
vreg_l2e_0p8: ldo2 {
regulator-name = "vreg_l2e_0p8";
@ -349,7 +367,7 @@
qcom,pmic-id = "j";
vdd-l1-supply = <&vreg_s1f_0p7>;
vdd-l2-supply = <&vph_pwr>;
vdd-l2-supply = <&vreg_s5j_1p2>;
vdd-l3-supply = <&vreg_s1f_0p7>;
vdd-s5-supply = <&vph_pwr>;
@ -383,17 +401,170 @@
};
};
&mdss {
status = "okay";
};
&mdss_dp3 {
compatible = "qcom,x1e80100-dp";
/delete-property/ #sound-dai-cells;
data-lanes = <0 1 2 3>;
status = "okay";
aux-bus {
panel {
compatible = "edp-panel";
power-supply = <&vreg_edp_3p3>;
port {
edp_panel_in: endpoint {
remote-endpoint = <&mdss_dp3_out>;
};
};
};
};
ports {
port@1 {
reg = <1>;
mdss_dp3_out: endpoint {
remote-endpoint = <&edp_panel_in>;
};
};
};
};
&mdss_dp3_phy {
vdda-phy-supply = <&vreg_l3j_0p8>;
vdda-pll-supply = <&vreg_l2j_1p2>;
status = "okay";
};
&pcie4 {
status = "okay";
};
&pcie4_phy {
vdda-phy-supply = <&vreg_l3j_0p8>;
vdda-pll-supply = <&vreg_l3e_1p2>;
status = "okay";
};
&pcie6a {
status = "okay";
};
&pcie6a_phy {
vdda-phy-supply = <&vreg_l3j_0p8>;
vdda-pll-supply = <&vreg_l2j_1p2>;
status = "okay";
};
&qupv3_0 {
status = "okay";
};
&qupv3_1 {
status = "okay";
};
&qupv3_2 {
status = "okay";
};
&remoteproc_adsp {
firmware-name = "qcom/x1e80100/adsp.mbn",
"qcom/x1e80100/adsp_dtb.mbn";
status = "okay";
};
&remoteproc_cdsp {
firmware-name = "qcom/x1e80100/cdsp.mbn",
"qcom/x1e80100/cdsp_dtb.mbn";
status = "okay";
};
&tlmm {
gpio-reserved-ranges = <33 3>, /* Unused */
<44 4>, /* SPI (TPM) */
<238 1>; /* UFS Reset */
edp_reg_en: edp-reg-en-state {
pins = "gpio70";
function = "gpio";
drive-strength = <16>;
bias-disable;
};
};
&uart21 {
compatible = "qcom,geni-debug-uart";
status = "okay";
};
&usb_1_ss0_hsphy {
vdd-supply = <&vreg_l2e_0p8>;
vdda12-supply = <&vreg_l3e_1p2>;
status = "okay";
};
&usb_1_ss0_qmpphy {
status = "okay";
};
&usb_1_ss0 {
status = "okay";
};
&usb_1_ss0_dwc3 {
dr_mode = "host";
usb-role-switch;
};
&usb_1_ss1_hsphy {
vdd-supply = <&vreg_l2e_0p8>;
vdda12-supply = <&vreg_l3e_1p2>;
status = "okay";
};
&usb_1_ss1_qmpphy {
status = "okay";
};
&usb_1_ss1 {
status = "okay";
};
&usb_1_ss1_dwc3 {
dr_mode = "host";
usb-role-switch;
};
&usb_1_ss2_hsphy {
vdd-supply = <&vreg_l2e_0p8>;
vdda12-supply = <&vreg_l3e_1p2>;
status = "okay";
};
&usb_1_ss2_qmpphy {
status = "okay";
};
&usb_1_ss2 {
status = "okay";
};
&usb_1_ss2_dwc3 {
dr_mode = "host";
usb-role-switch;
};

1777
arch/arm64/boot/dts/qcom/x1e80100.dtsi
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File diff suppressed because it is too large Load Diff

4
include/dt-bindings/clock/qcom,gcc-msm8953.h
View File

@ -218,6 +218,10 @@
#define GCC_USB3PHY_PHY_BCR 3
#define GCC_USB3_PHY_BCR 4
#define GCC_USB_30_BCR 5
#define GCC_MDSS_BCR 6
#define GCC_CRYPTO_BCR 7
#define GCC_SDCC1_BCR 8
#define GCC_SDCC2_BCR 9
/* GDSCs */
#define CPP_GDSC 0

2
include/dt-bindings/clock/qcom,gcc-sc8180x.h
View File

@ -246,6 +246,8 @@
#define GCC_PCIE_3_CLKREF_CLK 236
#define GCC_USB3_PRIM_CLKREF_CLK 237
#define GCC_USB3_SEC_CLKREF_CLK 238
#define GCC_UFS_MEM_CLKREF_EN 239
#define GCC_UFS_CARD_CLKREF_EN 240
#define GCC_EMAC_BCR 0
#define GCC_GPU_BCR 1

135
include/dt-bindings/clock/qcom,x1e80100-camcc.h Normal file
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@ -0,0 +1,135 @@
/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
/*
* Copyright (c) 2023, Qualcomm Innovation Center, Inc. All rights reserved.
*/
#ifndef _DT_BINDINGS_CLK_QCOM_CAM_CC_X1E80100_H
#define _DT_BINDINGS_CLK_QCOM_CAM_CC_X1E80100_H
/* CAM_CC clocks */
#define CAM_CC_BPS_AHB_CLK 0
#define CAM_CC_BPS_CLK 1
#define CAM_CC_BPS_CLK_SRC 2
#define CAM_CC_BPS_FAST_AHB_CLK 3
#define CAM_CC_CAMNOC_AXI_NRT_CLK 4
#define CAM_CC_CAMNOC_AXI_RT_CLK 5
#define CAM_CC_CAMNOC_AXI_RT_CLK_SRC 6
#define CAM_CC_CAMNOC_DCD_XO_CLK 7
#define CAM_CC_CAMNOC_XO_CLK 8
#define CAM_CC_CCI_0_CLK 9
#define CAM_CC_CCI_0_CLK_SRC 10
#define CAM_CC_CCI_1_CLK 11
#define CAM_CC_CCI_1_CLK_SRC 12
#define CAM_CC_CORE_AHB_CLK 13
#define CAM_CC_CPAS_AHB_CLK 14
#define CAM_CC_CPAS_BPS_CLK 15
#define CAM_CC_CPAS_FAST_AHB_CLK 16
#define CAM_CC_CPAS_IFE_0_CLK 17
#define CAM_CC_CPAS_IFE_1_CLK 18
#define CAM_CC_CPAS_IFE_LITE_CLK 19
#define CAM_CC_CPAS_IPE_NPS_CLK 20
#define CAM_CC_CPAS_SFE_0_CLK 21
#define CAM_CC_CPHY_RX_CLK_SRC 22
#define CAM_CC_CSI0PHYTIMER_CLK 23
#define CAM_CC_CSI0PHYTIMER_CLK_SRC 24
#define CAM_CC_CSI1PHYTIMER_CLK 25
#define CAM_CC_CSI1PHYTIMER_CLK_SRC 26
#define CAM_CC_CSI2PHYTIMER_CLK 27
#define CAM_CC_CSI2PHYTIMER_CLK_SRC 28
#define CAM_CC_CSI3PHYTIMER_CLK 29
#define CAM_CC_CSI3PHYTIMER_CLK_SRC 30
#define CAM_CC_CSI4PHYTIMER_CLK 31
#define CAM_CC_CSI4PHYTIMER_CLK_SRC 32
#define CAM_CC_CSI5PHYTIMER_CLK 33
#define CAM_CC_CSI5PHYTIMER_CLK_SRC 34
#define CAM_CC_CSID_CLK 35
#define CAM_CC_CSID_CLK_SRC 36
#define CAM_CC_CSID_CSIPHY_RX_CLK 37
#define CAM_CC_CSIPHY0_CLK 38
#define CAM_CC_CSIPHY1_CLK 39
#define CAM_CC_CSIPHY2_CLK 40
#define CAM_CC_CSIPHY3_CLK 41
#define CAM_CC_CSIPHY4_CLK 42
#define CAM_CC_CSIPHY5_CLK 43
#define CAM_CC_FAST_AHB_CLK_SRC 44
#define CAM_CC_GDSC_CLK 45
#define CAM_CC_ICP_AHB_CLK 46
#define CAM_CC_ICP_CLK 47
#define CAM_CC_ICP_CLK_SRC 48
#define CAM_CC_IFE_0_CLK 49
#define CAM_CC_IFE_0_CLK_SRC 50
#define CAM_CC_IFE_0_DSP_CLK 51
#define CAM_CC_IFE_0_FAST_AHB_CLK 52
#define CAM_CC_IFE_1_CLK 53
#define CAM_CC_IFE_1_CLK_SRC 54
#define CAM_CC_IFE_1_DSP_CLK 55
#define CAM_CC_IFE_1_FAST_AHB_CLK 56
#define CAM_CC_IFE_LITE_AHB_CLK 57
#define CAM_CC_IFE_LITE_CLK 58
#define CAM_CC_IFE_LITE_CLK_SRC 59
#define CAM_CC_IFE_LITE_CPHY_RX_CLK 60
#define CAM_CC_IFE_LITE_CSID_CLK 61
#define CAM_CC_IFE_LITE_CSID_CLK_SRC 62
#define CAM_CC_IPE_NPS_AHB_CLK 63
#define CAM_CC_IPE_NPS_CLK 64
#define CAM_CC_IPE_NPS_CLK_SRC 65
#define CAM_CC_IPE_NPS_FAST_AHB_CLK 66
#define CAM_CC_IPE_PPS_CLK 67
#define CAM_CC_IPE_PPS_FAST_AHB_CLK 68
#define CAM_CC_JPEG_CLK 69
#define CAM_CC_JPEG_CLK_SRC 70
#define CAM_CC_MCLK0_CLK 71
#define CAM_CC_MCLK0_CLK_SRC 72
#define CAM_CC_MCLK1_CLK 73
#define CAM_CC_MCLK1_CLK_SRC 74
#define CAM_CC_MCLK2_CLK 75
#define CAM_CC_MCLK2_CLK_SRC 76
#define CAM_CC_MCLK3_CLK 77
#define CAM_CC_MCLK3_CLK_SRC 78
#define CAM_CC_MCLK4_CLK 79
#define CAM_CC_MCLK4_CLK_SRC 80
#define CAM_CC_MCLK5_CLK 81
#define CAM_CC_MCLK5_CLK_SRC 82
#define CAM_CC_MCLK6_CLK 83
#define CAM_CC_MCLK6_CLK_SRC 84
#define CAM_CC_MCLK7_CLK 85
#define CAM_CC_MCLK7_CLK_SRC 86
#define CAM_CC_PLL0 87
#define CAM_CC_PLL0_OUT_EVEN 88
#define CAM_CC_PLL0_OUT_ODD 89
#define CAM_CC_PLL1 90
#define CAM_CC_PLL1_OUT_EVEN 91
#define CAM_CC_PLL2 92
#define CAM_CC_PLL3 93
#define CAM_CC_PLL3_OUT_EVEN 94
#define CAM_CC_PLL4 95
#define CAM_CC_PLL4_OUT_EVEN 96
#define CAM_CC_PLL6 97
#define CAM_CC_PLL6_OUT_EVEN 98
#define CAM_CC_PLL8 99
#define CAM_CC_PLL8_OUT_EVEN 100
#define CAM_CC_SFE_0_CLK 101
#define CAM_CC_SFE_0_CLK_SRC 102
#define CAM_CC_SFE_0_FAST_AHB_CLK 103
#define CAM_CC_SLEEP_CLK 104
#define CAM_CC_SLEEP_CLK_SRC 105
#define CAM_CC_SLOW_AHB_CLK_SRC 106
#define CAM_CC_XO_CLK_SRC 107
/* CAM_CC power domains */
#define CAM_CC_BPS_GDSC 0
#define CAM_CC_IFE_0_GDSC 1
#define CAM_CC_IFE_1_GDSC 2
#define CAM_CC_IPE_0_GDSC 3
#define CAM_CC_SFE_0_GDSC 4
#define CAM_CC_TITAN_TOP_GDSC 5
/* CAM_CC resets */
#define CAM_CC_BPS_BCR 0
#define CAM_CC_ICP_BCR 1
#define CAM_CC_IFE_0_BCR 2
#define CAM_CC_IFE_1_BCR 3
#define CAM_CC_IPE_0_BCR 4
#define CAM_CC_SFE_0_BCR 5
#endif

98
include/dt-bindings/clock/qcom,x1e80100-dispcc.h Normal file
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@ -0,0 +1,98 @@
/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
/*
* Copyright (c) 2023, Qualcomm Innovation Center, Inc. All rights reserved.
*/
#ifndef _DT_BINDINGS_CLK_QCOM_X1E80100_DISP_CC_H
#define _DT_BINDINGS_CLK_QCOM_X1E80100_DISP_CC_H
/* DISP_CC clocks */
#define DISP_CC_MDSS_ACCU_CLK 0
#define DISP_CC_MDSS_AHB1_CLK 1
#define DISP_CC_MDSS_AHB_CLK 2
#define DISP_CC_MDSS_AHB_CLK_SRC 3
#define DISP_CC_MDSS_BYTE0_CLK 4
#define DISP_CC_MDSS_BYTE0_CLK_SRC 5
#define DISP_CC_MDSS_BYTE0_DIV_CLK_SRC 6
#define DISP_CC_MDSS_BYTE0_INTF_CLK 7
#define DISP_CC_MDSS_BYTE1_CLK 8
#define DISP_CC_MDSS_BYTE1_CLK_SRC 9
#define DISP_CC_MDSS_BYTE1_DIV_CLK_SRC 10
#define DISP_CC_MDSS_BYTE1_INTF_CLK 11
#define DISP_CC_MDSS_DPTX0_AUX_CLK 12
#define DISP_CC_MDSS_DPTX0_AUX_CLK_SRC 13
#define DISP_CC_MDSS_DPTX0_LINK_CLK 14
#define DISP_CC_MDSS_DPTX0_LINK_CLK_SRC 15
#define DISP_CC_MDSS_DPTX0_LINK_DIV_CLK_SRC 16
#define DISP_CC_MDSS_DPTX0_LINK_INTF_CLK 17
#define DISP_CC_MDSS_DPTX0_PIXEL0_CLK 18
#define DISP_CC_MDSS_DPTX0_PIXEL0_CLK_SRC 19
#define DISP_CC_MDSS_DPTX0_PIXEL1_CLK 20
#define DISP_CC_MDSS_DPTX0_PIXEL1_CLK_SRC 21
#define DISP_CC_MDSS_DPTX0_USB_ROUTER_LINK_INTF_CLK 22
#define DISP_CC_MDSS_DPTX1_AUX_CLK 23
#define DISP_CC_MDSS_DPTX1_AUX_CLK_SRC 24
#define DISP_CC_MDSS_DPTX1_LINK_CLK 25
#define DISP_CC_MDSS_DPTX1_LINK_CLK_SRC 26
#define DISP_CC_MDSS_DPTX1_LINK_DIV_CLK_SRC 27
#define DISP_CC_MDSS_DPTX1_LINK_INTF_CLK 28
#define DISP_CC_MDSS_DPTX1_PIXEL0_CLK 29
#define DISP_CC_MDSS_DPTX1_PIXEL0_CLK_SRC 30
#define DISP_CC_MDSS_DPTX1_PIXEL1_CLK 31
#define DISP_CC_MDSS_DPTX1_PIXEL1_CLK_SRC 32
#define DISP_CC_MDSS_DPTX1_USB_ROUTER_LINK_INTF_CLK 33
#define DISP_CC_MDSS_DPTX2_AUX_CLK 34
#define DISP_CC_MDSS_DPTX2_AUX_CLK_SRC 35
#define DISP_CC_MDSS_DPTX2_LINK_CLK 36
#define DISP_CC_MDSS_DPTX2_LINK_CLK_SRC 37
#define DISP_CC_MDSS_DPTX2_LINK_DIV_CLK_SRC 38
#define DISP_CC_MDSS_DPTX2_LINK_INTF_CLK 39
#define DISP_CC_MDSS_DPTX2_PIXEL0_CLK 40
#define DISP_CC_MDSS_DPTX2_PIXEL0_CLK_SRC 41
#define DISP_CC_MDSS_DPTX2_PIXEL1_CLK 42
#define DISP_CC_MDSS_DPTX2_PIXEL1_CLK_SRC 43
#define DISP_CC_MDSS_DPTX2_USB_ROUTER_LINK_INTF_CLK 44
#define DISP_CC_MDSS_DPTX3_AUX_CLK 45
#define DISP_CC_MDSS_DPTX3_AUX_CLK_SRC 46
#define DISP_CC_MDSS_DPTX3_LINK_CLK 47
#define DISP_CC_MDSS_DPTX3_LINK_CLK_SRC 48
#define DISP_CC_MDSS_DPTX3_LINK_DIV_CLK_SRC 49
#define DISP_CC_MDSS_DPTX3_LINK_INTF_CLK 50
#define DISP_CC_MDSS_DPTX3_PIXEL0_CLK 51
#define DISP_CC_MDSS_DPTX3_PIXEL0_CLK_SRC 52
#define DISP_CC_MDSS_ESC0_CLK 53
#define DISP_CC_MDSS_ESC0_CLK_SRC 54
#define DISP_CC_MDSS_ESC1_CLK 55
#define DISP_CC_MDSS_ESC1_CLK_SRC 56
#define DISP_CC_MDSS_MDP1_CLK 57
#define DISP_CC_MDSS_MDP_CLK 58
#define DISP_CC_MDSS_MDP_CLK_SRC 59
#define DISP_CC_MDSS_MDP_LUT1_CLK 60
#define DISP_CC_MDSS_MDP_LUT_CLK 61
#define DISP_CC_MDSS_NON_GDSC_AHB_CLK 62
#define DISP_CC_MDSS_PCLK0_CLK 63
#define DISP_CC_MDSS_PCLK0_CLK_SRC 64
#define DISP_CC_MDSS_PCLK1_CLK 65
#define DISP_CC_MDSS_PCLK1_CLK_SRC 66
#define DISP_CC_MDSS_RSCC_AHB_CLK 67
#define DISP_CC_MDSS_RSCC_VSYNC_CLK 68
#define DISP_CC_MDSS_VSYNC1_CLK 69
#define DISP_CC_MDSS_VSYNC_CLK 70
#define DISP_CC_MDSS_VSYNC_CLK_SRC 71
#define DISP_CC_PLL0 72
#define DISP_CC_PLL1 73
#define DISP_CC_SLEEP_CLK 74
#define DISP_CC_SLEEP_CLK_SRC 75
#define DISP_CC_XO_CLK 76
#define DISP_CC_XO_CLK_SRC 77
/* DISP_CC resets */
#define DISP_CC_MDSS_CORE_BCR 0
#define DISP_CC_MDSS_CORE_INT2_BCR 1
#define DISP_CC_MDSS_RSCC_BCR 2
/* DISP_CC GDSCR */
#define MDSS_GDSC 0
#define MDSS_INT2_GDSC 1
#endif

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include/dt-bindings/clock/qcom,x1e80100-gpucc.h Normal file
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/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
/*
* Copyright (c) 2023, Qualcomm Innovation Center, Inc. All rights reserved.
*/
#ifndef _DT_BINDINGS_CLK_QCOM_X1E80100_GPU_CC_H
#define _DT_BINDINGS_CLK_QCOM_X1E80100_GPU_CC_H
/* GPU_CC clocks */
#define GPU_CC_AHB_CLK 0
#define GPU_CC_CB_CLK 1
#define GPU_CC_CRC_AHB_CLK 2
#define GPU_CC_CX_FF_CLK 3
#define GPU_CC_CX_GMU_CLK 4
#define GPU_CC_CXO_AON_CLK 5
#define GPU_CC_CXO_CLK 6
#define GPU_CC_DEMET_CLK 7
#define GPU_CC_DEMET_DIV_CLK_SRC 8
#define GPU_CC_FF_CLK_SRC 9
#define GPU_CC_FREQ_MEASURE_CLK 10
#define GPU_CC_GMU_CLK_SRC 11
#define GPU_CC_GX_GMU_CLK 12
#define GPU_CC_GX_VSENSE_CLK 13
#define GPU_CC_HLOS1_VOTE_GPU_SMMU_CLK 14
#define GPU_CC_HUB_AON_CLK 15
#define GPU_CC_HUB_CLK_SRC 16
#define GPU_CC_HUB_CX_INT_CLK 17
#define GPU_CC_MEMNOC_GFX_CLK 18
#define GPU_CC_MND1X_0_GFX3D_CLK 19
#define GPU_CC_MND1X_1_GFX3D_CLK 20
#define GPU_CC_PLL0 21
#define GPU_CC_PLL1 22
#define GPU_CC_SLEEP_CLK 23
#define GPU_CC_XO_CLK_SRC 24
#define GPU_CC_XO_DIV_CLK_SRC 25
/* GDSCs */
#define GPU_CX_GDSC 0
#define GPU_GX_GDSC 1
#endif

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include/dt-bindings/clock/qcom,x1e80100-tcsr.h Normal file
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/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
/*
* Copyright (c) 2023, Linaro Limited
*/
#ifndef _DT_BINDINGS_CLK_QCOM_X1E80100_TCSR_CC_H
#define _DT_BINDINGS_CLK_QCOM_X1E80100_TCSR_CC_H
/* TCSR CC clocks */
#define TCSR_PCIE_2L_4_CLKREF_EN 0
#define TCSR_PCIE_2L_5_CLKREF_EN 1
#define TCSR_PCIE_8L_CLKREF_EN 2
#define TCSR_USB3_MP0_CLKREF_EN 3
#define TCSR_USB3_MP1_CLKREF_EN 4
#define TCSR_USB2_1_CLKREF_EN 5
#define TCSR_UFS_PHY_CLKREF_EN 6
#define TCSR_USB4_1_CLKREF_EN 7
#define TCSR_USB4_2_CLKREF_EN 8
#define TCSR_USB2_2_CLKREF_EN 9
#define TCSR_PCIE_4L_CLKREF_EN 10
#define TCSR_EDP_CLKREF_EN 11
#endif

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include/dt-bindings/reset/qcom,x1e80100-gpucc.h Normal file
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/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
/*
* Copyright (c) 2023, Qualcomm Innovation Center, Inc. All rights reserved.
*/
#ifndef _DT_BINDINGS_RESET_QCOM_X1E80100_GPU_CC_H
#define _DT_BINDINGS_RESET_QCOM_X1E80100_GPU_CC_H
#define GPUCC_GPU_CC_ACD_BCR 0
#define GPUCC_GPU_CC_CB_BCR 1
#define GPUCC_GPU_CC_CX_BCR 2
#define GPUCC_GPU_CC_FAST_HUB_BCR 3
#define GPUCC_GPU_CC_FF_BCR 4
#define GPUCC_GPU_CC_GFX3D_AON_BCR 5
#define GPUCC_GPU_CC_GMU_BCR 6
#define GPUCC_GPU_CC_GX_BCR 7
#define GPUCC_GPU_CC_XO_BCR 8
#endif