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cxd2099: Remove the CHK_ERROR macro 

The CHK_ERROR macro does a flow control, violating chapter 12
of the Documentation/CodingStyle. Doing flow controls inside
macros is a bad idea, as it hides what's happening. It also
hides the var "status" with is also a bad idea.

The changes were done by this small perl script:
	my $blk=0;
	while (<>) {
		s/^\s+// if ($blk);
		$f =~ s/\s+$// if ($blk && /^\(/);
		$blk = 1 if (!m/\#/ && m/CHK_ERROR/);
		$blk=0 if ($blk && m/\;/);
		s/\n/ / if ($blk);
		$f.=$_;
	};
	$f=~ s,\n(\t+)CHK_ERROR\((.*)\)\;([^\n]*),\n\1status = \2;\3\n\1if (status < 0)\n\1\tbreak;,g;

	print $f;

And manually fixed.

Signed-off-by: Mauro Carvalho Chehab <mchehab@redhat.com>
This commit is contained in:
Mauro Carvalho Chehab 2011-07-03 18:45:37 -03:00
parent 1bd09ddcff
commit af070bd60f
1 changed files with 98 additions and 34 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

132
drivers/staging/cxd2099/cxd2099.c
View File

@ -294,8 +294,6 @@ static void cam_mode(struct cxd *ci, int mode)
#define CHK_ERROR(s) if ((status = s)) break
static int init(struct cxd *ci) static int init(struct cxd *ci)
{ {
int status; int status;
@ -303,55 +301,121 @@ static int init(struct cxd *ci)
mutex_lock(&ci->lock); mutex_lock(&ci->lock);
ci->mode = -1; ci->mode = -1;
do { do {
CHK_ERROR(write_reg(ci, 0x00, 0x00)); status = write_reg(ci, 0x00, 0x00);
CHK_ERROR(write_reg(ci, 0x01, 0x00)); if (status < 0)
CHK_ERROR(write_reg(ci, 0x02, 0x10)); break;
CHK_ERROR(write_reg(ci, 0x03, 0x00)); status = write_reg(ci, 0x01, 0x00);
CHK_ERROR(write_reg(ci, 0x05, 0xFF)); if (status < 0)
CHK_ERROR(write_reg(ci, 0x06, 0x1F)); break;
CHK_ERROR(write_reg(ci, 0x07, 0x1F)); status = write_reg(ci, 0x02, 0x10);
CHK_ERROR(write_reg(ci, 0x08, 0x28)); if (status < 0)
CHK_ERROR(write_reg(ci, 0x14, 0x20)); break;
status = write_reg(ci, 0x03, 0x00);
if (status < 0)
break;
status = write_reg(ci, 0x05, 0xFF);
if (status < 0)
break;
status = write_reg(ci, 0x06, 0x1F);
if (status < 0)
break;
status = write_reg(ci, 0x07, 0x1F);
if (status < 0)
break;
status = write_reg(ci, 0x08, 0x28);
if (status < 0)
break;
status = write_reg(ci, 0x14, 0x20);
if (status < 0)
break;
/* CHK_ERROR(write_reg(ci, 0x09, 0x4D));*/ /* Input Mode C, BYPass Serial, TIVAL = low, MSB */ #if 0
CHK_ERROR(write_reg(ci, 0x0A, 0xA7)); /* TOSTRT = 8, Mode B (gated clock), falling Edge, Serial, POL=HIGH, MSB */ status = write_reg(ci, 0x09, 0x4D); /* Input Mode C, BYPass Serial, TIVAL = low, MSB */
if (status < 0)
break;
#endif
status = write_reg(ci, 0x0A, 0xA7); /* TOSTRT = 8, Mode B (gated clock), falling Edge, Serial, POL=HIGH, MSB */
if (status < 0)
break;
CHK_ERROR(write_reg(ci, 0x0B, 0x33)); status = write_reg(ci, 0x0B, 0x33);
CHK_ERROR(write_reg(ci, 0x0C, 0x33)); if (status < 0)
break;
status = write_reg(ci, 0x0C, 0x33);
if (status < 0)
break;
CHK_ERROR(write_regm(ci, 0x14, 0x00, 0x0F)); status = write_regm(ci, 0x14, 0x00, 0x0F);
CHK_ERROR(write_reg(ci, 0x15, ci->clk_reg_b)); if (status < 0)
CHK_ERROR(write_regm(ci, 0x16, 0x00, 0x0F)); break;
CHK_ERROR(write_reg(ci, 0x17, ci->clk_reg_f)); status = write_reg(ci, 0x15, ci->clk_reg_b);
if (status < 0)
break;
status = write_regm(ci, 0x16, 0x00, 0x0F);
if (status < 0)
break;
status = write_reg(ci, 0x17, ci->clk_reg_f);
if (status < 0)
break;
if (ci->cfg.clock_mode) { if (ci->cfg.clock_mode) {
if (ci->cfg.polarity) { if (ci->cfg.polarity) {
CHK_ERROR(write_reg(ci, 0x09, 0x6f)); status = write_reg(ci, 0x09, 0x6f);
if (status < 0)
break;
} else { } else {
CHK_ERROR(write_reg(ci, 0x09, 0x6d)); status = write_reg(ci, 0x09, 0x6d);
if (status < 0)
break;
} }
CHK_ERROR(write_reg(ci, 0x20, 0x68)); status = write_reg(ci, 0x20, 0x68);
CHK_ERROR(write_reg(ci, 0x21, 0x00)); if (status < 0)
CHK_ERROR(write_reg(ci, 0x22, 0x02)); break;
status = write_reg(ci, 0x21, 0x00);
if (status < 0)
break;
status = write_reg(ci, 0x22, 0x02);
if (status < 0)
break;
} else { } else {
if (ci->cfg.polarity) { if (ci->cfg.polarity) {
CHK_ERROR(write_reg(ci, 0x09, 0x4f)); status = write_reg(ci, 0x09, 0x4f);
if (status < 0)
break;
} else { } else {
CHK_ERROR(write_reg(ci, 0x09, 0x4d)); status = write_reg(ci, 0x09, 0x4d);
if (status < 0)
break;
} }
CHK_ERROR(write_reg(ci, 0x20, 0x28)); status = write_reg(ci, 0x20, 0x28);
CHK_ERROR(write_reg(ci, 0x21, 0x00)); if (status < 0)
CHK_ERROR(write_reg(ci, 0x22, 0x07)); break;
status = write_reg(ci, 0x21, 0x00);
if (status < 0)
break;
status = write_reg(ci, 0x22, 0x07);
if (status < 0)
break;
} }
CHK_ERROR(write_regm(ci, 0x20, 0x80, 0x80)); status = write_regm(ci, 0x20, 0x80, 0x80);
CHK_ERROR(write_regm(ci, 0x03, 0x02, 0x02)); if (status < 0)
CHK_ERROR(write_reg(ci, 0x01, 0x04)); break;
CHK_ERROR(write_reg(ci, 0x00, 0x31)); status = write_regm(ci, 0x03, 0x02, 0x02);
if (status < 0)
break;
status = write_reg(ci, 0x01, 0x04);
if (status < 0)
break;
status = write_reg(ci, 0x00, 0x31);
if (status < 0)
break;
/* Put TS in bypass */ /* Put TS in bypass */
CHK_ERROR(write_regm(ci, 0x09, 0x08, 0x08)); status = write_regm(ci, 0x09, 0x08, 0x08);
if (status < 0)
break;
ci->cammode = -1; ci->cammode = -1;
cam_mode(ci, 0); cam_mode(ci, 0);
} while (0); } while (0);