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arm64: mte: Allow user control of the generated random tags via prctl()
The IRG, ADDG and SUBG instructions insert a random tag in the resulting address. Certain tags can be excluded via the GCR_EL1.Exclude bitmap when, for example, the user wants a certain colour for freed buffers. Since the GCR_EL1 register is not accessible at EL0, extend the prctl(PR_SET_TAGGED_ADDR_CTRL) interface to include a 16-bit field in the first argument for controlling which tags can be generated by the above instruction (an include rather than exclude mask). Note that by default all non-zero tags are excluded. This setting is per-thread. Signed-off-by: Catalin Marinas <catalin.marinas@arm.com> Cc: Will Deacon <will@kernel.org>
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parent
1c101da8b9
commit
af5ce95282
5 changed files with 44 additions and 4 deletions
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@ -153,6 +153,7 @@ struct thread_struct {
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#endif
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#ifdef CONFIG_ARM64_MTE
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u64 sctlr_tcf0;
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u64 gcr_user_incl;
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#endif
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};
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@ -1078,6 +1078,13 @@
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write_sysreg(__scs_new, sysreg); \
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} while (0)
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#define sysreg_clear_set_s(sysreg, clear, set) do { \
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u64 __scs_val = read_sysreg_s(sysreg); \
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u64 __scs_new = (__scs_val & ~(u64)(clear)) | (set); \
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if (__scs_new != __scs_val) \
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write_sysreg_s(__scs_new, sysreg); \
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} while (0)
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#endif
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#endif /* __ASM_SYSREG_H */
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@ -71,6 +71,25 @@ static void set_sctlr_el1_tcf0(u64 tcf0)
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preempt_enable();
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}
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static void update_gcr_el1_excl(u64 incl)
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{
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u64 excl = ~incl & SYS_GCR_EL1_EXCL_MASK;
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/*
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* Note that 'incl' is an include mask (controlled by the user via
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* prctl()) while GCR_EL1 accepts an exclude mask.
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* No need for ISB since this only affects EL0 currently, implicit
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* with ERET.
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*/
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sysreg_clear_set_s(SYS_GCR_EL1, SYS_GCR_EL1_EXCL_MASK, excl);
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}
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static void set_gcr_el1_excl(u64 incl)
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{
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current->thread.gcr_user_incl = incl;
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update_gcr_el1_excl(incl);
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}
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void flush_mte_state(void)
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{
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if (!system_supports_mte())
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@ -82,6 +101,8 @@ void flush_mte_state(void)
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clear_thread_flag(TIF_MTE_ASYNC_FAULT);
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/* disable tag checking */
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set_sctlr_el1_tcf0(SCTLR_EL1_TCF0_NONE);
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/* reset tag generation mask */
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set_gcr_el1_excl(0);
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}
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void mte_thread_switch(struct task_struct *next)
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@ -92,6 +113,7 @@ void mte_thread_switch(struct task_struct *next)
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/* avoid expensive SCTLR_EL1 accesses if no change */
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if (current->thread.sctlr_tcf0 != next->thread.sctlr_tcf0)
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update_sctlr_el1_tcf0(next->thread.sctlr_tcf0);
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update_gcr_el1_excl(next->thread.gcr_user_incl);
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}
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long set_mte_ctrl(unsigned long arg)
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@ -116,23 +138,30 @@ long set_mte_ctrl(unsigned long arg)
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}
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set_sctlr_el1_tcf0(tcf0);
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set_gcr_el1_excl((arg & PR_MTE_TAG_MASK) >> PR_MTE_TAG_SHIFT);
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return 0;
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}
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long get_mte_ctrl(void)
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{
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unsigned long ret;
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if (!system_supports_mte())
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return 0;
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ret = current->thread.gcr_user_incl << PR_MTE_TAG_SHIFT;
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switch (current->thread.sctlr_tcf0) {
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case SCTLR_EL1_TCF0_NONE:
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return PR_MTE_TCF_NONE;
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case SCTLR_EL1_TCF0_SYNC:
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return PR_MTE_TCF_SYNC;
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ret |= PR_MTE_TCF_SYNC;
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break;
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case SCTLR_EL1_TCF0_ASYNC:
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return PR_MTE_TCF_ASYNC;
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ret |= PR_MTE_TCF_ASYNC;
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break;
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}
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return 0;
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return ret;
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}
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@ -649,7 +649,7 @@ long set_tagged_addr_ctrl(unsigned long arg)
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return -EINVAL;
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if (system_supports_mte())
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valid_mask |= PR_MTE_TCF_MASK;
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valid_mask |= PR_MTE_TCF_MASK | PR_MTE_TAG_MASK;
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if (arg & ~valid_mask)
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return -EINVAL;
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@ -239,6 +239,9 @@ struct prctl_mm_map {
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# define PR_MTE_TCF_SYNC (1UL << PR_MTE_TCF_SHIFT)
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# define PR_MTE_TCF_ASYNC (2UL << PR_MTE_TCF_SHIFT)
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# define PR_MTE_TCF_MASK (3UL << PR_MTE_TCF_SHIFT)
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/* MTE tag inclusion mask */
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# define PR_MTE_TAG_SHIFT 3
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# define PR_MTE_TAG_MASK (0xffffUL << PR_MTE_TAG_SHIFT)
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/* Control reclaim behavior when allocating memory */
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#define PR_SET_IO_FLUSHER 57
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