mirror of
https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git
synced 2024-08-21 16:29:59 +00:00
ARC: Boot #2: Verbose Boot reporting / feature verification
Signed-off-by: Vineet Gupta <vgupta@synopsys.com>
This commit is contained in:
Vineet Gupta
parent
f46121bd26
commit
af61742813
7 changed files with 490 additions and 11 deletions
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@ -20,6 +20,8 @@ export PLATFORM
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cflags-y += -Iarch/arc/plat-$(PLATFORM)/include
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cflags-y += -mA7 -fno-common -pipe -fno-builtin -D__linux__
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LINUXINCLUDE += -include ${src}/arch/arc/include/asm/defines.h
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ifdef CONFIG_ARC_CURR_IN_REG
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# For a global register defintion, make sure it gets passed to every file
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# We had a customer reported bug where some code built in kernel was NOT using
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@ -12,8 +12,26 @@
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#ifdef __KERNEL__
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/* Build Configuration Registers */
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#define ARC_REG_DCCMBASE_BCR 0x61 /* DCCM Base Addr */
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#define ARC_REG_CRC_BCR 0x62
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#define ARC_REG_DVFB_BCR 0x64
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#define ARC_REG_EXTARITH_BCR 0x65
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#define ARC_REG_VECBASE_BCR 0x68
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#define ARC_REG_PERIBASE_BCR 0x69
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#define ARC_REG_FP_BCR 0x6B /* Single-Precision FPU */
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#define ARC_REG_DPFP_BCR 0x6C /* Dbl Precision FPU */
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#define ARC_REG_MMU_BCR 0x6f
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#define ARC_REG_DCCM_BCR 0x74 /* DCCM Present + SZ */
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#define ARC_REG_TIMERS_BCR 0x75
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#define ARC_REG_ICCM_BCR 0x78
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#define ARC_REG_XY_MEM_BCR 0x79
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#define ARC_REG_MAC_BCR 0x7a
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#define ARC_REG_MUL_BCR 0x7b
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#define ARC_REG_SWAP_BCR 0x7c
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#define ARC_REG_NORM_BCR 0x7d
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#define ARC_REG_MIXMAX_BCR 0x7e
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#define ARC_REG_BARREL_BCR 0x7f
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#define ARC_REG_D_UNCACH_BCR 0x6A
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/* status32 Bits Positions */
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#define STATUS_H_BIT 0 /* CPU Halted */
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@ -88,16 +106,6 @@
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#define TIMER_CTRL_IE (1 << 0) /* Interupt when Count reachs limit */
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#define TIMER_CTRL_NH (1 << 1) /* Count only when CPU NOT halted */
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#if defined(CONFIG_ARC_MMU_V1)
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#define CONFIG_ARC_MMU_VER 1
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#elif defined(CONFIG_ARC_MMU_V2)
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#define CONFIG_ARC_MMU_VER 2
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#elif defined(CONFIG_ARC_MMU_V3)
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#define CONFIG_ARC_MMU_VER 3
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#else
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#error "Error: MMU ver"
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#endif
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/* MMU Management regs */
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#define ARC_REG_TLBPD0 0x405
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#define ARC_REG_TLBPD1 0x406
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@ -277,6 +285,13 @@ struct arc_fpu {
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***************************************************************
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* Build Configuration Registers, with encoded hardware config
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*/
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struct bcr_identity {
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#ifdef CONFIG_CPU_BIG_ENDIAN
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unsigned int chip_id:16, cpu_id:8, family:8;
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#else
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unsigned int family:8, cpu_id:8, chip_id:16;
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#endif
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};
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struct bcr_mmu_1_2 {
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#ifdef CONFIG_CPU_BIG_ENDIAN
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@ -296,6 +311,38 @@ struct bcr_mmu_3 {
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#endif
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};
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#define EXTN_SWAP_VALID 0x1
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#define EXTN_NORM_VALID 0x2
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#define EXTN_MINMAX_VALID 0x2
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#define EXTN_BARREL_VALID 0x2
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struct bcr_extn {
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#ifdef CONFIG_CPU_BIG_ENDIAN
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unsigned int pad:20, crc:1, ext_arith:2, mul:2, barrel:2, minmax:2,
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norm:2, swap:1;
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#else
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unsigned int swap:1, norm:2, minmax:2, barrel:2, mul:2, ext_arith:2,
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crc:1, pad:20;
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#endif
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};
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/* DSP Options Ref Manual */
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struct bcr_extn_mac_mul {
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#ifdef CONFIG_CPU_BIG_ENDIAN
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unsigned int pad:16, type:8, ver:8;
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#else
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unsigned int ver:8, type:8, pad:16;
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#endif
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};
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struct bcr_extn_xymem {
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#ifdef CONFIG_CPU_BIG_ENDIAN
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unsigned int ram_org:2, num_banks:4, bank_sz:4, ver:8;
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#else
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unsigned int ver:8, bank_sz:4, num_banks:4, ram_org:2;
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#endif
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};
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struct bcr_cache {
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#ifdef CONFIG_CPU_BIG_ENDIAN
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unsigned int pad:12, line_len:4, sz:4, config:4, ver:8;
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@ -304,6 +351,48 @@ struct bcr_cache {
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#endif
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};
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struct bcr_perip {
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#ifdef CONFIG_CPU_BIG_ENDIAN
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unsigned int start:8, pad2:8, sz:8, pad:8;
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#else
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unsigned int pad:8, sz:8, pad2:8, start:8;
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#endif
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};
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struct bcr_iccm {
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#ifdef CONFIG_CPU_BIG_ENDIAN
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unsigned int base:16, pad:5, sz:3, ver:8;
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#else
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unsigned int ver:8, sz:3, pad:5, base:16;
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#endif
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};
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/* DCCM Base Address Register: ARC_REG_DCCMBASE_BCR */
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struct bcr_dccm_base {
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#ifdef CONFIG_CPU_BIG_ENDIAN
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unsigned int addr:24, ver:8;
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#else
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unsigned int ver:8, addr:24;
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#endif
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};
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/* DCCM RAM Configuration Register: ARC_REG_DCCM_BCR */
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struct bcr_dccm {
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#ifdef CONFIG_CPU_BIG_ENDIAN
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unsigned int res:21, sz:3, ver:8;
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#else
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unsigned int ver:8, sz:3, res:21;
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#endif
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};
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/* Both SP and DP FPU BCRs have same format */
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struct bcr_fp {
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#ifdef CONFIG_CPU_BIG_ENDIAN
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unsigned int fast:1, ver:8;
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#else
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unsigned int ver:8, fast:1;
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#endif
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};
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/*
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*******************************************************************
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* Generic structures to hold build configuration used at runtime
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@ -317,9 +406,22 @@ struct cpuinfo_arc_cache {
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unsigned int has_aliasing, sz, line_len, assoc, ver;
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};
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struct cpuinfo_arc_ccm {
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unsigned int base_addr, sz;
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};
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struct cpuinfo_arc {
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struct cpuinfo_arc_cache icache, dcache;
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struct cpuinfo_arc_mmu mmu;
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struct bcr_identity core;
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unsigned int timers;
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unsigned int vec_base;
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unsigned int uncached_base;
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struct cpuinfo_arc_ccm iccm, dccm;
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struct bcr_extn extn;
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struct bcr_extn_xymem extn_xymem;
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struct bcr_extn_mac_mul extn_mac_mul;
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struct bcr_fp fp, dpfp;
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};
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extern struct cpuinfo_arc cpuinfo_arc700[];
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56
arch/arc/include/asm/defines.h
Normal file
56
arch/arc/include/asm/defines.h
Normal file
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@ -0,0 +1,56 @@
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/*
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* Copyright (C) 2004, 2007-2010, 2011-2012 Synopsys, Inc. (www.synopsys.com)
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#ifndef __ARC_ASM_DEFINES_H__
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#define __ARC_ASM_DEFINES_H__
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#if defined(CONFIG_ARC_MMU_V1)
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#define CONFIG_ARC_MMU_VER 1
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#elif defined(CONFIG_ARC_MMU_V2)
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#define CONFIG_ARC_MMU_VER 2
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#elif defined(CONFIG_ARC_MMU_V3)
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#define CONFIG_ARC_MMU_VER 3
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#endif
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#ifdef CONFIG_ARC_HAS_LLSC
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#define __CONFIG_ARC_HAS_LLSC_VAL 1
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#else
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#define __CONFIG_ARC_HAS_LLSC_VAL 0
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#endif
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#ifdef CONFIG_ARC_HAS_SWAPE
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#define __CONFIG_ARC_HAS_SWAPE_VAL 1
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#else
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#define __CONFIG_ARC_HAS_SWAPE_VAL 0
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#endif
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#ifdef CONFIG_ARC_HAS_RTSC
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#define __CONFIG_ARC_HAS_RTSC_VAL 1
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#else
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#define __CONFIG_ARC_HAS_RTSC_VAL 0
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#endif
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#ifdef CONFIG_ARC_MMU_SASID
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#define __CONFIG_ARC_MMU_SASID_VAL 1
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#else
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#define __CONFIG_ARC_MMU_SASID_VAL 0
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#endif
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#ifdef CONFIG_ARC_HAS_ICACHE
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#define __CONFIG_ARC_HAS_ICACHE 1
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#else
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#define __CONFIG_ARC_HAS_ICACHE 0
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#endif
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#ifdef CONFIG_ARC_HAS_DCACHE
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#define __CONFIG_ARC_HAS_DCACHE 1
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#else
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#define __CONFIG_ARC_HAS_DCACHE 0
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#endif
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#endif /* __ARC_ASM_DEFINES_H__ */
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@ -13,6 +13,20 @@
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#define COMMAND_LINE_SIZE 256
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/*
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* Data structure to map a ID to string
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* Used a lot for bootup reporting of hardware diversity
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*/
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struct id_to_str {
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int id;
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const char *str;
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};
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struct cpuinfo_data {
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struct id_to_str info;
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int up_range;
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};
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extern int root_mountflags, end_mem;
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extern int running_on_hw;
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@ -24,6 +24,7 @@
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#include <asm/arcregs.h>
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#include <asm/prom.h>
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#include <asm/unwind.h>
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#include <asm/clk.h>
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#define FIX_PTR(x) __asm__ __volatile__(";" : "+r"(x))
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@ -35,10 +36,205 @@ struct task_struct *_current_task[NR_CPUS]; /* For stack switching */
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struct cpuinfo_arc cpuinfo_arc700[NR_CPUS];
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void __init read_arc_build_cfg_regs(void)
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{
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struct bcr_perip uncached_space;
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struct cpuinfo_arc *cpu = &cpuinfo_arc700[smp_processor_id()];
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FIX_PTR(cpu);
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READ_BCR(AUX_IDENTITY, cpu->core);
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cpu->timers = read_aux_reg(ARC_REG_TIMERS_BCR);
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cpu->vec_base = read_aux_reg(AUX_INTR_VEC_BASE);
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if (cpu->vec_base == 0)
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cpu->vec_base = (unsigned int)_int_vec_base_lds;
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READ_BCR(ARC_REG_D_UNCACH_BCR, uncached_space);
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cpu->uncached_base = uncached_space.start << 24;
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cpu->extn.mul = read_aux_reg(ARC_REG_MUL_BCR);
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cpu->extn.swap = read_aux_reg(ARC_REG_SWAP_BCR);
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cpu->extn.norm = read_aux_reg(ARC_REG_NORM_BCR);
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cpu->extn.minmax = read_aux_reg(ARC_REG_MIXMAX_BCR);
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cpu->extn.barrel = read_aux_reg(ARC_REG_BARREL_BCR);
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READ_BCR(ARC_REG_MAC_BCR, cpu->extn_mac_mul);
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cpu->extn.ext_arith = read_aux_reg(ARC_REG_EXTARITH_BCR);
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cpu->extn.crc = read_aux_reg(ARC_REG_CRC_BCR);
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READ_BCR(ARC_REG_XY_MEM_BCR, cpu->extn_xymem);
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read_decode_mmu_bcr();
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read_decode_cache_bcr();
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READ_BCR(ARC_REG_FP_BCR, cpu->fp);
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READ_BCR(ARC_REG_DPFP_BCR, cpu->dpfp);
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}
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static const struct cpuinfo_data arc_cpu_tbl[] = {
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{ {0x10, "ARCTangent A5"}, 0x1F},
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{ {0x20, "ARC 600" }, 0x2F},
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{ {0x30, "ARC 700" }, 0x33},
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{ {0x34, "ARC 700 R4.10"}, 0x34},
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{ {0x00, NULL } }
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};
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char *arc_cpu_mumbojumbo(int cpu_id, char *buf, int len)
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{
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int n = 0;
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struct cpuinfo_arc *cpu = &cpuinfo_arc700[cpu_id];
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struct bcr_identity *core = &cpu->core;
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const struct cpuinfo_data *tbl;
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int be = 0;
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#ifdef CONFIG_CPU_BIG_ENDIAN
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be = 1;
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#endif
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FIX_PTR(cpu);
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n += scnprintf(buf + n, len - n,
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"\nARC IDENTITY\t: Family [%#02x]"
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" Cpu-id [%#02x] Chip-id [%#4x]\n",
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core->family, core->cpu_id,
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core->chip_id);
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for (tbl = &arc_cpu_tbl[0]; tbl->info.id != 0; tbl++) {
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if ((core->family >= tbl->info.id) &&
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(core->family <= tbl->up_range)) {
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n += scnprintf(buf + n, len - n,
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"processor\t: %s %s\n",
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tbl->info.str,
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be ? "[Big Endian]" : "");
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break;
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}
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}
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if (tbl->info.id == 0)
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n += scnprintf(buf + n, len - n, "UNKNOWN ARC Processor\n");
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n += scnprintf(buf + n, len - n, "CPU speed\t: %u.%02u Mhz\n",
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(unsigned int)(arc_get_core_freq() / 1000000),
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(unsigned int)(arc_get_core_freq() / 10000) % 100);
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n += scnprintf(buf + n, len - n, "Timers\t\t: %s %s\n",
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(cpu->timers & 0x200) ? "TIMER1" : "",
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(cpu->timers & 0x100) ? "TIMER0" : "");
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n += scnprintf(buf + n, len - n, "Vect Tbl Base\t: %#x\n",
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cpu->vec_base);
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n += scnprintf(buf + n, len - n, "UNCACHED Base\t: %#x\n",
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cpu->uncached_base);
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return buf;
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}
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static const struct id_to_str mul_type_nm[] = {
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{ 0x0, "N/A"},
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{ 0x1, "32x32 (spl Result Reg)" },
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{ 0x2, "32x32 (ANY Result Reg)" }
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};
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static const struct id_to_str mac_mul_nm[] = {
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{0x0, "N/A"},
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{0x1, "N/A"},
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{0x2, "Dual 16 x 16"},
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{0x3, "N/A"},
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{0x4, "32x16"},
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{0x5, "N/A"},
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{0x6, "Dual 16x16 and 32x16"}
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};
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char *arc_extn_mumbojumbo(int cpu_id, char *buf, int len)
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{
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int n = 0;
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struct cpuinfo_arc *cpu = &cpuinfo_arc700[cpu_id];
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FIX_PTR(cpu);
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#define IS_AVAIL1(var, str) ((var) ? str : "")
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#define IS_AVAIL2(var, str) ((var == 0x2) ? str : "")
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#define IS_USED(var) ((var) ? "(in-use)" : "(not used)")
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n += scnprintf(buf + n, len - n,
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"Extn [700-Base]\t: %s %s %s %s %s %s\n",
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IS_AVAIL2(cpu->extn.norm, "norm,"),
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IS_AVAIL2(cpu->extn.barrel, "barrel-shift,"),
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IS_AVAIL1(cpu->extn.swap, "swap,"),
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IS_AVAIL2(cpu->extn.minmax, "minmax,"),
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IS_AVAIL1(cpu->extn.crc, "crc,"),
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IS_AVAIL2(cpu->extn.ext_arith, "ext-arith"));
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n += scnprintf(buf + n, len - n, "Extn [700-MPY]\t: %s",
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mul_type_nm[cpu->extn.mul].str);
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n += scnprintf(buf + n, len - n, " MAC MPY: %s\n",
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mac_mul_nm[cpu->extn_mac_mul.type].str);
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if (cpu->core.family == 0x34) {
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n += scnprintf(buf + n, len - n,
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"Extn [700-4.10]\t: LLOCK/SCOND %s, SWAPE %s, RTSC %s\n",
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IS_USED(__CONFIG_ARC_HAS_LLSC_VAL),
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IS_USED(__CONFIG_ARC_HAS_SWAPE_VAL),
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IS_USED(__CONFIG_ARC_HAS_RTSC_VAL));
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}
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n += scnprintf(buf + n, len - n, "Extn [CCM]\t: %s",
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!(cpu->dccm.sz || cpu->iccm.sz) ? "N/A" : "");
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if (cpu->dccm.sz)
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n += scnprintf(buf + n, len - n, "DCCM: @ %x, %d KB ",
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cpu->dccm.base_addr, TO_KB(cpu->dccm.sz));
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if (cpu->iccm.sz)
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n += scnprintf(buf + n, len - n, "ICCM: @ %x, %d KB",
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cpu->iccm.base_addr, TO_KB(cpu->iccm.sz));
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n += scnprintf(buf + n, len - n, "\nExtn [FPU]\t: %s",
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!(cpu->fp.ver || cpu->dpfp.ver) ? "N/A" : "");
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|
||||
if (cpu->fp.ver)
|
||||
n += scnprintf(buf + n, len - n, "SP [v%d] %s",
|
||||
cpu->fp.ver, cpu->fp.fast ? "(fast)" : "");
|
||||
|
||||
if (cpu->dpfp.ver)
|
||||
n += scnprintf(buf + n, len - n, "DP [v%d] %s",
|
||||
cpu->dpfp.ver, cpu->dpfp.fast ? "(fast)" : "");
|
||||
|
||||
n += scnprintf(buf + n, len - n, "\n");
|
||||
|
||||
#ifdef _ASM_GENERIC_UNISTD_H
|
||||
n += scnprintf(buf + n, len - n,
|
||||
"OS ABI [v2]\t: asm-generic/{unistd,stat,fcntl}\n");
|
||||
#endif
|
||||
|
||||
return buf;
|
||||
}
|
||||
|
||||
/*
|
||||
* Ensure that FP hardware and kernel config match
|
||||
* -If hardware contains DPFP, kernel needs to save/restore FPU state
|
||||
* across context switches
|
||||
* -If hardware lacks DPFP, but kernel configured to save FPU state then
|
||||
* kernel trying to access non-existant DPFP regs will crash
|
||||
*
|
||||
* We only check for Dbl precision Floating Point, because only DPFP
|
||||
* hardware has dedicated regs which need to be saved/restored on ctx-sw
|
||||
* (Single Precision uses core regs), thus kernel is kind of oblivious to it
|
||||
*/
|
||||
void __init arc_chk_fpu(void)
|
||||
{
|
||||
struct cpuinfo_arc *cpu = &cpuinfo_arc700[smp_processor_id()];
|
||||
|
||||
if (cpu->dpfp.ver) {
|
||||
#ifndef CONFIG_ARC_FPU_SAVE_RESTORE
|
||||
pr_warn("DPFP support broken in this kernel...\n");
|
||||
#endif
|
||||
} else {
|
||||
#ifdef CONFIG_ARC_FPU_SAVE_RESTORE
|
||||
panic("H/w lacks DPFP support, apps won't work\n");
|
||||
#endif
|
||||
}
|
||||
}
|
||||
|
||||
/*
|
||||
|
|
@ -49,10 +245,25 @@ void __init read_arc_build_cfg_regs(void)
|
|||
|
||||
void __init setup_processor(void)
|
||||
{
|
||||
char str[512];
|
||||
int cpu_id = smp_processor_id();
|
||||
|
||||
read_arc_build_cfg_regs();
|
||||
arc_init_IRQ();
|
||||
|
||||
printk(arc_cpu_mumbojumbo(cpu_id, str, sizeof(str)));
|
||||
|
||||
arc_mmu_init();
|
||||
arc_cache_init();
|
||||
|
||||
|
||||
printk(arc_extn_mumbojumbo(cpu_id, str, sizeof(str)));
|
||||
|
||||
#ifdef CONFIG_SMP
|
||||
printk(arc_platform_smp_cpuinfo());
|
||||
#endif
|
||||
|
||||
arc_chk_fpu();
|
||||
}
|
||||
|
||||
void __init __attribute__((weak)) arc_platform_early_init(void)
|
||||
|
|
@ -126,12 +337,22 @@ static int show_cpuinfo(struct seq_file *m, void *v)
|
|||
if (!str)
|
||||
goto done;
|
||||
|
||||
seq_printf(m, "ARC700 #%d\n", cpu_id);
|
||||
seq_printf(m, arc_cpu_mumbojumbo(cpu_id, str, PAGE_SIZE));
|
||||
|
||||
seq_printf(m, "Bogo MIPS : \t%lu.%02lu\n",
|
||||
loops_per_jiffy / (500000 / HZ),
|
||||
(loops_per_jiffy / (5000 / HZ)) % 100);
|
||||
|
||||
seq_printf(m, arc_mmu_mumbojumbo(cpu_id, str, PAGE_SIZE));
|
||||
|
||||
seq_printf(m, arc_cache_mumbojumbo(cpu_id, str, PAGE_SIZE));
|
||||
|
||||
seq_printf(m, arc_extn_mumbojumbo(cpu_id, str, PAGE_SIZE));
|
||||
|
||||
#ifdef CONFIG_SMP
|
||||
seq_printf(m, arc_platform_smp_cpuinfo());
|
||||
#endif
|
||||
|
||||
free_page((unsigned long)str);
|
||||
done:
|
||||
seq_printf(m, "\n\n");
|
||||
|
|
|
|||
|
|
@ -82,6 +82,28 @@ static void __ic_line_inv_4_alias(unsigned long, int);
|
|||
static void (*___flush_icache_rtn) (unsigned long, int);
|
||||
#endif
|
||||
|
||||
char *arc_cache_mumbojumbo(int cpu_id, char *buf, int len)
|
||||
{
|
||||
int n = 0;
|
||||
unsigned int c = smp_processor_id();
|
||||
|
||||
#define PR_CACHE(p, enb, str) \
|
||||
{ \
|
||||
if (!(p)->ver) \
|
||||
n += scnprintf(buf + n, len - n, str"\t\t: N/A\n"); \
|
||||
else \
|
||||
n += scnprintf(buf + n, len - n, \
|
||||
str"\t\t: (%uK) VIPT, %dway set-asc, %ub Line %s\n", \
|
||||
TO_KB((p)->sz), (p)->assoc, (p)->line_len, \
|
||||
enb ? "" : "DISABLED (kernel-build)"); \
|
||||
}
|
||||
|
||||
PR_CACHE(&cpuinfo_arc700[c].icache, __CONFIG_ARC_HAS_ICACHE, "I-Cache");
|
||||
PR_CACHE(&cpuinfo_arc700[c].dcache, __CONFIG_ARC_HAS_DCACHE, "D-Cache");
|
||||
|
||||
return buf;
|
||||
}
|
||||
|
||||
/*
|
||||
* Read the Cache Build Confuration Registers, Decode them and save into
|
||||
* the cpuinfo structure for later use.
|
||||
|
|
@ -132,10 +154,29 @@ void __init arc_cache_init(void)
|
|||
struct cpuinfo_arc_cache *dc;
|
||||
#endif
|
||||
int way_pg_ratio = way_pg_ratio;
|
||||
char str[256];
|
||||
|
||||
printk(arc_cache_mumbojumbo(0, str, sizeof(str)));
|
||||
|
||||
#ifdef CONFIG_ARC_HAS_ICACHE
|
||||
ic = &cpuinfo_arc700[cpu].icache;
|
||||
|
||||
/* 1. Confirm some of I-cache params which Linux assumes */
|
||||
if ((ic->assoc != ARC_ICACHE_WAYS) ||
|
||||
(ic->line_len != ARC_ICACHE_LINE_LEN)) {
|
||||
panic("Cache H/W doesn't match kernel Config");
|
||||
}
|
||||
#if (CONFIG_ARC_MMU_VER > 2)
|
||||
if (ic->ver != 3) {
|
||||
if (running_on_hw)
|
||||
panic("Cache ver doesn't match MMU ver\n");
|
||||
|
||||
/* For ISS - suggest the toggles to use */
|
||||
pr_err("Use -prop=icache_version=3,-prop=dcache_version=3\n");
|
||||
|
||||
}
|
||||
#endif
|
||||
|
||||
/*
|
||||
* if Cache way size is <= page size then no aliasing exhibited
|
||||
* otherwise ratio determines num of aliases.
|
||||
|
|
@ -175,6 +216,11 @@ void __init arc_cache_init(void)
|
|||
#ifdef CONFIG_ARC_HAS_DCACHE
|
||||
dc = &cpuinfo_arc700[cpu].dcache;
|
||||
|
||||
if ((dc->assoc != ARC_DCACHE_WAYS) ||
|
||||
(dc->line_len != ARC_DCACHE_LINE_LEN)) {
|
||||
panic("Cache H/W doesn't match kernel Config");
|
||||
}
|
||||
|
||||
/* check for D-Cache aliasing */
|
||||
if ((dc->sz / ARC_DCACHE_WAYS) > PAGE_SIZE)
|
||||
panic("D$ aliasing not handled right now\n");
|
||||
|
|
|
|||
|
|
@ -463,8 +463,46 @@ void __init read_decode_mmu_bcr(void)
|
|||
mmu->num_tlb = mmu->sets * mmu->ways;
|
||||
}
|
||||
|
||||
char *arc_mmu_mumbojumbo(int cpu_id, char *buf, int len)
|
||||
{
|
||||
int n = 0;
|
||||
struct cpuinfo_arc_mmu *p_mmu = &cpuinfo_arc700[smp_processor_id()].mmu;
|
||||
|
||||
n += scnprintf(buf + n, len - n, "ARC700 MMU [v%x]\t: %dk PAGE, ",
|
||||
p_mmu->ver, TO_KB(p_mmu->pg_sz));
|
||||
|
||||
n += scnprintf(buf + n, len - n,
|
||||
"J-TLB %d (%dx%d), uDTLB %d, uITLB %d, %s\n",
|
||||
p_mmu->num_tlb, p_mmu->sets, p_mmu->ways,
|
||||
p_mmu->u_dtlb, p_mmu->u_itlb,
|
||||
__CONFIG_ARC_MMU_SASID_VAL ? "SASID" : "");
|
||||
|
||||
return buf;
|
||||
}
|
||||
|
||||
void __init arc_mmu_init(void)
|
||||
{
|
||||
char str[256];
|
||||
struct cpuinfo_arc_mmu *mmu = &cpuinfo_arc700[smp_processor_id()].mmu;
|
||||
|
||||
printk(arc_mmu_mumbojumbo(0, str, sizeof(str)));
|
||||
|
||||
/* For efficiency sake, kernel is compile time built for a MMU ver
|
||||
* This must match the hardware it is running on.
|
||||
* Linux built for MMU V2, if run on MMU V1 will break down because V1
|
||||
* hardware doesn't understand cmds such as WriteNI, or IVUTLB
|
||||
* On the other hand, Linux built for V1 if run on MMU V2 will do
|
||||
* un-needed workarounds to prevent memcpy thrashing.
|
||||
* Similarly MMU V3 has new features which won't work on older MMU
|
||||
*/
|
||||
if (mmu->ver != CONFIG_ARC_MMU_VER) {
|
||||
panic("MMU ver %d doesn't match kernel built for %d...\n",
|
||||
mmu->ver, CONFIG_ARC_MMU_VER);
|
||||
}
|
||||
|
||||
if (mmu->pg_sz != PAGE_SIZE)
|
||||
panic("MMU pg size != PAGE_SIZE (%luk)\n", TO_KB(PAGE_SIZE));
|
||||
|
||||
/*
|
||||
* ASID mgmt data structures are compile time init
|
||||
* asid_cache = FIRST_ASID and asid_mm_map[] all zeroes
|
||||
|
|
|
|||
Loading…
Reference in a new issue