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iwlwifi: kill bus_apm_config
This handler was called from the transport layer only. Merge it to the transport's apm_init. Signed-off-by: Emmanuel Grumbach <emmanuel.grumbach@intel.com> Signed-off-by: Wey-Yi Guy <wey-yi.w.guy@intel.com>
This commit is contained in:
parent
cf6142975b
commit
af634bee8c
3 changed files with 46 additions and 40 deletions
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@ -121,13 +121,11 @@ struct iwl_bus;
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/**
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* struct iwl_bus_ops - bus specific operations
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* @get_pm_support: must returns true if the bus can go to sleep
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* @apm_config: will be called during the config of the APM
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* @get_hw_id_string: prints the hw_id in the provided buffer
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* @get_hw_id: get hw_id in u32
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*/
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struct iwl_bus_ops {
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bool (*get_pm_support)(struct iwl_bus *bus);
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void (*apm_config)(struct iwl_bus *bus);
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void (*get_hw_id_string)(struct iwl_bus *bus, char buf[], int buf_len);
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u32 (*get_hw_id)(struct iwl_bus *bus);
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};
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@ -156,11 +154,6 @@ static inline bool bus_get_pm_support(struct iwl_bus *bus)
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return bus->ops->get_pm_support(bus);
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}
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static inline void bus_apm_config(struct iwl_bus *bus)
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{
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bus->ops->apm_config(bus);
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}
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static inline void bus_get_hw_id_string(struct iwl_bus *bus, char buf[],
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int buf_len)
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{
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@ -106,34 +106,6 @@ static bool iwl_pci_is_pm_supported(struct iwl_bus *bus)
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return !(lctl & PCI_CFG_LINK_CTRL_VAL_L0S_EN);
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}
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static void iwl_pci_apm_config(struct iwl_bus *bus)
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{
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/*
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* HW bug W/A for instability in PCIe bus L0S->L1 transition.
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* Check if BIOS (or OS) enabled L1-ASPM on this device.
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* If so (likely), disable L0S, so device moves directly L0->L1;
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* costs negligible amount of power savings.
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* If not (unlikely), enable L0S, so there is at least some
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* power savings, even without L1.
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*/
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u16 lctl = iwl_pciexp_link_ctrl(bus);
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if ((lctl & PCI_CFG_LINK_CTRL_VAL_L1_EN) ==
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PCI_CFG_LINK_CTRL_VAL_L1_EN) {
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/* L1-ASPM enabled; disable(!) L0S */
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iwl_set_bit(trans(bus), CSR_GIO_REG,
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CSR_GIO_REG_VAL_L0S_ENABLED);
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dev_printk(KERN_INFO, trans(bus)->dev,
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"L1 Enabled; Disabling L0S\n");
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} else {
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/* L1-ASPM disabled; enable(!) L0S */
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iwl_clear_bit(trans(bus), CSR_GIO_REG,
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CSR_GIO_REG_VAL_L0S_ENABLED);
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dev_printk(KERN_INFO, trans(bus)->dev,
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"L1 Disabled; Enabling L0S\n");
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}
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}
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static void iwl_pci_get_hw_id_string(struct iwl_bus *bus, char buf[],
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int buf_len)
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{
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@ -152,7 +124,6 @@ static u32 iwl_pci_get_hw_id(struct iwl_bus *bus)
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static const struct iwl_bus_ops bus_ops_pci = {
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.get_pm_support = iwl_pci_is_pm_supported,
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.apm_config = iwl_pci_apm_config,
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.get_hw_id_string = iwl_pci_get_hw_id_string,
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.get_hw_id = iwl_pci_get_hw_id,
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};
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@ -633,6 +633,51 @@ static void iwl_set_pwr_vmain(struct iwl_trans *trans)
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~APMG_PS_CTRL_MSK_PWR_SRC);
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}
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/* PCI registers */
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#define PCI_CFG_RETRY_TIMEOUT 0x041
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#define PCI_CFG_LINK_CTRL_VAL_L0S_EN 0x01
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#define PCI_CFG_LINK_CTRL_VAL_L1_EN 0x02
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static u16 iwl_pciexp_link_ctrl(struct iwl_trans *trans)
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{
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int pos;
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u16 pci_lnk_ctl;
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struct iwl_trans_pcie *trans_pcie =
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IWL_TRANS_GET_PCIE_TRANS(trans);
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struct pci_dev *pci_dev = trans_pcie->pci_dev;
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pos = pci_pcie_cap(pci_dev);
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pci_read_config_word(pci_dev, pos + PCI_EXP_LNKCTL, &pci_lnk_ctl);
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return pci_lnk_ctl;
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}
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static void iwl_apm_config(struct iwl_trans *trans)
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{
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/*
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* HW bug W/A for instability in PCIe bus L0S->L1 transition.
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* Check if BIOS (or OS) enabled L1-ASPM on this device.
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* If so (likely), disable L0S, so device moves directly L0->L1;
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* costs negligible amount of power savings.
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* If not (unlikely), enable L0S, so there is at least some
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* power savings, even without L1.
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*/
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u16 lctl = iwl_pciexp_link_ctrl(trans);
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if ((lctl & PCI_CFG_LINK_CTRL_VAL_L1_EN) ==
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PCI_CFG_LINK_CTRL_VAL_L1_EN) {
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/* L1-ASPM enabled; disable(!) L0S */
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iwl_set_bit(trans, CSR_GIO_REG, CSR_GIO_REG_VAL_L0S_ENABLED);
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dev_printk(KERN_INFO, trans->dev,
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"L1 Enabled; Disabling L0S\n");
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} else {
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/* L1-ASPM disabled; enable(!) L0S */
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iwl_clear_bit(trans, CSR_GIO_REG, CSR_GIO_REG_VAL_L0S_ENABLED);
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dev_printk(KERN_INFO, trans->dev,
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"L1 Disabled; Enabling L0S\n");
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}
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}
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/*
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* Start up NIC's basic functionality after it has been reset
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* (e.g. after platform boot, or shutdown via iwl_apm_stop())
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@ -669,7 +714,7 @@ static int iwl_apm_init(struct iwl_trans *trans)
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iwl_set_bit(trans, CSR_HW_IF_CONFIG_REG,
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CSR_HW_IF_CONFIG_REG_BIT_HAP_WAKE_L1A);
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bus_apm_config(bus(trans));
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iwl_apm_config(trans);
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/* Configure analog phase-lock-loop before activating to D0A */
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if (cfg(trans)->base_params->pll_cfg_val)
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@ -2187,9 +2232,6 @@ const struct iwl_trans_ops trans_ops_pcie = {
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.read32 = iwl_trans_pcie_read32,
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};
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/* PCI registers */
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#define PCI_CFG_RETRY_TIMEOUT 0x041
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struct iwl_trans *iwl_trans_pcie_alloc(struct iwl_shared *shrd,
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struct pci_dev *pdev,
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const struct pci_device_id *ent)
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