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RDMA/rxe: Enable MW object pool
Currently the rxe driver has a rxe_mw struct object but nothing about memory windows is enabled. This patch turns on memory windows and some minor cleanup. Set device attribute in rxe.c so max_mw = MAX_MW. Change parameters in rxe_param.h so that MAX_MW is the same as MAX_MR. Reduce the number of MRs and MWs to 4K from 256K. Add device capability bits for 2a and 2b memory windows. Removed RXE_MR_TYPE_MW from the rxe_mr_type enum. Link: https://lore.kernel.org/r/20210608042552.33275-4-rpearsonhpe@gmail.com Signed-off-by: Bob Pearson <rpearsonhpe@gmail.com> Signed-off-by: Jason Gunthorpe <jgg@nvidia.com>
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08224016ab
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3 changed files with 13 additions and 8 deletions
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@ -54,6 +54,7 @@ static void rxe_init_device_param(struct rxe_dev *rxe)
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rxe->attr.max_cq = RXE_MAX_CQ;
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rxe->attr.max_cqe = (1 << RXE_MAX_LOG_CQE) - 1;
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rxe->attr.max_mr = RXE_MAX_MR;
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rxe->attr.max_mw = RXE_MAX_MW;
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rxe->attr.max_pd = RXE_MAX_PD;
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rxe->attr.max_qp_rd_atom = RXE_MAX_QP_RD_ATOM;
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rxe->attr.max_res_rd_atom = RXE_MAX_RES_RD_ATOM;
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@ -37,7 +37,6 @@ static inline enum ib_mtu eth_mtu_int_to_enum(int mtu)
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enum rxe_device_param {
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RXE_MAX_MR_SIZE = -1ull,
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RXE_PAGE_SIZE_CAP = 0xfffff000,
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RXE_MAX_QP = 0x10000,
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RXE_MAX_QP_WR = 0x4000,
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RXE_DEVICE_CAP_FLAGS = IB_DEVICE_BAD_PKEY_CNTR
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| IB_DEVICE_BAD_QKEY_CNTR
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@ -49,7 +48,10 @@ enum rxe_device_param {
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| IB_DEVICE_RC_RNR_NAK_GEN
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| IB_DEVICE_SRQ_RESIZE
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| IB_DEVICE_MEM_MGT_EXTENSIONS
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| IB_DEVICE_ALLOW_USER_UNREG,
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| IB_DEVICE_ALLOW_USER_UNREG
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| IB_DEVICE_MEM_WINDOW
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| IB_DEVICE_MEM_WINDOW_TYPE_2A
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| IB_DEVICE_MEM_WINDOW_TYPE_2B,
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RXE_MAX_SGE = 32,
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RXE_MAX_WQE_SIZE = sizeof(struct rxe_send_wqe) +
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sizeof(struct ib_sge) * RXE_MAX_SGE,
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@ -58,7 +60,6 @@ enum rxe_device_param {
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RXE_MAX_SGE_RD = 32,
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RXE_MAX_CQ = 16384,
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RXE_MAX_LOG_CQE = 15,
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RXE_MAX_MR = 256 * 1024,
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RXE_MAX_PD = 0x7ffc,
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RXE_MAX_QP_RD_ATOM = 128,
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RXE_MAX_RES_RD_ATOM = 0x3f000,
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@ -67,7 +68,6 @@ enum rxe_device_param {
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RXE_MAX_MCAST_QP_ATTACH = 56,
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RXE_MAX_TOT_MCAST_QP_ATTACH = 0x70000,
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RXE_MAX_AH = 100,
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RXE_MAX_SRQ = 960,
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RXE_MAX_SRQ_WR = 0x4000,
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RXE_MIN_SRQ_WR = 1,
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RXE_MAX_SRQ_SGE = 27,
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@ -80,16 +80,21 @@ enum rxe_device_param {
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RXE_NUM_PORT = 1,
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RXE_MAX_QP = 0x10000,
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RXE_MIN_QP_INDEX = 16,
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RXE_MAX_QP_INDEX = 0x00020000,
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RXE_MAX_SRQ = 0x00001000,
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RXE_MIN_SRQ_INDEX = 0x00020001,
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RXE_MAX_SRQ_INDEX = 0x00040000,
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RXE_MAX_MR = 0x00001000,
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RXE_MAX_MW = 0x00001000,
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RXE_MIN_MR_INDEX = 0x00000001,
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RXE_MAX_MR_INDEX = 0x00040000,
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RXE_MIN_MW_INDEX = 0x00040001,
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RXE_MAX_MW_INDEX = 0x00060000,
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RXE_MAX_MR_INDEX = 0x00010000,
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RXE_MIN_MW_INDEX = 0x00010001,
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RXE_MAX_MW_INDEX = 0x00020000,
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RXE_MAX_PKT_PER_ACK = 64,
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RXE_MAX_UNACKED_PSNS = 128,
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@ -276,7 +276,6 @@ enum rxe_mr_type {
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RXE_MR_TYPE_NONE,
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RXE_MR_TYPE_DMA,
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RXE_MR_TYPE_MR,
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RXE_MR_TYPE_MW,
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};
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#define RXE_BUF_PER_MAP (PAGE_SIZE / sizeof(struct rxe_phys_buf))
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