mirrors/linux-stable
1
0
Fork 0
mirror of https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git synced 2024-10-28 23:24:50 +00:00
Code Issues Releases Wiki Activity

[MIPS] Malta: use tabs not spaces

Browse source 
This patch fixes all "use tabs not spaces" warnings reported by
the checkpatch.pl script on the board-specific files.

No functional changes introduced.

Signed-off-by: Dmitri Vorobiev <dmitri.vorobiev@gmail.com>
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
This commit is contained in:
Dmitri Vorobiev 2008-01-24 19:52:45 +03:00 committed by Ralf Baechle
parent a382963edc
commit af825586c0
2 changed files with 33 additions and 33 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

64
arch/mips/mips-boards/malta/malta_int.c
View file

@ -47,7 +47,7 @@ static DEFINE_SPINLOCK(mips_irq_lock);
static inline int mips_pcibios_iack(void) static inline int mips_pcibios_iack(void)
{ {
int irq; int irq;
u32 dummy; u32 dummy;
/* /*
* Determine highest priority pending interrupt by performing * Determine highest priority pending interrupt by performing
@ -58,7 +58,7 @@ static inline int mips_pcibios_iack(void)
case MIPS_REVISION_SCON_ROCIT: case MIPS_REVISION_SCON_ROCIT:
case MIPS_REVISION_SCON_SOCITSC: case MIPS_REVISION_SCON_SOCITSC:
case MIPS_REVISION_SCON_SOCITSCP: case MIPS_REVISION_SCON_SOCITSCP:
MSC_READ(MSC01_PCI_IACK, irq); MSC_READ(MSC01_PCI_IACK, irq);
irq &= 0xff; irq &= 0xff;
break; break;
case MIPS_REVISION_SCON_GT64120: case MIPS_REVISION_SCON_GT64120:
@ -123,15 +123,15 @@ static void malta_hw0_irqdispatch(void)
static void corehi_irqdispatch(void) static void corehi_irqdispatch(void)
{ {
unsigned int intedge, intsteer, pcicmd, pcibadaddr; unsigned int intedge, intsteer, pcicmd, pcibadaddr;
unsigned int pcimstat, intisr, inten, intpol; unsigned int pcimstat, intisr, inten, intpol;
unsigned int intrcause, datalo, datahi; unsigned int intrcause, datalo, datahi;
struct pt_regs *regs = get_irq_regs(); struct pt_regs *regs = get_irq_regs();
printk(KERN_EMERG "CoreHI interrupt, shouldn't happen, we die here!\n"); printk(KERN_EMERG "CoreHI interrupt, shouldn't happen, we die here!\n");
printk(KERN_EMERG "epc : %08lx\nStatus: %08lx\n" printk(KERN_EMERG "epc : %08lx\nStatus: %08lx\n"
"Cause : %08lx\nbadVaddr : %08lx\n", "Cause : %08lx\nbadVaddr : %08lx\n",
regs->cp0_epc, regs->cp0_status, regs->cp0_epc, regs->cp0_status,
regs->cp0_cause, regs->cp0_badvaddr); regs->cp0_cause, regs->cp0_badvaddr);
/* Read all the registers and then print them as there is a /* Read all the registers and then print them as there is a
problem with interspersed printk's upsetting the Bonito controller. problem with interspersed printk's upsetting the Bonito controller.
@ -139,29 +139,29 @@ static void corehi_irqdispatch(void)
*/ */
switch (mips_revision_sconid) { switch (mips_revision_sconid) {
case MIPS_REVISION_SCON_SOCIT: case MIPS_REVISION_SCON_SOCIT:
case MIPS_REVISION_SCON_ROCIT: case MIPS_REVISION_SCON_ROCIT:
case MIPS_REVISION_SCON_SOCITSC: case MIPS_REVISION_SCON_SOCITSC:
case MIPS_REVISION_SCON_SOCITSCP: case MIPS_REVISION_SCON_SOCITSCP:
ll_msc_irq(); ll_msc_irq();
break; break;
case MIPS_REVISION_SCON_GT64120: case MIPS_REVISION_SCON_GT64120:
intrcause = GT_READ(GT_INTRCAUSE_OFS); intrcause = GT_READ(GT_INTRCAUSE_OFS);
datalo = GT_READ(GT_CPUERR_ADDRLO_OFS); datalo = GT_READ(GT_CPUERR_ADDRLO_OFS);
datahi = GT_READ(GT_CPUERR_ADDRHI_OFS); datahi = GT_READ(GT_CPUERR_ADDRHI_OFS);
printk(KERN_EMERG "GT_INTRCAUSE = %08x\n", intrcause); printk(KERN_EMERG "GT_INTRCAUSE = %08x\n", intrcause);
printk(KERN_EMERG "GT_CPUERR_ADDR = %02x%08x\n", printk(KERN_EMERG "GT_CPUERR_ADDR = %02x%08x\n",
datahi, datalo); datahi, datalo);
break; break;
case MIPS_REVISION_SCON_BONITO: case MIPS_REVISION_SCON_BONITO:
pcibadaddr = BONITO_PCIBADADDR; pcibadaddr = BONITO_PCIBADADDR;
pcimstat = BONITO_PCIMSTAT; pcimstat = BONITO_PCIMSTAT;
intisr = BONITO_INTISR; intisr = BONITO_INTISR;
inten = BONITO_INTEN; inten = BONITO_INTEN;
intpol = BONITO_INTPOL; intpol = BONITO_INTPOL;
intedge = BONITO_INTEDGE; intedge = BONITO_INTEDGE;
intsteer = BONITO_INTSTEER; intsteer = BONITO_INTSTEER;
pcicmd = BONITO_PCICMD; pcicmd = BONITO_PCICMD;
printk(KERN_EMERG "BONITO_INTISR = %08x\n", intisr); printk(KERN_EMERG "BONITO_INTISR = %08x\n", intisr);
printk(KERN_EMERG "BONITO_INTEN = %08x\n", inten); printk(KERN_EMERG "BONITO_INTEN = %08x\n", inten);
printk(KERN_EMERG "BONITO_INTPOL = %08x\n", intpol); printk(KERN_EMERG "BONITO_INTPOL = %08x\n", intpol);
@ -170,11 +170,11 @@ static void corehi_irqdispatch(void)
printk(KERN_EMERG "BONITO_PCICMD = %08x\n", pcicmd); printk(KERN_EMERG "BONITO_PCICMD = %08x\n", pcicmd);
printk(KERN_EMERG "BONITO_PCIBADADDR = %08x\n", pcibadaddr); printk(KERN_EMERG "BONITO_PCIBADADDR = %08x\n", pcibadaddr);
printk(KERN_EMERG "BONITO_PCIMSTAT = %08x\n", pcimstat); printk(KERN_EMERG "BONITO_PCIMSTAT = %08x\n", pcimstat);
break; break;
} }
/* We die here*/ /* We die here*/
die("CoreHi interrupt", regs); die("CoreHi interrupt", regs);
} }
static inline int clz(unsigned long x) static inline int clz(unsigned long x)
@ -300,17 +300,17 @@ void __init arch_init_irq(void)
if (!cpu_has_veic) if (!cpu_has_veic)
mips_cpu_irq_init(); mips_cpu_irq_init();
switch(mips_revision_sconid) { switch (mips_revision_sconid) {
case MIPS_REVISION_SCON_SOCIT: case MIPS_REVISION_SCON_SOCIT:
case MIPS_REVISION_SCON_ROCIT: case MIPS_REVISION_SCON_ROCIT:
if (cpu_has_veic) if (cpu_has_veic)
init_msc_irqs(MIPS_MSC01_IC_REG_BASE, MSC01E_INT_BASE, msc_eicirqmap, msc_nr_eicirqs); init_msc_irqs(MIPS_MSC01_IC_REG_BASE, MSC01E_INT_BASE, msc_eicirqmap, msc_nr_eicirqs);
else else
init_msc_irqs(MIPS_MSC01_IC_REG_BASE, MSC01C_INT_BASE, msc_irqmap, msc_nr_irqs); init_msc_irqs(MIPS_MSC01_IC_REG_BASE, MSC01C_INT_BASE, msc_irqmap, msc_nr_irqs);
break; break;
case MIPS_REVISION_SCON_SOCITSC: case MIPS_REVISION_SCON_SOCITSC:
case MIPS_REVISION_SCON_SOCITSCP: case MIPS_REVISION_SCON_SOCITSCP:
if (cpu_has_veic) if (cpu_has_veic)
init_msc_irqs(MIPS_SOCITSC_IC_REG_BASE, MSC01E_INT_BASE, msc_eicirqmap, msc_nr_eicirqs); init_msc_irqs(MIPS_SOCITSC_IC_REG_BASE, MSC01E_INT_BASE, msc_eicirqmap, msc_nr_eicirqs);
else else

2
arch/mips/mips-boards/malta/malta_smtc.c
View file

@ -34,7 +34,7 @@ static void msmtc_send_ipi_mask(cpumask_t mask, unsigned int action)
*/ */
static void __cpuinit msmtc_init_secondary(void) static void __cpuinit msmtc_init_secondary(void)
{ {
void smtc_init_secondary(void); void smtc_init_secondary(void);
int myvpe; int myvpe;
/* Don't enable Malta I/O interrupts (IP2) for secondary VPEs */ /* Don't enable Malta I/O interrupts (IP2) for secondary VPEs */