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mmc: sdhci: add quirk SDHCI_QUIRK2_NEED_DELAY_AFTER_INT_CLK_RST
The Atmel sdhci device needs a new quirk. sdhci_set_clock set the Clock Control Register to 0 before computing the new value and writing it. It disables the internal clock which causes a reset mecanism. If we write the new value before this reset mecanism is done, it will prevent the stabilisation of the internal clock, so a delay is needed. This delay is about 2-3 cycles of the base clock. To be safe, a 1 ms delay is used. Signed-off-by: Ludovic Desroches <ludovic.desroches@atmel.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
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2 changed files with 7 additions and 0 deletions
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@ -1160,6 +1160,8 @@ void sdhci_set_clock(struct sdhci_host *host, unsigned int clock)
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host->mmc->actual_clock = 0;
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host->mmc->actual_clock = 0;
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sdhci_writew(host, 0, SDHCI_CLOCK_CONTROL);
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sdhci_writew(host, 0, SDHCI_CLOCK_CONTROL);
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if (host->quirks2 & SDHCI_QUIRK2_NEED_DELAY_AFTER_INT_CLK_RST)
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mdelay(1);
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if (clock == 0)
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if (clock == 0)
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return;
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return;
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@ -412,6 +412,11 @@ struct sdhci_host {
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#define SDHCI_QUIRK2_ACMD23_BROKEN (1<<14)
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#define SDHCI_QUIRK2_ACMD23_BROKEN (1<<14)
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/* Broken Clock divider zero in controller */
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/* Broken Clock divider zero in controller */
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#define SDHCI_QUIRK2_CLOCK_DIV_ZERO_BROKEN (1<<15)
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#define SDHCI_QUIRK2_CLOCK_DIV_ZERO_BROKEN (1<<15)
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/*
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* When internal clock is disabled, a delay is needed before modifying the
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* SD clock frequency or enabling back the internal clock.
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*/
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#define SDHCI_QUIRK2_NEED_DELAY_AFTER_INT_CLK_RST (1<<16)
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int irq; /* Device IRQ */
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int irq; /* Device IRQ */
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void __iomem *ioaddr; /* Mapped address */
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void __iomem *ioaddr; /* Mapped address */
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