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arm64: dts: qcom: Fix 'reg-names' for sdhci nodes
Since the Qualcomm sdhci-msm device-tree binding has been converted to yaml format, 'make dtbs_check' reports a number of issues with ordering of 'reg-names' as various possible combinations are possible for different qcom SoC dts files. Fix the same by updating the offending 'dts' files. Cc: Bjorn Andersson <bjorn.andersson@linaro.org> Cc: Rob Herring <robh@kernel.org> Signed-off-by: Bhupesh Sharma <bhupesh.sharma@linaro.org> Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Link: https://lore.kernel.org/r/20220514215424.1007718-6-bhupesh.sharma@linaro.org
This commit is contained in:
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4ff12270db
commit
afcbe252e9
6 changed files with 8 additions and 8 deletions
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@ -809,7 +809,7 @@ pcie_phy: phy@7786000 {
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sdcc1: mmc@7804000 {
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sdcc1: mmc@7804000 {
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compatible = "qcom,qcs404-sdhci", "qcom,sdhci-msm-v5";
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compatible = "qcom,qcs404-sdhci", "qcom,sdhci-msm-v5";
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reg = <0x07804000 0x1000>, <0x7805000 0x1000>;
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reg = <0x07804000 0x1000>, <0x7805000 0x1000>;
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reg-names = "hc", "cqhci";
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reg-names = "hc_mem", "cqe_mem";
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interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>,
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interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>;
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<GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>;
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@ -697,7 +697,7 @@ sdhc_1: mmc@7c4000 {
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compatible = "qcom,sc7180-sdhci", "qcom,sdhci-msm-v5";
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compatible = "qcom,sc7180-sdhci", "qcom,sdhci-msm-v5";
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reg = <0 0x7c4000 0 0x1000>,
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reg = <0 0x7c4000 0 0x1000>,
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<0 0x07c5000 0 0x1000>;
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<0 0x07c5000 0 0x1000>;
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reg-names = "hc", "cqhci";
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reg-names = "hc_mem", "cqe_mem";
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iommus = <&apps_smmu 0x60 0x0>;
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iommus = <&apps_smmu 0x60 0x0>;
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interrupts = <GIC_SPI 641 IRQ_TYPE_LEVEL_HIGH>,
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interrupts = <GIC_SPI 641 IRQ_TYPE_LEVEL_HIGH>,
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@ -866,7 +866,7 @@ sdhc_1: mmc@7c4000 {
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reg = <0 0x007c4000 0 0x1000>,
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reg = <0 0x007c4000 0 0x1000>,
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<0 0x007c5000 0 0x1000>;
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<0 0x007c5000 0 0x1000>;
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reg-names = "hc", "cqhci";
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reg-names = "hc_mem", "cqe_mem";
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iommus = <&apps_smmu 0xc0 0x0>;
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iommus = <&apps_smmu 0xc0 0x0>;
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interrupts = <GIC_SPI 652 IRQ_TYPE_LEVEL_HIGH>,
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interrupts = <GIC_SPI 652 IRQ_TYPE_LEVEL_HIGH>,
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@ -1280,7 +1280,7 @@ qusb2phy1: phy@c014000 {
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sdhc_2: mmc@c084000 {
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sdhc_2: mmc@c084000 {
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compatible = "qcom,sdm630-sdhci", "qcom,sdhci-msm-v5";
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compatible = "qcom,sdm630-sdhci", "qcom,sdhci-msm-v5";
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reg = <0x0c084000 0x1000>;
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reg = <0x0c084000 0x1000>;
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reg-names = "hc";
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reg-names = "hc_mem";
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interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>,
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interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH>;
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<GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH>;
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@ -1335,7 +1335,7 @@ sdhc_1: mmc@c0c4000 {
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reg = <0x0c0c4000 0x1000>,
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reg = <0x0c0c4000 0x1000>,
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<0x0c0c5000 0x1000>,
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<0x0c0c5000 0x1000>,
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<0x0c0c8000 0x8000>;
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<0x0c0c8000 0x8000>;
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reg-names = "hc", "cqhci", "ice";
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reg-names = "hc_mem", "cqe_mem", "ice_mem";
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interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,
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interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>;
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<GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>;
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@ -438,7 +438,7 @@ rpm_msg_ram: sram@45f0000 {
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sdhc_1: mmc@4744000 {
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sdhc_1: mmc@4744000 {
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compatible = "qcom,sm6125-sdhci", "qcom,sdhci-msm-v5";
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compatible = "qcom,sm6125-sdhci", "qcom,sdhci-msm-v5";
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reg = <0x04744000 0x1000>, <0x04745000 0x1000>;
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reg = <0x04744000 0x1000>, <0x04745000 0x1000>;
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reg-names = "hc", "core";
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reg-names = "hc_mem", "core_mem";
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interrupts = <GIC_SPI 348 IRQ_TYPE_LEVEL_HIGH>,
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interrupts = <GIC_SPI 348 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 352 IRQ_TYPE_LEVEL_HIGH>;
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<GIC_SPI 352 IRQ_TYPE_LEVEL_HIGH>;
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@ -459,7 +459,7 @@ sdhc_1: mmc@4744000 {
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sdhc_2: mmc@4784000 {
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sdhc_2: mmc@4784000 {
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compatible = "qcom,sm6125-sdhci", "qcom,sdhci-msm-v5";
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compatible = "qcom,sm6125-sdhci", "qcom,sdhci-msm-v5";
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reg = <0x04784000 0x1000>;
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reg = <0x04784000 0x1000>;
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reg-names = "hc";
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reg-names = "hc_mem";
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interrupts = <GIC_SPI 350 IRQ_TYPE_LEVEL_HIGH>,
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interrupts = <GIC_SPI 350 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>;
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<GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>;
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@ -477,7 +477,7 @@ sdhc_1: mmc@7c4000 {
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reg = <0 0x007c4000 0 0x1000>,
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reg = <0 0x007c4000 0 0x1000>,
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<0 0x007c5000 0 0x1000>,
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<0 0x007c5000 0 0x1000>,
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<0 0x007c8000 0 0x8000>;
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<0 0x007c8000 0 0x8000>;
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reg-names = "hc", "cqhci", "ice";
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reg-names = "hc_mem", "cqe_mem", "ice_mem";
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interrupts = <GIC_SPI 641 IRQ_TYPE_LEVEL_HIGH>,
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interrupts = <GIC_SPI 641 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 644 IRQ_TYPE_LEVEL_HIGH>;
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<GIC_SPI 644 IRQ_TYPE_LEVEL_HIGH>;
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