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ARM: 7245/1: S3C64XX: introduce arch/arm/mach-s3c64xx/common.[ch]
This patch introduces common.[ch] which are used only in the arch/arm/mach-s3c64xx/ directory. The common.c file merges the cpu.c, irq.c and irq-eint.c which are used commonly on S3C64XX SoCs and the common.h file replaces with plat/s3c6400.h and plat/s3c6410.h files. Cc: Ben Dooks <ben-linux@fluff.org> Signed-off-by: Kukjin Kim <kgene.kim@samsung.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
This commit is contained in:
parent
61b3875382
commit
b024043b6d
22 changed files with 288 additions and 342 deletions
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@ -10,54 +10,49 @@ obj-m :=
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obj-n :=
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obj- :=
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# Core files
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obj-y += cpu.o
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obj-y += clock.o
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# Core
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# Core support for S3C6400 system
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obj-y += common.o clock.o
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# Core support
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obj-$(CONFIG_CPU_S3C6400) += s3c6400.o
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obj-$(CONFIG_CPU_S3C6410) += s3c6410.o
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obj-y += irq.o
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obj-y += irq-eint.o
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# PM
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obj-$(CONFIG_PM) += pm.o irq-pm.o sleep.o
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# DMA support
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obj-$(CONFIG_S3C64XX_DMA) += dma.o
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# Device support
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obj-y += dev-uart.o
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obj-y += dev-audio.o
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obj-$(CONFIG_S3C64XX_DEV_SPI) += dev-spi.o
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# Device setup
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obj-$(CONFIG_S3C64XX_SETUP_FB_24BPP) += setup-fb-24bpp.o
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obj-$(CONFIG_S3C64XX_SETUP_I2C0) += setup-i2c0.o
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obj-$(CONFIG_S3C64XX_SETUP_I2C1) += setup-i2c1.o
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obj-$(CONFIG_S3C64XX_SETUP_IDE) += setup-ide.o
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obj-$(CONFIG_S3C64XX_SETUP_KEYPAD) += setup-keypad.o
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obj-$(CONFIG_S3C64XX_SETUP_SDHCI) += setup-sdhci.o
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obj-$(CONFIG_S3C64XX_SETUP_FB_24BPP) += setup-fb-24bpp.o
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obj-$(CONFIG_S3C64XX_SETUP_SDHCI_GPIO) += setup-sdhci-gpio.o
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# PM
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obj-$(CONFIG_PM) += pm.o
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obj-$(CONFIG_PM) += sleep.o
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obj-$(CONFIG_PM) += irq-pm.o
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# Machine support
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obj-$(CONFIG_MACH_ANW6410) += mach-anw6410.o
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obj-$(CONFIG_MACH_SMDK6400) += mach-smdk6400.o
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obj-$(CONFIG_MACH_SMDK6410) += mach-smdk6410.o
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obj-$(CONFIG_MACH_REAL6410) += mach-real6410.o
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obj-$(CONFIG_MACH_HMT) += mach-hmt.o
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obj-$(CONFIG_MACH_MINI6410) += mach-mini6410.o
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obj-$(CONFIG_MACH_NCP) += mach-ncp.o
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obj-$(CONFIG_MACH_HMT) += mach-hmt.o
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obj-$(CONFIG_MACH_REAL6410) += mach-real6410.o
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obj-$(CONFIG_MACH_SMARTQ) += mach-smartq.o
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obj-$(CONFIG_MACH_SMARTQ5) += mach-smartq5.o
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obj-$(CONFIG_MACH_SMARTQ7) += mach-smartq7.o
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obj-$(CONFIG_MACH_SMDK6400) += mach-smdk6400.o
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obj-$(CONFIG_MACH_SMDK6410) += mach-smdk6410.o
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obj-$(CONFIG_MACH_WLF_CRAGG_6410) += mach-crag6410.o mach-crag6410-module.o
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# device support
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obj-y += dev-uart.o
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obj-y += dev-audio.o
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obj-$(CONFIG_S3C64XX_DEV_SPI) += dev-spi.o
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@ -705,7 +705,7 @@ static struct clksrc_clk *init_parents[] = {
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#define GET_DIV(clk, field) ((((clk) & field##_MASK) >> field##_SHIFT) + 1)
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void __init_or_cpufreq s3c6400_setup_clocks(void)
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void __init_or_cpufreq s3c64xx_setup_clocks(void)
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{
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struct clk *xtal_clk;
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unsigned long xtal;
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@ -804,7 +804,7 @@ static struct clk *clks[] __initdata = {
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* as ARMCLK as well as the necessary parent clocks.
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*
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* This call does not setup the clocks, which is left to the
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* s3c6400_setup_clocks() call which may be needed by the cpufreq
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* s3c64xx_setup_clocks() call which may be needed by the cpufreq
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* or resume code to re-set the clocks if the bootloader has changed
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* them.
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*/
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@ -1,11 +1,13 @@
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/* arch/arm/plat-s3c64xx/irq-eint.c
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/*
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* Copyright (c) 2011 Samsung Electronics Co., Ltd.
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* http://www.samsung.com
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*
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* Copyright 2008 Openmoko, Inc.
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* Copyright 2008 Simtec Electronics
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* Ben Dooks <ben@simtec.co.uk>
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* http://armlinux.simtec.co.uk/
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*
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* S3C64XX - Interrupt handling for IRQ_EINT(x)
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* Common Codes for S3C64XX machines
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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@ -13,21 +15,182 @@
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*/
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#include <linux/kernel.h>
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#include <linux/init.h>
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#include <linux/module.h>
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#include <linux/interrupt.h>
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#include <linux/ioport.h>
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#include <linux/sysdev.h>
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#include <linux/gpio.h>
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#include <linux/irq.h>
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#include <linux/serial_core.h>
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#include <linux/platform_device.h>
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#include <linux/io.h>
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#include <linux/dma-mapping.h>
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#include <linux/irq.h>
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#include <linux/gpio.h>
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#include <asm/mach/arch.h>
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#include <asm/mach/map.h>
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#include <asm/hardware/vic.h>
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#include <plat/regs-irqtype.h>
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#include <mach/regs-gpio.h>
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#include <plat/gpio-cfg.h>
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#include <mach/map.h>
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#include <mach/hardware.h>
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#include <mach/regs-gpio.h>
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#include <plat/cpu.h>
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#include <plat/clock.h>
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#include <plat/devs.h>
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#include <plat/pm.h>
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#include <plat/gpio-cfg.h>
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#include <plat/irq-uart.h>
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#include <plat/irq-vic-timer.h>
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#include <plat/regs-irqtype.h>
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#include <plat/regs-serial.h>
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#include "common.h"
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/* uart registration process */
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void __init s3c64xx_init_uarts(struct s3c2410_uartcfg *cfg, int no)
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{
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s3c24xx_init_uartdevs("s3c6400-uart", s3c64xx_uart_resources, cfg, no);
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}
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/* table of supported CPUs */
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static const char name_s3c6400[] = "S3C6400";
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static const char name_s3c6410[] = "S3C6410";
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static struct cpu_table cpu_ids[] __initdata = {
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{
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.idcode = S3C6400_CPU_ID,
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.idmask = S3C64XX_CPU_MASK,
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.map_io = s3c6400_map_io,
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.init_clocks = s3c6400_init_clocks,
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.init_uarts = s3c64xx_init_uarts,
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.init = s3c6400_init,
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.name = name_s3c6400,
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}, {
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.idcode = S3C6410_CPU_ID,
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.idmask = S3C64XX_CPU_MASK,
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.map_io = s3c6410_map_io,
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.init_clocks = s3c6410_init_clocks,
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.init_uarts = s3c64xx_init_uarts,
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.init = s3c6410_init,
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.name = name_s3c6410,
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},
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};
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/* minimal IO mapping */
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/* see notes on uart map in arch/arm/mach-s3c64xx/include/mach/debug-macro.S */
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#define UART_OFFS (S3C_PA_UART & 0xfffff)
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static struct map_desc s3c_iodesc[] __initdata = {
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{
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.virtual = (unsigned long)S3C_VA_SYS,
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.pfn = __phys_to_pfn(S3C64XX_PA_SYSCON),
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.length = SZ_4K,
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.type = MT_DEVICE,
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}, {
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.virtual = (unsigned long)S3C_VA_MEM,
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.pfn = __phys_to_pfn(S3C64XX_PA_SROM),
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.length = SZ_4K,
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.type = MT_DEVICE,
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}, {
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.virtual = (unsigned long)(S3C_VA_UART + UART_OFFS),
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.pfn = __phys_to_pfn(S3C_PA_UART),
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.length = SZ_4K,
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.type = MT_DEVICE,
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}, {
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.virtual = (unsigned long)VA_VIC0,
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.pfn = __phys_to_pfn(S3C64XX_PA_VIC0),
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.length = SZ_16K,
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.type = MT_DEVICE,
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}, {
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.virtual = (unsigned long)VA_VIC1,
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.pfn = __phys_to_pfn(S3C64XX_PA_VIC1),
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.length = SZ_16K,
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.type = MT_DEVICE,
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}, {
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.virtual = (unsigned long)S3C_VA_TIMER,
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.pfn = __phys_to_pfn(S3C_PA_TIMER),
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.length = SZ_16K,
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.type = MT_DEVICE,
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}, {
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.virtual = (unsigned long)S3C64XX_VA_GPIO,
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.pfn = __phys_to_pfn(S3C64XX_PA_GPIO),
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.length = SZ_4K,
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.type = MT_DEVICE,
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}, {
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.virtual = (unsigned long)S3C64XX_VA_MODEM,
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.pfn = __phys_to_pfn(S3C64XX_PA_MODEM),
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.length = SZ_4K,
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.type = MT_DEVICE,
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}, {
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.virtual = (unsigned long)S3C_VA_WATCHDOG,
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.pfn = __phys_to_pfn(S3C64XX_PA_WATCHDOG),
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.length = SZ_4K,
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.type = MT_DEVICE,
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}, {
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.virtual = (unsigned long)S3C_VA_USB_HSPHY,
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.pfn = __phys_to_pfn(S3C64XX_PA_USB_HSPHY),
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.length = SZ_1K,
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.type = MT_DEVICE,
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},
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};
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struct sysdev_class s3c64xx_sysclass = {
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.name = "s3c64xx-core",
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};
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static struct sys_device s3c64xx_sysdev = {
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.cls = &s3c64xx_sysclass,
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};
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/* read cpu identification code */
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void __init s3c64xx_init_io(struct map_desc *mach_desc, int size)
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{
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/* initialise the io descriptors we need for initialisation */
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iotable_init(s3c_iodesc, ARRAY_SIZE(s3c_iodesc));
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iotable_init(mach_desc, size);
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init_consistent_dma_size(SZ_8M);
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/* detect cpu id */
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s3c64xx_init_cpu();
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s3c_init_cpu(samsung_cpu_id, cpu_ids, ARRAY_SIZE(cpu_ids));
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}
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static __init int s3c64xx_sysdev_init(void)
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{
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sysdev_class_register(&s3c64xx_sysclass);
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return sysdev_register(&s3c64xx_sysdev);
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}
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core_initcall(s3c64xx_sysdev_init);
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/*
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* setup the sources the vic should advertise resume
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* for, even though it is not doing the wake
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* (set_irq_wake needs to be valid)
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*/
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#define IRQ_VIC0_RESUME (1 << (IRQ_RTC_TIC - IRQ_VIC0_BASE))
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#define IRQ_VIC1_RESUME (1 << (IRQ_RTC_ALARM - IRQ_VIC1_BASE) | \
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1 << (IRQ_PENDN - IRQ_VIC1_BASE) | \
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1 << (IRQ_HSMMC0 - IRQ_VIC1_BASE) | \
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1 << (IRQ_HSMMC1 - IRQ_VIC1_BASE) | \
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1 << (IRQ_HSMMC2 - IRQ_VIC1_BASE))
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void __init s3c64xx_init_irq(u32 vic0_valid, u32 vic1_valid)
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{
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printk(KERN_DEBUG "%s: initialising interrupts\n", __func__);
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/* initialise the pair of VICs */
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vic_init(VA_VIC0, IRQ_VIC0_BASE, vic0_valid, IRQ_VIC0_RESUME);
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vic_init(VA_VIC1, IRQ_VIC1_BASE, vic1_valid, IRQ_VIC1_RESUME);
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/* add the timer sub-irqs */
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s3c_init_vic_timer_irq(5, IRQ_TIMER0);
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}
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#define eint_offset(irq) ((irq) - IRQ_EINT(0))
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#define eint_irq_to_bit(irq) ((u32)(1 << eint_offset(irq)))
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@ -209,5 +372,4 @@ static int __init s3c64xx_init_irq_eint(void)
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return 0;
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}
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arch_initcall(s3c64xx_init_irq_eint);
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55
arch/arm/mach-s3c64xx/common.h
Normal file
55
arch/arm/mach-s3c64xx/common.h
Normal file
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@ -0,0 +1,55 @@
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/*
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* Copyright (c) 2011 Samsung Electronics Co., Ltd.
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* http://www.samsung.com
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*
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* Copyright 2008 Openmoko, Inc.
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* Copyright 2008 Simtec Electronics
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* Ben Dooks <ben@simtec.co.uk>
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* http://armlinux.simtec.co.uk/
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*
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* Common Header for S3C64XX machines
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#ifndef __ARCH_ARM_MACH_S3C64XX_COMMON_H
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#define __ARCH_ARM_MACH_S3C64XX_COMMON_H
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void s3c64xx_init_irq(u32 vic0, u32 vic1);
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void s3c64xx_init_io(struct map_desc *mach_desc, int size);
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void s3c64xx_register_clocks(unsigned long xtal, unsigned armclk_limit);
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void s3c64xx_setup_clocks(void);
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extern struct syscore_ops s3c64xx_irq_syscore_ops;
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extern struct sysdev_class s3c64xx_sysclass;
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#ifdef CONFIG_CPU_S3C6400
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extern int s3c6400_init(void);
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extern void s3c6400_init_irq(void);
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extern void s3c6400_map_io(void);
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extern void s3c6400_init_clocks(int xtal);
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#else
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#define s3c6400_init_clocks NULL
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#define s3c6400_map_io NULL
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#define s3c6400_init NULL
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#endif
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#ifdef CONFIG_CPU_S3C6410
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extern int s3c6410_init(void);
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extern void s3c6410_init_irq(void);
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extern void s3c6410_map_io(void);
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extern void s3c6410_init_clocks(int xtal);
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#else
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#define s3c6410_init_clocks NULL
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#define s3c6410_map_io NULL
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#define s3c6410_init NULL
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#endif
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#endif /* __ARCH_ARM_MACH_S3C64XX_COMMON_H */
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@ -1,161 +0,0 @@
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/* linux/arch/arm/plat-s3c64xx/cpu.c
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*
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* Copyright 2008 Openmoko, Inc.
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* Copyright 2008 Simtec Electronics
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* Ben Dooks <ben@simtec.co.uk>
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* http://armlinux.simtec.co.uk/
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*
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* S3C64XX CPU Support
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#include <linux/init.h>
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#include <linux/module.h>
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#include <linux/interrupt.h>
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#include <linux/ioport.h>
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#include <linux/sysdev.h>
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#include <linux/serial_core.h>
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#include <linux/platform_device.h>
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#include <linux/io.h>
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#include <linux/dma-mapping.h>
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#include <mach/hardware.h>
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#include <mach/map.h>
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#include <asm/mach/arch.h>
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#include <asm/mach/map.h>
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#include <plat/regs-serial.h>
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#include <plat/cpu.h>
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#include <plat/devs.h>
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#include <plat/clock.h>
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#include <plat/s3c6400.h>
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#include <plat/s3c6410.h>
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/* table of supported CPUs */
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static const char name_s3c6400[] = "S3C6400";
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static const char name_s3c6410[] = "S3C6410";
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static struct cpu_table cpu_ids[] __initdata = {
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{
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.idcode = S3C6400_CPU_ID,
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.idmask = S3C64XX_CPU_MASK,
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.map_io = s3c6400_map_io,
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.init_clocks = s3c6400_init_clocks,
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.init_uarts = s3c6400_init_uarts,
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.init = s3c6400_init,
|
||||
.name = name_s3c6400,
|
||||
}, {
|
||||
.idcode = S3C6410_CPU_ID,
|
||||
.idmask = S3C64XX_CPU_MASK,
|
||||
.map_io = s3c6410_map_io,
|
||||
.init_clocks = s3c6410_init_clocks,
|
||||
.init_uarts = s3c6410_init_uarts,
|
||||
.init = s3c6410_init,
|
||||
.name = name_s3c6410,
|
||||
},
|
||||
};
|
||||
|
||||
/* minimal IO mapping */
|
||||
|
||||
/* see notes on uart map in arch/arm/mach-s3c6400/include/mach/debug-macro.S */
|
||||
#define UART_OFFS (S3C_PA_UART & 0xfffff)
|
||||
|
||||
static struct map_desc s3c_iodesc[] __initdata = {
|
||||
{
|
||||
.virtual = (unsigned long)S3C_VA_SYS,
|
||||
.pfn = __phys_to_pfn(S3C64XX_PA_SYSCON),
|
||||
.length = SZ_4K,
|
||||
.type = MT_DEVICE,
|
||||
}, {
|
||||
.virtual = (unsigned long)S3C_VA_MEM,
|
||||
.pfn = __phys_to_pfn(S3C64XX_PA_SROM),
|
||||
.length = SZ_4K,
|
||||
.type = MT_DEVICE,
|
||||
}, {
|
||||
.virtual = (unsigned long)(S3C_VA_UART + UART_OFFS),
|
||||
.pfn = __phys_to_pfn(S3C_PA_UART),
|
||||
.length = SZ_4K,
|
||||
.type = MT_DEVICE,
|
||||
}, {
|
||||
.virtual = (unsigned long)VA_VIC0,
|
||||
.pfn = __phys_to_pfn(S3C64XX_PA_VIC0),
|
||||
.length = SZ_16K,
|
||||
.type = MT_DEVICE,
|
||||
}, {
|
||||
.virtual = (unsigned long)VA_VIC1,
|
||||
.pfn = __phys_to_pfn(S3C64XX_PA_VIC1),
|
||||
.length = SZ_16K,
|
||||
.type = MT_DEVICE,
|
||||
}, {
|
||||
.virtual = (unsigned long)S3C_VA_TIMER,
|
||||
.pfn = __phys_to_pfn(S3C_PA_TIMER),
|
||||
.length = SZ_16K,
|
||||
.type = MT_DEVICE,
|
||||
}, {
|
||||
.virtual = (unsigned long)S3C64XX_VA_GPIO,
|
||||
.pfn = __phys_to_pfn(S3C64XX_PA_GPIO),
|
||||
.length = SZ_4K,
|
||||
.type = MT_DEVICE,
|
||||
}, {
|
||||
.virtual = (unsigned long)S3C64XX_VA_MODEM,
|
||||
.pfn = __phys_to_pfn(S3C64XX_PA_MODEM),
|
||||
.length = SZ_4K,
|
||||
.type = MT_DEVICE,
|
||||
}, {
|
||||
.virtual = (unsigned long)S3C_VA_WATCHDOG,
|
||||
.pfn = __phys_to_pfn(S3C64XX_PA_WATCHDOG),
|
||||
.length = SZ_4K,
|
||||
.type = MT_DEVICE,
|
||||
}, {
|
||||
.virtual = (unsigned long)S3C_VA_USB_HSPHY,
|
||||
.pfn = __phys_to_pfn(S3C64XX_PA_USB_HSPHY),
|
||||
.length = SZ_1K,
|
||||
.type = MT_DEVICE,
|
||||
},
|
||||
};
|
||||
|
||||
|
||||
struct sysdev_class s3c64xx_sysclass = {
|
||||
.name = "s3c64xx-core",
|
||||
};
|
||||
|
||||
static struct sys_device s3c64xx_sysdev = {
|
||||
.cls = &s3c64xx_sysclass,
|
||||
};
|
||||
|
||||
/* uart registration process */
|
||||
|
||||
void __init s3c6400_common_init_uarts(struct s3c2410_uartcfg *cfg, int no)
|
||||
{
|
||||
s3c24xx_init_uartdevs("s3c6400-uart", s3c64xx_uart_resources, cfg, no);
|
||||
}
|
||||
|
||||
/* read cpu identification code */
|
||||
|
||||
void __init s3c64xx_init_io(struct map_desc *mach_desc, int size)
|
||||
{
|
||||
/* initialise the io descriptors we need for initialisation */
|
||||
iotable_init(s3c_iodesc, ARRAY_SIZE(s3c_iodesc));
|
||||
iotable_init(mach_desc, size);
|
||||
init_consistent_dma_size(SZ_8M);
|
||||
|
||||
/* detect cpu id */
|
||||
s3c64xx_init_cpu();
|
||||
|
||||
s3c_init_cpu(samsung_cpu_id, cpu_ids, ARRAY_SIZE(cpu_ids));
|
||||
}
|
||||
|
||||
static __init int s3c64xx_sysdev_init(void)
|
||||
{
|
||||
sysdev_class_register(&s3c64xx_sysclass);
|
||||
return sysdev_register(&s3c64xx_sysdev);
|
||||
}
|
||||
|
||||
core_initcall(s3c64xx_sysdev_init);
|
|
@ -1,47 +0,0 @@
|
|||
/* arch/arm/plat-s3c64xx/irq.c
|
||||
*
|
||||
* Copyright 2008 Openmoko, Inc.
|
||||
* Copyright 2008 Simtec Electronics
|
||||
* Ben Dooks <ben@simtec.co.uk>
|
||||
* http://armlinux.simtec.co.uk/
|
||||
*
|
||||
* S3C64XX - Interrupt handling
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License version 2 as
|
||||
* published by the Free Software Foundation.
|
||||
*/
|
||||
|
||||
#include <linux/kernel.h>
|
||||
#include <linux/interrupt.h>
|
||||
#include <linux/serial_core.h>
|
||||
#include <linux/irq.h>
|
||||
#include <linux/io.h>
|
||||
|
||||
#include <asm/hardware/vic.h>
|
||||
|
||||
#include <mach/map.h>
|
||||
#include <plat/irq-vic-timer.h>
|
||||
#include <plat/irq-uart.h>
|
||||
#include <plat/cpu.h>
|
||||
|
||||
/* setup the sources the vic should advertise resume for, even though it
|
||||
* is not doing the wake (set_irq_wake needs to be valid) */
|
||||
#define IRQ_VIC0_RESUME (1 << (IRQ_RTC_TIC - IRQ_VIC0_BASE))
|
||||
#define IRQ_VIC1_RESUME (1 << (IRQ_RTC_ALARM - IRQ_VIC1_BASE) | \
|
||||
1 << (IRQ_PENDN - IRQ_VIC1_BASE) | \
|
||||
1 << (IRQ_HSMMC0 - IRQ_VIC1_BASE) | \
|
||||
1 << (IRQ_HSMMC1 - IRQ_VIC1_BASE) | \
|
||||
1 << (IRQ_HSMMC2 - IRQ_VIC1_BASE))
|
||||
|
||||
void __init s3c64xx_init_irq(u32 vic0_valid, u32 vic1_valid)
|
||||
{
|
||||
printk(KERN_DEBUG "%s: initialising interrupts\n", __func__);
|
||||
|
||||
/* initialise the pair of VICs */
|
||||
vic_init(VA_VIC0, IRQ_VIC0_BASE, vic0_valid, IRQ_VIC0_RESUME);
|
||||
vic_init(VA_VIC1, IRQ_VIC1_BASE, vic1_valid, IRQ_VIC1_RESUME);
|
||||
|
||||
/* add the timer sub-irqs */
|
||||
s3c_init_vic_timer_irq(5, IRQ_TIMER0);
|
||||
}
|
|
@ -45,13 +45,14 @@
|
|||
#include <plat/fb.h>
|
||||
#include <plat/regs-fb-v4.h>
|
||||
|
||||
#include <plat/s3c6410.h>
|
||||
#include <plat/clock.h>
|
||||
#include <plat/devs.h>
|
||||
#include <plat/cpu.h>
|
||||
#include <mach/regs-gpio.h>
|
||||
#include <mach/regs-modem.h>
|
||||
|
||||
#include "common.h"
|
||||
|
||||
/* DM9000 */
|
||||
#define ANW6410_PA_DM9000 (0x18000000)
|
||||
|
||||
|
|
|
@ -50,7 +50,6 @@
|
|||
|
||||
#include <mach/regs-gpio-memport.h>
|
||||
|
||||
#include <plat/s3c6410.h>
|
||||
#include <plat/regs-serial.h>
|
||||
#include <plat/regs-fb-v4.h>
|
||||
#include <plat/fb.h>
|
||||
|
@ -66,6 +65,8 @@
|
|||
#include <plat/iic.h>
|
||||
#include <plat/pm.h>
|
||||
|
||||
#include "common.h"
|
||||
|
||||
/* serial port setup */
|
||||
|
||||
#define UCON (S3C2410_UCON_DEFAULT | S3C2410_UCON_UCLK)
|
||||
|
|
|
@ -37,12 +37,13 @@
|
|||
#include <plat/fb.h>
|
||||
#include <plat/nand.h>
|
||||
|
||||
#include <plat/s3c6410.h>
|
||||
#include <plat/clock.h>
|
||||
#include <plat/devs.h>
|
||||
#include <plat/cpu.h>
|
||||
#include <plat/regs-fb-v4.h>
|
||||
|
||||
#include "common.h"
|
||||
|
||||
#define UCON S3C2410_UCON_DEFAULT
|
||||
#define ULCON (S3C2410_LCON_CS8 | S3C2410_LCON_PNONE)
|
||||
#define UFCON (S3C2410_UFCON_RXTRIG8 | S3C2410_UFCON_FIFOMODE)
|
||||
|
|
|
@ -33,7 +33,6 @@
|
|||
#include <mach/regs-modem.h>
|
||||
#include <mach/regs-srom.h>
|
||||
|
||||
#include <plat/s3c6410.h>
|
||||
#include <plat/adc.h>
|
||||
#include <plat/cpu.h>
|
||||
#include <plat/devs.h>
|
||||
|
@ -45,6 +44,8 @@
|
|||
|
||||
#include <video/platform_lcd.h>
|
||||
|
||||
#include "common.h"
|
||||
|
||||
#define UCON S3C2410_UCON_DEFAULT
|
||||
#define ULCON (S3C2410_LCON_CS8 | S3C2410_LCON_PNONE | S3C2410_LCON_STOPB)
|
||||
#define UFCON (S3C2410_UFCON_RXTRIG8 | S3C2410_UFCON_FIFOMODE)
|
||||
|
|
|
@ -39,12 +39,13 @@
|
|||
#include <plat/iic.h>
|
||||
#include <plat/fb.h>
|
||||
|
||||
#include <plat/s3c6410.h>
|
||||
#include <plat/clock.h>
|
||||
#include <plat/devs.h>
|
||||
#include <plat/cpu.h>
|
||||
#include <plat/regs-fb-v4.h>
|
||||
|
||||
#include "common.h"
|
||||
|
||||
#define UCON S3C2410_UCON_DEFAULT
|
||||
#define ULCON S3C2410_LCON_CS8 | S3C2410_LCON_PNONE
|
||||
#define UFCON S3C2410_UFCON_RXTRIG8 | S3C2410_UFCON_FIFOMODE
|
||||
|
|
|
@ -34,7 +34,6 @@
|
|||
#include <mach/regs-modem.h>
|
||||
#include <mach/regs-srom.h>
|
||||
|
||||
#include <plat/s3c6410.h>
|
||||
#include <plat/adc.h>
|
||||
#include <plat/cpu.h>
|
||||
#include <plat/devs.h>
|
||||
|
@ -46,6 +45,8 @@
|
|||
|
||||
#include <video/platform_lcd.h>
|
||||
|
||||
#include "common.h"
|
||||
|
||||
#define UCON S3C2410_UCON_DEFAULT
|
||||
#define ULCON (S3C2410_LCON_CS8 | S3C2410_LCON_PNONE | S3C2410_LCON_STOPB)
|
||||
#define UFCON (S3C2410_UFCON_RXTRIG8 | S3C2410_UFCON_FIFOMODE)
|
||||
|
|
|
@ -40,6 +40,8 @@
|
|||
|
||||
#include <video/platform_lcd.h>
|
||||
|
||||
#include "common.h"
|
||||
|
||||
#define UCON S3C2410_UCON_DEFAULT
|
||||
#define ULCON (S3C2410_LCON_CS8 | S3C2410_LCON_PNONE)
|
||||
#define UFCON (S3C2410_UFCON_RXTRIG8 | S3C2410_UFCON_FIFOMODE)
|
||||
|
|
|
@ -23,13 +23,13 @@
|
|||
#include <mach/map.h>
|
||||
#include <mach/regs-gpio.h>
|
||||
|
||||
#include <plat/s3c6410.h>
|
||||
#include <plat/cpu.h>
|
||||
#include <plat/devs.h>
|
||||
#include <plat/fb.h>
|
||||
#include <plat/gpio-cfg.h>
|
||||
#include <plat/regs-fb-v4.h>
|
||||
|
||||
#include "common.h"
|
||||
#include "mach-smartq.h"
|
||||
|
||||
static struct gpio_led smartq5_leds[] = {
|
||||
|
|
|
@ -23,13 +23,13 @@
|
|||
#include <mach/map.h>
|
||||
#include <mach/regs-gpio.h>
|
||||
|
||||
#include <plat/s3c6410.h>
|
||||
#include <plat/cpu.h>
|
||||
#include <plat/devs.h>
|
||||
#include <plat/fb.h>
|
||||
#include <plat/gpio-cfg.h>
|
||||
#include <plat/regs-fb-v4.h>
|
||||
|
||||
#include "common.h"
|
||||
#include "mach-smartq.h"
|
||||
|
||||
static struct gpio_led smartq7_leds[] = {
|
||||
|
|
|
@ -31,12 +31,13 @@
|
|||
|
||||
#include <plat/regs-serial.h>
|
||||
|
||||
#include <plat/s3c6400.h>
|
||||
#include <plat/clock.h>
|
||||
#include <plat/devs.h>
|
||||
#include <plat/cpu.h>
|
||||
#include <plat/iic.h>
|
||||
|
||||
#include "common.h"
|
||||
|
||||
#define UCON S3C2410_UCON_DEFAULT | S3C2410_UCON_UCLK
|
||||
#define ULCON S3C2410_LCON_CS8 | S3C2410_LCON_PNONE | S3C2410_LCON_STOPB
|
||||
#define UFCON S3C2410_UFCON_RXTRIG8 | S3C2410_UFCON_FIFOMODE
|
||||
|
|
|
@ -63,7 +63,6 @@
|
|||
#include <plat/fb.h>
|
||||
#include <plat/gpio-cfg.h>
|
||||
|
||||
#include <plat/s3c6410.h>
|
||||
#include <plat/clock.h>
|
||||
#include <plat/devs.h>
|
||||
#include <plat/cpu.h>
|
||||
|
@ -73,6 +72,8 @@
|
|||
#include <plat/backlight.h>
|
||||
#include <plat/regs-fb-v4.h>
|
||||
|
||||
#include "common.h"
|
||||
|
||||
#define UCON S3C2410_UCON_DEFAULT | S3C2410_UCON_UCLK
|
||||
#define ULCON S3C2410_LCON_CS8 | S3C2410_LCON_PNONE | S3C2410_LCON_STOPB
|
||||
#define UFCON S3C2410_UFCON_RXTRIG8 | S3C2410_UFCON_FIFOMODE
|
||||
|
|
|
@ -38,7 +38,8 @@
|
|||
#include <plat/sdhci.h>
|
||||
#include <plat/iic-core.h>
|
||||
#include <plat/onenand-core.h>
|
||||
#include <plat/s3c6400.h>
|
||||
|
||||
#include "common.h"
|
||||
|
||||
void __init s3c6400_map_io(void)
|
||||
{
|
||||
|
@ -60,7 +61,7 @@ void __init s3c6400_map_io(void)
|
|||
void __init s3c6400_init_clocks(int xtal)
|
||||
{
|
||||
s3c64xx_register_clocks(xtal, S3C6400_CLKDIV0_ARM_MASK);
|
||||
s3c6400_setup_clocks();
|
||||
s3c64xx_setup_clocks();
|
||||
}
|
||||
|
||||
void __init s3c6400_init_irq(void)
|
||||
|
|
|
@ -41,8 +41,8 @@
|
|||
#include <plat/adc-core.h>
|
||||
#include <plat/iic-core.h>
|
||||
#include <plat/onenand-core.h>
|
||||
#include <plat/s3c6400.h>
|
||||
#include <plat/s3c6410.h>
|
||||
|
||||
#include "common.h"
|
||||
|
||||
void __init s3c6410_map_io(void)
|
||||
{
|
||||
|
@ -66,7 +66,7 @@ void __init s3c6410_init_clocks(int xtal)
|
|||
{
|
||||
printk(KERN_DEBUG "%s: initialising clocks\n", __func__);
|
||||
s3c64xx_register_clocks(xtal, S3C6410_CLKDIV0_ARM_MASK);
|
||||
s3c6400_setup_clocks();
|
||||
s3c64xx_setup_clocks();
|
||||
}
|
||||
|
||||
void __init s3c6410_init_irq(void)
|
||||
|
|
|
@ -152,11 +152,9 @@ extern void s3c_init_cpu(unsigned long idcode,
|
|||
/* core initialisation functions */
|
||||
|
||||
extern void s3c24xx_init_irq(void);
|
||||
extern void s3c64xx_init_irq(u32 vic0, u32 vic1);
|
||||
extern void s5p_init_irq(u32 *vic, u32 num_vic);
|
||||
|
||||
extern void s3c24xx_init_io(struct map_desc *mach_desc, int size);
|
||||
extern void s3c64xx_init_io(struct map_desc *mach_desc, int size);
|
||||
extern void s5p_init_io(struct map_desc *mach_desc,
|
||||
int size, void __iomem *cpuid_addr);
|
||||
|
||||
|
@ -183,7 +181,6 @@ extern struct syscore_ops s3c2410_pm_syscore_ops;
|
|||
extern struct syscore_ops s3c2412_pm_syscore_ops;
|
||||
extern struct syscore_ops s3c2416_pm_syscore_ops;
|
||||
extern struct syscore_ops s3c244x_pm_syscore_ops;
|
||||
extern struct syscore_ops s3c64xx_irq_syscore_ops;
|
||||
|
||||
/* system device classes */
|
||||
|
||||
|
@ -195,7 +192,6 @@ extern struct sysdev_class s3c2440_sysclass;
|
|||
extern struct sysdev_class s3c2442_sysclass;
|
||||
extern struct sysdev_class s3c2443_sysclass;
|
||||
extern struct sysdev_class s3c6410_sysclass;
|
||||
extern struct sysdev_class s3c64xx_sysclass;
|
||||
extern struct sysdev_class s5p64x0_sysclass;
|
||||
extern struct sysdev_class s5pv210_sysclass;
|
||||
extern struct sysdev_class exynos4_sysclass;
|
||||
|
|
|
@ -1,36 +0,0 @@
|
|||
/* linux/arch/arm/plat-samsung/include/plat/s3c6400.h
|
||||
*
|
||||
* Copyright 2008 Openmoko, Inc.
|
||||
* Copyright 2008 Simtec Electronics
|
||||
* Ben Dooks <ben@simtec.co.uk>
|
||||
* http://armlinux.simtec.co.uk/
|
||||
*
|
||||
* Header file for s3c6400 cpu support
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License version 2 as
|
||||
* published by the Free Software Foundation.
|
||||
*/
|
||||
|
||||
/* Common init code for S3C6400 related SoCs */
|
||||
|
||||
extern void s3c6400_common_init_uarts(struct s3c2410_uartcfg *cfg, int no);
|
||||
extern void s3c6400_setup_clocks(void);
|
||||
|
||||
extern void s3c64xx_register_clocks(unsigned long xtal, unsigned armclk_limit);
|
||||
|
||||
#ifdef CONFIG_CPU_S3C6400
|
||||
|
||||
extern int s3c6400_init(void);
|
||||
extern void s3c6400_init_irq(void);
|
||||
extern void s3c6400_map_io(void);
|
||||
extern void s3c6400_init_clocks(int xtal);
|
||||
|
||||
#define s3c6400_init_uarts s3c6400_common_init_uarts
|
||||
|
||||
#else
|
||||
#define s3c6400_init_clocks NULL
|
||||
#define s3c6400_init_uarts NULL
|
||||
#define s3c6400_map_io NULL
|
||||
#define s3c6400_init NULL
|
||||
#endif
|
|
@ -1,29 +0,0 @@
|
|||
/* linux/arch/arm/plat-samsung/include/plat/s3c6410.h
|
||||
*
|
||||
* Copyright 2008 Openmoko, Inc.
|
||||
* Copyright 2008 Simtec Electronics
|
||||
* Ben Dooks <ben@simtec.co.uk>
|
||||
* http://armlinux.simtec.co.uk/
|
||||
*
|
||||
* Header file for s3c6410 cpu support
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License version 2 as
|
||||
* published by the Free Software Foundation.
|
||||
*/
|
||||
|
||||
#ifdef CONFIG_CPU_S3C6410
|
||||
|
||||
extern int s3c6410_init(void);
|
||||
extern void s3c6410_init_irq(void);
|
||||
extern void s3c6410_map_io(void);
|
||||
extern void s3c6410_init_clocks(int xtal);
|
||||
|
||||
#define s3c6410_init_uarts s3c6400_common_init_uarts
|
||||
|
||||
#else
|
||||
#define s3c6410_init_clocks NULL
|
||||
#define s3c6410_init_uarts NULL
|
||||
#define s3c6410_map_io NULL
|
||||
#define s3c6410_init NULL
|
||||
#endif
|
Loading…
Reference in a new issue