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mfd: mt6360: Merge header file into driver and remove unuse register define
Merge header file into driver and remove unuse register define Signed-off-by: Gene Chen <gene_chen@richtek.com> Signed-off-by: Lee Jones <lee.jones@linaro.org>
This commit is contained in:
Gene Chen
Lee Jones
parent
e847029406
commit
b042c085de
2 changed files with 47 additions and 241 deletions
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@ -15,7 +15,53 @@
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#include <linux/regmap.h>
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#include <linux/slab.h>
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#include <linux/mfd/mt6360.h>
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enum {
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MT6360_SLAVE_TCPC = 0,
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MT6360_SLAVE_PMIC,
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MT6360_SLAVE_LDO,
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MT6360_SLAVE_PMU,
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MT6360_SLAVE_MAX,
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};
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struct mt6360_ddata {
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struct i2c_client *i2c[MT6360_SLAVE_MAX];
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struct device *dev;
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struct regmap *regmap;
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struct regmap_irq_chip_data *irq_data;
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unsigned int chip_rev;
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u8 crc8_tbl[CRC8_TABLE_SIZE];
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};
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#define MT6360_TCPC_SLAVEID 0x4E
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#define MT6360_PMIC_SLAVEID 0x1A
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#define MT6360_LDO_SLAVEID 0x64
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#define MT6360_PMU_SLAVEID 0x34
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#define MT6360_REG_TCPCSTART 0x00
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#define MT6360_REG_TCPCEND 0xFF
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#define MT6360_REG_PMICSTART 0x100
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#define MT6360_REG_PMICEND 0x13B
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#define MT6360_REG_LDOSTART 0x200
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#define MT6360_REG_LDOEND 0x21C
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#define MT6360_REG_PMUSTART 0x300
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#define MT6360_PMU_DEV_INFO 0x300
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#define MT6360_PMU_CHG_IRQ1 0x3D0
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#define MT6360_PMU_CHG_MASK1 0x3F0
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#define MT6360_REG_PMUEND 0x3FF
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#define MT6360_PMU_IRQ_REGNUM 16
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#define CHIP_VEN_MASK 0xF0
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#define CHIP_VEN_MT6360 0x50
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#define CHIP_REV_MASK 0x0F
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#define MT6360_ADDRESS_MASK 0x3F
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#define MT6360_DATA_SIZE_1_BYTE 0x00
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#define MT6360_DATA_SIZE_2_BYTES 0x40
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#define MT6360_DATA_SIZE_3_BYTES 0x80
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#define MT6360_DATA_SIZE_4_BYTES 0xC0
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#define MT6360_CRC8_POLYNOMIAL 0x7
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/* reg 0 -> 0 ~ 7 */
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#define MT6360_CHG_TREG_EVT 4
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@ -1,240 +0,0 @@
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/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* Copyright (c) 2020 MediaTek Inc.
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*/
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#ifndef __MT6360_H__
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#define __MT6360_H__
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#include <linux/regmap.h>
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enum {
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MT6360_SLAVE_PMU = 0,
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MT6360_SLAVE_PMIC,
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MT6360_SLAVE_LDO,
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MT6360_SLAVE_TCPC,
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MT6360_SLAVE_MAX,
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};
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#define MT6360_PMU_SLAVEID 0x34
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#define MT6360_PMIC_SLAVEID 0x1A
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#define MT6360_LDO_SLAVEID 0x64
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#define MT6360_TCPC_SLAVEID 0x4E
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struct mt6360_ddata {
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struct i2c_client *i2c[MT6360_SLAVE_MAX];
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struct device *dev;
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struct regmap *regmap;
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struct regmap_irq_chip_data *irq_data;
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unsigned int chip_rev;
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};
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/* PMU register defininition */
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#define MT6360_PMU_DEV_INFO 0x00
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#define MT6360_PMU_CORE_CTRL1 0x01
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#define MT6360_PMU_RST1 0x02
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#define MT6360_PMU_CRCEN 0x03
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#define MT6360_PMU_RST_PAS_CODE1 0x04
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#define MT6360_PMU_RST_PAS_CODE2 0x05
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#define MT6360_PMU_CORE_CTRL2 0x06
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#define MT6360_PMU_TM_PAS_CODE1 0x07
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#define MT6360_PMU_TM_PAS_CODE2 0x08
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#define MT6360_PMU_TM_PAS_CODE3 0x09
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#define MT6360_PMU_TM_PAS_CODE4 0x0A
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#define MT6360_PMU_IRQ_IND 0x0B
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#define MT6360_PMU_IRQ_MASK 0x0C
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#define MT6360_PMU_IRQ_SET 0x0D
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#define MT6360_PMU_SHDN_CTRL 0x0E
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#define MT6360_PMU_TM_INF 0x0F
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#define MT6360_PMU_I2C_CTRL 0x10
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#define MT6360_PMU_CHG_CTRL1 0x11
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#define MT6360_PMU_CHG_CTRL2 0x12
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#define MT6360_PMU_CHG_CTRL3 0x13
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#define MT6360_PMU_CHG_CTRL4 0x14
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#define MT6360_PMU_CHG_CTRL5 0x15
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#define MT6360_PMU_CHG_CTRL6 0x16
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#define MT6360_PMU_CHG_CTRL7 0x17
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#define MT6360_PMU_CHG_CTRL8 0x18
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#define MT6360_PMU_CHG_CTRL9 0x19
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#define MT6360_PMU_CHG_CTRL10 0x1A
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#define MT6360_PMU_CHG_CTRL11 0x1B
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#define MT6360_PMU_CHG_CTRL12 0x1C
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#define MT6360_PMU_CHG_CTRL13 0x1D
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#define MT6360_PMU_CHG_CTRL14 0x1E
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#define MT6360_PMU_CHG_CTRL15 0x1F
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#define MT6360_PMU_CHG_CTRL16 0x20
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#define MT6360_PMU_CHG_AICC_RESULT 0x21
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#define MT6360_PMU_DEVICE_TYPE 0x22
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#define MT6360_PMU_QC_CONTROL1 0x23
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#define MT6360_PMU_QC_CONTROL2 0x24
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#define MT6360_PMU_QC30_CONTROL1 0x25
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#define MT6360_PMU_QC30_CONTROL2 0x26
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#define MT6360_PMU_USB_STATUS1 0x27
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#define MT6360_PMU_QC_STATUS1 0x28
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#define MT6360_PMU_QC_STATUS2 0x29
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#define MT6360_PMU_CHG_PUMP 0x2A
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#define MT6360_PMU_CHG_CTRL17 0x2B
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#define MT6360_PMU_CHG_CTRL18 0x2C
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#define MT6360_PMU_CHRDET_CTRL1 0x2D
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#define MT6360_PMU_CHRDET_CTRL2 0x2E
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#define MT6360_PMU_DPDN_CTRL 0x2F
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#define MT6360_PMU_CHG_HIDDEN_CTRL1 0x30
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#define MT6360_PMU_CHG_HIDDEN_CTRL2 0x31
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#define MT6360_PMU_CHG_HIDDEN_CTRL3 0x32
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#define MT6360_PMU_CHG_HIDDEN_CTRL4 0x33
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#define MT6360_PMU_CHG_HIDDEN_CTRL5 0x34
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#define MT6360_PMU_CHG_HIDDEN_CTRL6 0x35
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#define MT6360_PMU_CHG_HIDDEN_CTRL7 0x36
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#define MT6360_PMU_CHG_HIDDEN_CTRL8 0x37
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#define MT6360_PMU_CHG_HIDDEN_CTRL9 0x38
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#define MT6360_PMU_CHG_HIDDEN_CTRL10 0x39
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#define MT6360_PMU_CHG_HIDDEN_CTRL11 0x3A
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#define MT6360_PMU_CHG_HIDDEN_CTRL12 0x3B
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#define MT6360_PMU_CHG_HIDDEN_CTRL13 0x3C
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#define MT6360_PMU_CHG_HIDDEN_CTRL14 0x3D
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#define MT6360_PMU_CHG_HIDDEN_CTRL15 0x3E
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#define MT6360_PMU_CHG_HIDDEN_CTRL16 0x3F
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#define MT6360_PMU_CHG_HIDDEN_CTRL17 0x40
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#define MT6360_PMU_CHG_HIDDEN_CTRL18 0x41
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#define MT6360_PMU_CHG_HIDDEN_CTRL19 0x42
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#define MT6360_PMU_CHG_HIDDEN_CTRL20 0x43
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#define MT6360_PMU_CHG_HIDDEN_CTRL21 0x44
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#define MT6360_PMU_CHG_HIDDEN_CTRL22 0x45
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#define MT6360_PMU_CHG_HIDDEN_CTRL23 0x46
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#define MT6360_PMU_CHG_HIDDEN_CTRL24 0x47
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#define MT6360_PMU_CHG_HIDDEN_CTRL25 0x48
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#define MT6360_PMU_BC12_CTRL 0x49
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#define MT6360_PMU_CHG_STAT 0x4A
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#define MT6360_PMU_RESV1 0x4B
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#define MT6360_PMU_TYPEC_OTP_TH_SEL_CODEH 0x4E
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#define MT6360_PMU_TYPEC_OTP_TH_SEL_CODEL 0x4F
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#define MT6360_PMU_TYPEC_OTP_HYST_TH 0x50
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#define MT6360_PMU_TYPEC_OTP_CTRL 0x51
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#define MT6360_PMU_ADC_BAT_DATA_H 0x52
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#define MT6360_PMU_ADC_BAT_DATA_L 0x53
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#define MT6360_PMU_IMID_BACKBST_ON 0x54
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#define MT6360_PMU_IMID_BACKBST_OFF 0x55
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#define MT6360_PMU_ADC_CONFIG 0x56
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#define MT6360_PMU_ADC_EN2 0x57
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#define MT6360_PMU_ADC_IDLE_T 0x58
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#define MT6360_PMU_ADC_RPT_1 0x5A
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#define MT6360_PMU_ADC_RPT_2 0x5B
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#define MT6360_PMU_ADC_RPT_3 0x5C
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#define MT6360_PMU_ADC_RPT_ORG1 0x5D
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#define MT6360_PMU_ADC_RPT_ORG2 0x5E
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#define MT6360_PMU_BAT_OVP_TH_SEL_CODEH 0x5F
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#define MT6360_PMU_BAT_OVP_TH_SEL_CODEL 0x60
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#define MT6360_PMU_CHG_CTRL19 0x61
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#define MT6360_PMU_VDDASUPPLY 0x62
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#define MT6360_PMU_BC12_MANUAL 0x63
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#define MT6360_PMU_CHGDET_FUNC 0x64
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#define MT6360_PMU_FOD_CTRL 0x65
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#define MT6360_PMU_CHG_CTRL20 0x66
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#define MT6360_PMU_CHG_HIDDEN_CTRL26 0x67
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#define MT6360_PMU_CHG_HIDDEN_CTRL27 0x68
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#define MT6360_PMU_RESV2 0x69
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#define MT6360_PMU_USBID_CTRL1 0x6D
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#define MT6360_PMU_USBID_CTRL2 0x6E
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#define MT6360_PMU_USBID_CTRL3 0x6F
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#define MT6360_PMU_FLED_CFG 0x70
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#define MT6360_PMU_RESV3 0x71
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#define MT6360_PMU_FLED1_CTRL 0x72
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#define MT6360_PMU_FLED_STRB_CTRL 0x73
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#define MT6360_PMU_FLED1_STRB_CTRL2 0x74
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#define MT6360_PMU_FLED1_TOR_CTRL 0x75
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#define MT6360_PMU_FLED2_CTRL 0x76
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#define MT6360_PMU_RESV4 0x77
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#define MT6360_PMU_FLED2_STRB_CTRL2 0x78
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#define MT6360_PMU_FLED2_TOR_CTRL 0x79
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#define MT6360_PMU_FLED_VMIDTRK_CTRL1 0x7A
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#define MT6360_PMU_FLED_VMID_RTM 0x7B
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#define MT6360_PMU_FLED_VMIDTRK_CTRL2 0x7C
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#define MT6360_PMU_FLED_PWSEL 0x7D
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#define MT6360_PMU_FLED_EN 0x7E
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#define MT6360_PMU_FLED_Hidden1 0x7F
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#define MT6360_PMU_RGB_EN 0x80
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#define MT6360_PMU_RGB1_ISNK 0x81
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#define MT6360_PMU_RGB2_ISNK 0x82
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#define MT6360_PMU_RGB3_ISNK 0x83
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#define MT6360_PMU_RGB_ML_ISNK 0x84
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#define MT6360_PMU_RGB1_DIM 0x85
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#define MT6360_PMU_RGB2_DIM 0x86
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#define MT6360_PMU_RGB3_DIM 0x87
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#define MT6360_PMU_RESV5 0x88
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#define MT6360_PMU_RGB12_Freq 0x89
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#define MT6360_PMU_RGB34_Freq 0x8A
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#define MT6360_PMU_RGB1_Tr 0x8B
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#define MT6360_PMU_RGB1_Tf 0x8C
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#define MT6360_PMU_RGB1_TON_TOFF 0x8D
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#define MT6360_PMU_RGB2_Tr 0x8E
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#define MT6360_PMU_RGB2_Tf 0x8F
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#define MT6360_PMU_RGB2_TON_TOFF 0x90
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#define MT6360_PMU_RGB3_Tr 0x91
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#define MT6360_PMU_RGB3_Tf 0x92
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#define MT6360_PMU_RGB3_TON_TOFF 0x93
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#define MT6360_PMU_RGB_Hidden_CTRL1 0x94
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#define MT6360_PMU_RGB_Hidden_CTRL2 0x95
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#define MT6360_PMU_RESV6 0x97
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#define MT6360_PMU_SPARE1 0x9A
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#define MT6360_PMU_SPARE2 0xA0
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#define MT6360_PMU_SPARE3 0xB0
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#define MT6360_PMU_SPARE4 0xC0
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#define MT6360_PMU_CHG_IRQ1 0xD0
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#define MT6360_PMU_CHG_IRQ2 0xD1
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#define MT6360_PMU_CHG_IRQ3 0xD2
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#define MT6360_PMU_CHG_IRQ4 0xD3
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#define MT6360_PMU_CHG_IRQ5 0xD4
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#define MT6360_PMU_CHG_IRQ6 0xD5
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#define MT6360_PMU_QC_IRQ 0xD6
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#define MT6360_PMU_FOD_IRQ 0xD7
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#define MT6360_PMU_BASE_IRQ 0xD8
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#define MT6360_PMU_FLED_IRQ1 0xD9
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#define MT6360_PMU_FLED_IRQ2 0xDA
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#define MT6360_PMU_RGB_IRQ 0xDB
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#define MT6360_PMU_BUCK1_IRQ 0xDC
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#define MT6360_PMU_BUCK2_IRQ 0xDD
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#define MT6360_PMU_LDO_IRQ1 0xDE
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#define MT6360_PMU_LDO_IRQ2 0xDF
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#define MT6360_PMU_CHG_STAT1 0xE0
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#define MT6360_PMU_CHG_STAT2 0xE1
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#define MT6360_PMU_CHG_STAT3 0xE2
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#define MT6360_PMU_CHG_STAT4 0xE3
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#define MT6360_PMU_CHG_STAT5 0xE4
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#define MT6360_PMU_CHG_STAT6 0xE5
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#define MT6360_PMU_QC_STAT 0xE6
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#define MT6360_PMU_FOD_STAT 0xE7
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#define MT6360_PMU_BASE_STAT 0xE8
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#define MT6360_PMU_FLED_STAT1 0xE9
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#define MT6360_PMU_FLED_STAT2 0xEA
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#define MT6360_PMU_RGB_STAT 0xEB
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#define MT6360_PMU_BUCK1_STAT 0xEC
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#define MT6360_PMU_BUCK2_STAT 0xED
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#define MT6360_PMU_LDO_STAT1 0xEE
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#define MT6360_PMU_LDO_STAT2 0xEF
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#define MT6360_PMU_CHG_MASK1 0xF0
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#define MT6360_PMU_CHG_MASK2 0xF1
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#define MT6360_PMU_CHG_MASK3 0xF2
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#define MT6360_PMU_CHG_MASK4 0xF3
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#define MT6360_PMU_CHG_MASK5 0xF4
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#define MT6360_PMU_CHG_MASK6 0xF5
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#define MT6360_PMU_QC_MASK 0xF6
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#define MT6360_PMU_FOD_MASK 0xF7
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#define MT6360_PMU_BASE_MASK 0xF8
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#define MT6360_PMU_FLED_MASK1 0xF9
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#define MT6360_PMU_FLED_MASK2 0xFA
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#define MT6360_PMU_FAULTB_MASK 0xFB
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#define MT6360_PMU_BUCK1_MASK 0xFC
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#define MT6360_PMU_BUCK2_MASK 0xFD
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#define MT6360_PMU_LDO_MASK1 0xFE
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#define MT6360_PMU_LDO_MASK2 0xFF
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#define MT6360_PMU_MAXREG MT6360_PMU_LDO_MASK2
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/* MT6360_PMU_IRQ_SET */
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#define MT6360_PMU_IRQ_REGNUM 16
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#define MT6360_IRQ_RETRIG BIT(2)
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#define CHIP_VEN_MASK 0xF0
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#define CHIP_VEN_MT6360 0x50
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#define CHIP_REV_MASK 0x0F
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#endif /* __MT6360_H__ */
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