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net: bcmgenet: add support for new GENET PHY revision scheme
Starting with GPHY revision G0, the GENET register layout has changed to use the same numbering scheme as the Starfighter 2 switch. This means that GPHY major revision is in bits 15:12, minor in bits 11:8 and patch level is in bits 7:4. Introduce a small heuristic which checks for the old scheme first, tests for the new scheme and finally attempts to catch reserved values and aborts. Signed-off-by: Florian Fainelli <f.fainelli@gmail.com> Signed-off-by: David S. Miller <davem@davemloft.net>
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1 changed files with 23 additions and 1 deletions
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@ -2504,6 +2504,7 @@ static void bcmgenet_set_hw_params(struct bcmgenet_priv *priv)
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struct bcmgenet_hw_params *params;
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u32 reg;
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u8 major;
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u16 gphy_rev;
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if (GENET_IS_V4(priv)) {
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bcmgenet_dma_regs = bcmgenet_dma_regs_v3plus;
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@ -2552,8 +2553,29 @@ static void bcmgenet_set_hw_params(struct bcmgenet_priv *priv)
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* to pass this information to the PHY driver. The PHY driver expects
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* to find the PHY major revision in bits 15:8 while the GENET register
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* stores that information in bits 7:0, account for that.
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*
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* On newer chips, starting with PHY revision G0, a new scheme is
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* deployed similar to the Starfighter 2 switch with GPHY major
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* revision in bits 15:8 and patch level in bits 7:0. Major revision 0
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* is reserved as well as special value 0x01ff, we have a small
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* heuristic to check for the new GPHY revision and re-arrange things
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* so the GPHY driver is happy.
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*/
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priv->gphy_rev = (reg & 0xffff) << 8;
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gphy_rev = reg & 0xffff;
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/* This is the good old scheme, just GPHY major, no minor nor patch */
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if ((gphy_rev & 0xf0) != 0)
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priv->gphy_rev = gphy_rev << 8;
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/* This is the new scheme, GPHY major rolls over with 0x10 = rev G0 */
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else if ((gphy_rev & 0xff00) != 0)
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priv->gphy_rev = gphy_rev;
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/* This is reserved so should require special treatment */
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else if (gphy_rev == 0 || gphy_rev == 0x01ff) {
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pr_warn("Invalid GPHY revision detected: 0x%04x\n", gphy_rev);
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return;
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}
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#ifdef CONFIG_PHYS_ADDR_T_64BIT
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if (!(params->flags & GENET_HAS_40BITS))
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