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pinctrl: sunxi: h6-r: Add s_rsb pin functions
As there is an RSB controller in the H6 SoC, there should be some pin configuration for it. While no such configuration is documented, the "s_i2c" pins are suspiciously on the "alternate" function 3, with no primary function 2 given. This suggests the primary function for these pins is actually RSB, and that is indeed the case. Add the "s_rsb" pin functions so the RSB controller can be used. Signed-off-by: Samuel Holland <samuel@sholland.org> Acked-by: Chen-Yu Tsai <wens@csie.org> Acked-by: Maxime Ripard <mripard@kernel.org> Link: https://lore.kernel.org/r/20210103100007.32867-3-samuel@sholland.org Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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@ -24,11 +24,13 @@ static const struct sunxi_desc_pin sun50i_h6_r_pins[] = {
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SUNXI_PIN(SUNXI_PINCTRL_PIN(L, 0),
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SUNXI_FUNCTION(0x0, "gpio_in"),
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SUNXI_FUNCTION(0x1, "gpio_out"),
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SUNXI_FUNCTION(0x2, "s_rsb"), /* SCK */
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SUNXI_FUNCTION(0x3, "s_i2c"), /* SCK */
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SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 0)), /* PL_EINT0 */
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SUNXI_PIN(SUNXI_PINCTRL_PIN(L, 1),
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SUNXI_FUNCTION(0x0, "gpio_in"),
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SUNXI_FUNCTION(0x1, "gpio_out"),
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SUNXI_FUNCTION(0x2, "s_rsb"), /* SDA */
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SUNXI_FUNCTION(0x3, "s_i2c"), /* SDA */
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SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 1)), /* PL_EINT1 */
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SUNXI_PIN(SUNXI_PINCTRL_PIN(L, 2),
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