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drm/amdgpu: move more logic into amdgpu_vm_map_gart v3
No need to duplicate that code over and over again. Also stop using the flags to determine if we need to map the addresses. v2: constify the pages_addr v3: rebased, fix typo in commit message Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
This commit is contained in:
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599f434817
commit
b07c9d2a73
5 changed files with 33 additions and 42 deletions
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@ -283,7 +283,7 @@ struct amdgpu_vm_pte_funcs {
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unsigned count);
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unsigned count);
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/* write pte one entry at a time with addr mapping */
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/* write pte one entry at a time with addr mapping */
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void (*write_pte)(struct amdgpu_ib *ib,
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void (*write_pte)(struct amdgpu_ib *ib,
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uint64_t pe,
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const dma_addr_t *pages_addr, uint64_t pe,
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uint64_t addr, unsigned count,
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uint64_t addr, unsigned count,
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uint32_t incr, uint32_t flags);
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uint32_t incr, uint32_t flags);
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/* for linear pte/pde updates without addr mapping */
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/* for linear pte/pde updates without addr mapping */
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@ -962,7 +962,7 @@ int amdgpu_vm_grab_id(struct amdgpu_vm *vm, struct amdgpu_ring *ring,
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void amdgpu_vm_flush(struct amdgpu_ring *ring,
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void amdgpu_vm_flush(struct amdgpu_ring *ring,
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struct amdgpu_vm *vm,
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struct amdgpu_vm *vm,
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struct fence *updates);
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struct fence *updates);
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uint64_t amdgpu_vm_map_gart(struct amdgpu_device *adev, uint64_t addr);
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uint64_t amdgpu_vm_map_gart(const dma_addr_t *pages_addr, uint64_t addr);
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int amdgpu_vm_update_page_directory(struct amdgpu_device *adev,
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int amdgpu_vm_update_page_directory(struct amdgpu_device *adev,
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struct amdgpu_vm *vm);
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struct amdgpu_vm *vm);
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int amdgpu_vm_clear_freed(struct amdgpu_device *adev,
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int amdgpu_vm_clear_freed(struct amdgpu_device *adev,
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@ -2198,7 +2198,7 @@ amdgpu_get_sdma_instance(struct amdgpu_ring *ring)
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#define amdgpu_gart_flush_gpu_tlb(adev, vmid) (adev)->gart.gart_funcs->flush_gpu_tlb((adev), (vmid))
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#define amdgpu_gart_flush_gpu_tlb(adev, vmid) (adev)->gart.gart_funcs->flush_gpu_tlb((adev), (vmid))
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#define amdgpu_gart_set_pte_pde(adev, pt, idx, addr, flags) (adev)->gart.gart_funcs->set_pte_pde((adev), (pt), (idx), (addr), (flags))
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#define amdgpu_gart_set_pte_pde(adev, pt, idx, addr, flags) (adev)->gart.gart_funcs->set_pte_pde((adev), (pt), (idx), (addr), (flags))
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#define amdgpu_vm_copy_pte(adev, ib, pe, src, count) ((adev)->vm_manager.vm_pte_funcs->copy_pte((ib), (pe), (src), (count)))
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#define amdgpu_vm_copy_pte(adev, ib, pe, src, count) ((adev)->vm_manager.vm_pte_funcs->copy_pte((ib), (pe), (src), (count)))
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#define amdgpu_vm_write_pte(adev, ib, pe, addr, count, incr, flags) ((adev)->vm_manager.vm_pte_funcs->write_pte((ib), (pe), (addr), (count), (incr), (flags)))
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#define amdgpu_vm_write_pte(adev, ib, pa, pe, addr, count, incr, flags) ((adev)->vm_manager.vm_pte_funcs->write_pte((ib), (pa), (pe), (addr), (count), (incr), (flags)))
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#define amdgpu_vm_set_pte_pde(adev, ib, pe, addr, count, incr, flags) ((adev)->vm_manager.vm_pte_funcs->set_pte_pde((ib), (pe), (addr), (count), (incr), (flags)))
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#define amdgpu_vm_set_pte_pde(adev, ib, pe, addr, count, incr, flags) ((adev)->vm_manager.vm_pte_funcs->set_pte_pde((ib), (pe), (addr), (count), (incr), (flags)))
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#define amdgpu_vm_pad_ib(adev, ib) ((adev)->vm_manager.vm_pte_funcs->pad_ib((ib)))
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#define amdgpu_vm_pad_ib(adev, ib) ((adev)->vm_manager.vm_pte_funcs->pad_ib((ib)))
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#define amdgpu_ring_parse_cs(r, p, ib) ((r)->funcs->parse_cs((p), (ib)))
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#define amdgpu_ring_parse_cs(r, p, ib) ((r)->funcs->parse_cs((p), (ib)))
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@ -299,8 +299,13 @@ static void amdgpu_vm_update_pages(struct amdgpu_device *adev,
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uint64_t src = adev->gart.table_addr + (addr >> 12) * 8;
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uint64_t src = adev->gart.table_addr + (addr >> 12) * 8;
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amdgpu_vm_copy_pte(adev, ib, pe, src, count);
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amdgpu_vm_copy_pte(adev, ib, pe, src, count);
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} else if ((flags & AMDGPU_PTE_SYSTEM) || (count < 3)) {
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} else if (flags & AMDGPU_PTE_SYSTEM) {
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amdgpu_vm_write_pte(adev, ib, pe, addr,
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dma_addr_t *pages_addr = adev->gart.pages_addr;
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amdgpu_vm_write_pte(adev, ib, pages_addr, pe, addr,
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count, incr, flags);
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} else if (count < 3) {
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amdgpu_vm_write_pte(adev, ib, NULL, pe, addr,
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count, incr, flags);
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count, incr, flags);
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} else {
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} else {
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@ -378,25 +383,32 @@ static int amdgpu_vm_clear_bo(struct amdgpu_device *adev,
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}
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}
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/**
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/**
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* amdgpu_vm_map_gart - get the physical address of a gart page
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* amdgpu_vm_map_gart - Resolve gart mapping of addr
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*
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*
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* @adev: amdgpu_device pointer
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* @pages_addr: optional DMA address to use for lookup
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* @addr: the unmapped addr
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* @addr: the unmapped addr
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*
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*
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* Look up the physical address of the page that the pte resolves
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* Look up the physical address of the page that the pte resolves
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* to (cayman+).
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* to and return the pointer for the page table entry.
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* Returns the physical address of the page.
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*/
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*/
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uint64_t amdgpu_vm_map_gart(struct amdgpu_device *adev, uint64_t addr)
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uint64_t amdgpu_vm_map_gart(const dma_addr_t *pages_addr, uint64_t addr)
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{
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{
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uint64_t result;
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uint64_t result;
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if (pages_addr) {
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/* page table offset */
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/* page table offset */
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result = adev->gart.pages_addr[addr >> PAGE_SHIFT];
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result = pages_addr[addr >> PAGE_SHIFT];
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/* in case cpu page size != gpu page size*/
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/* in case cpu page size != gpu page size*/
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result |= addr & (~PAGE_MASK);
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result |= addr & (~PAGE_MASK);
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} else {
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/* No mapping required */
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result = addr;
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}
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result &= 0xFFFFFFFFFFFFF000ULL;
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return result;
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return result;
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}
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}
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@ -714,7 +714,7 @@ static void cik_sdma_vm_copy_pte(struct amdgpu_ib *ib,
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* Update PTEs by writing them manually using sDMA (CIK).
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* Update PTEs by writing them manually using sDMA (CIK).
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*/
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*/
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static void cik_sdma_vm_write_pte(struct amdgpu_ib *ib,
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static void cik_sdma_vm_write_pte(struct amdgpu_ib *ib,
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uint64_t pe,
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const dma_addr_t *pages_addr, uint64_t pe,
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uint64_t addr, unsigned count,
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uint64_t addr, unsigned count,
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uint32_t incr, uint32_t flags)
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uint32_t incr, uint32_t flags)
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{
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{
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@ -733,14 +733,7 @@ static void cik_sdma_vm_write_pte(struct amdgpu_ib *ib,
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ib->ptr[ib->length_dw++] = upper_32_bits(pe);
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ib->ptr[ib->length_dw++] = upper_32_bits(pe);
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ib->ptr[ib->length_dw++] = ndw;
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ib->ptr[ib->length_dw++] = ndw;
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for (; ndw > 0; ndw -= 2, --count, pe += 8) {
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for (; ndw > 0; ndw -= 2, --count, pe += 8) {
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if (flags & AMDGPU_PTE_SYSTEM) {
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value = amdgpu_vm_map_gart(pages_addr, addr);
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value = amdgpu_vm_map_gart(ib->ring->adev, addr);
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value &= 0xFFFFFFFFFFFFF000ULL;
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} else if (flags & AMDGPU_PTE_VALID) {
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value = addr;
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} else {
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value = 0;
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}
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addr += incr;
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addr += incr;
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value |= flags;
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value |= flags;
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ib->ptr[ib->length_dw++] = value;
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ib->ptr[ib->length_dw++] = value;
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@ -772,7 +772,7 @@ static void sdma_v2_4_vm_copy_pte(struct amdgpu_ib *ib,
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* Update PTEs by writing them manually using sDMA (CIK).
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* Update PTEs by writing them manually using sDMA (CIK).
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*/
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*/
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static void sdma_v2_4_vm_write_pte(struct amdgpu_ib *ib,
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static void sdma_v2_4_vm_write_pte(struct amdgpu_ib *ib,
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uint64_t pe,
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const dma_addr_t *pages_addr, uint64_t pe,
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uint64_t addr, unsigned count,
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uint64_t addr, unsigned count,
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uint32_t incr, uint32_t flags)
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uint32_t incr, uint32_t flags)
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{
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{
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@ -791,14 +791,7 @@ static void sdma_v2_4_vm_write_pte(struct amdgpu_ib *ib,
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ib->ptr[ib->length_dw++] = upper_32_bits(pe);
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ib->ptr[ib->length_dw++] = upper_32_bits(pe);
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ib->ptr[ib->length_dw++] = ndw;
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ib->ptr[ib->length_dw++] = ndw;
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for (; ndw > 0; ndw -= 2, --count, pe += 8) {
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for (; ndw > 0; ndw -= 2, --count, pe += 8) {
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if (flags & AMDGPU_PTE_SYSTEM) {
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value = amdgpu_vm_map_gart(pages_addr, addr);
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value = amdgpu_vm_map_gart(ib->ring->adev, addr);
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value &= 0xFFFFFFFFFFFFF000ULL;
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} else if (flags & AMDGPU_PTE_VALID) {
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value = addr;
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} else {
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value = 0;
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}
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addr += incr;
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addr += incr;
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value |= flags;
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value |= flags;
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ib->ptr[ib->length_dw++] = value;
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ib->ptr[ib->length_dw++] = value;
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@ -922,7 +922,7 @@ static void sdma_v3_0_vm_copy_pte(struct amdgpu_ib *ib,
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* Update PTEs by writing them manually using sDMA (CIK).
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* Update PTEs by writing them manually using sDMA (CIK).
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*/
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*/
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static void sdma_v3_0_vm_write_pte(struct amdgpu_ib *ib,
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static void sdma_v3_0_vm_write_pte(struct amdgpu_ib *ib,
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uint64_t pe,
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const dma_addr_t *pages_addr, uint64_t pe,
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uint64_t addr, unsigned count,
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uint64_t addr, unsigned count,
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uint32_t incr, uint32_t flags)
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uint32_t incr, uint32_t flags)
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{
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{
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@ -941,14 +941,7 @@ static void sdma_v3_0_vm_write_pte(struct amdgpu_ib *ib,
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ib->ptr[ib->length_dw++] = upper_32_bits(pe);
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ib->ptr[ib->length_dw++] = upper_32_bits(pe);
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ib->ptr[ib->length_dw++] = ndw;
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ib->ptr[ib->length_dw++] = ndw;
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for (; ndw > 0; ndw -= 2, --count, pe += 8) {
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for (; ndw > 0; ndw -= 2, --count, pe += 8) {
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if (flags & AMDGPU_PTE_SYSTEM) {
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value = amdgpu_vm_map_gart(pages_addr, addr);
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value = amdgpu_vm_map_gart(ib->ring->adev, addr);
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value &= 0xFFFFFFFFFFFFF000ULL;
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} else if (flags & AMDGPU_PTE_VALID) {
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value = addr;
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} else {
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value = 0;
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}
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addr += incr;
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addr += incr;
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value |= flags;
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value |= flags;
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ib->ptr[ib->length_dw++] = value;
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ib->ptr[ib->length_dw++] = value;
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