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[PATCH] x86: Temporarily revert parts of the Core 2 nmi nmi watchdog support
This makes merging easier. They are readded a few patches later. Signed-off-by: Andi Kleen <ak@suse.de>
This commit is contained in:
parent
874c4fe389
commit
b07f8915cd
4 changed files with 6 additions and 178 deletions
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@ -24,7 +24,6 @@
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#include <asm/smp.h>
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#include <asm/smp.h>
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#include <asm/nmi.h>
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#include <asm/nmi.h>
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#include <asm/intel_arch_perfmon.h>
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#include "mach_traps.h"
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#include "mach_traps.h"
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@ -96,9 +95,6 @@ int nmi_active;
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(P4_CCCR_OVF_PMI0|P4_CCCR_THRESHOLD(15)|P4_CCCR_COMPLEMENT| \
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(P4_CCCR_OVF_PMI0|P4_CCCR_THRESHOLD(15)|P4_CCCR_COMPLEMENT| \
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P4_CCCR_COMPARE|P4_CCCR_REQUIRED|P4_CCCR_ESCR_SELECT(4)|P4_CCCR_ENABLE)
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P4_CCCR_COMPARE|P4_CCCR_REQUIRED|P4_CCCR_ESCR_SELECT(4)|P4_CCCR_ENABLE)
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#define ARCH_PERFMON_NMI_EVENT_SEL ARCH_PERFMON_UNHALTED_CORE_CYCLES_SEL
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#define ARCH_PERFMON_NMI_EVENT_UMASK ARCH_PERFMON_UNHALTED_CORE_CYCLES_UMASK
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#ifdef CONFIG_SMP
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#ifdef CONFIG_SMP
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/* The performance counters used by NMI_LOCAL_APIC don't trigger when
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/* The performance counters used by NMI_LOCAL_APIC don't trigger when
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* the CPU is idle. To make sure the NMI watchdog really ticks on all
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* the CPU is idle. To make sure the NMI watchdog really ticks on all
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@ -211,8 +207,6 @@ static int __init setup_nmi_watchdog(char *str)
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__setup("nmi_watchdog=", setup_nmi_watchdog);
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__setup("nmi_watchdog=", setup_nmi_watchdog);
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static void disable_intel_arch_watchdog(void);
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static void disable_lapic_nmi_watchdog(void)
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static void disable_lapic_nmi_watchdog(void)
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{
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{
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if (nmi_active <= 0)
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if (nmi_active <= 0)
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@ -222,10 +216,6 @@ static void disable_lapic_nmi_watchdog(void)
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wrmsr(MSR_K7_EVNTSEL0, 0, 0);
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wrmsr(MSR_K7_EVNTSEL0, 0, 0);
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break;
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break;
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case X86_VENDOR_INTEL:
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case X86_VENDOR_INTEL:
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if (cpu_has(&boot_cpu_data, X86_FEATURE_ARCH_PERFMON)) {
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disable_intel_arch_watchdog();
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break;
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}
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switch (boot_cpu_data.x86) {
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switch (boot_cpu_data.x86) {
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case 6:
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case 6:
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if (boot_cpu_data.x86_model > 0xd)
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if (boot_cpu_data.x86_model > 0xd)
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@ -454,53 +444,6 @@ static int setup_p4_watchdog(void)
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return 1;
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return 1;
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}
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}
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static void disable_intel_arch_watchdog(void)
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{
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unsigned ebx;
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/*
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* Check whether the Architectural PerfMon supports
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* Unhalted Core Cycles Event or not.
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* NOTE: Corresponding bit = 0 in ebp indicates event present.
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*/
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ebx = cpuid_ebx(10);
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if (!(ebx & ARCH_PERFMON_UNHALTED_CORE_CYCLES_PRESENT))
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wrmsr(MSR_ARCH_PERFMON_EVENTSEL0, 0, 0);
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}
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static int setup_intel_arch_watchdog(void)
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{
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unsigned int evntsel;
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unsigned ebx;
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/*
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* Check whether the Architectural PerfMon supports
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* Unhalted Core Cycles Event or not.
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* NOTE: Corresponding bit = 0 in ebp indicates event present.
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*/
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ebx = cpuid_ebx(10);
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if ((ebx & ARCH_PERFMON_UNHALTED_CORE_CYCLES_PRESENT))
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return 0;
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nmi_perfctr_msr = MSR_ARCH_PERFMON_PERFCTR0;
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clear_msr_range(MSR_ARCH_PERFMON_EVENTSEL0, 2);
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clear_msr_range(MSR_ARCH_PERFMON_PERFCTR0, 2);
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evntsel = ARCH_PERFMON_EVENTSEL_INT
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| ARCH_PERFMON_EVENTSEL_OS
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| ARCH_PERFMON_EVENTSEL_USR
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| ARCH_PERFMON_NMI_EVENT_SEL
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| ARCH_PERFMON_NMI_EVENT_UMASK;
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wrmsr(MSR_ARCH_PERFMON_EVENTSEL0, evntsel, 0);
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write_watchdog_counter("INTEL_ARCH_PERFCTR0");
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apic_write(APIC_LVTPC, APIC_DM_NMI);
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evntsel |= ARCH_PERFMON_EVENTSEL0_ENABLE;
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wrmsr(MSR_ARCH_PERFMON_EVENTSEL0, evntsel, 0);
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return 1;
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}
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void setup_apic_nmi_watchdog (void)
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void setup_apic_nmi_watchdog (void)
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{
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{
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switch (boot_cpu_data.x86_vendor) {
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switch (boot_cpu_data.x86_vendor) {
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@ -510,11 +453,6 @@ void setup_apic_nmi_watchdog (void)
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setup_k7_watchdog();
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setup_k7_watchdog();
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break;
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break;
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case X86_VENDOR_INTEL:
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case X86_VENDOR_INTEL:
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if (cpu_has(&boot_cpu_data, X86_FEATURE_ARCH_PERFMON)) {
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if (!setup_intel_arch_watchdog())
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return;
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break;
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}
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switch (boot_cpu_data.x86) {
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switch (boot_cpu_data.x86) {
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case 6:
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case 6:
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if (boot_cpu_data.x86_model > 0xd)
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if (boot_cpu_data.x86_model > 0xd)
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@ -619,8 +557,7 @@ void nmi_watchdog_tick (struct pt_regs * regs)
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wrmsr(MSR_P4_IQ_CCCR0, nmi_p4_cccr_val, 0);
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wrmsr(MSR_P4_IQ_CCCR0, nmi_p4_cccr_val, 0);
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apic_write(APIC_LVTPC, APIC_DM_NMI);
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apic_write(APIC_LVTPC, APIC_DM_NMI);
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}
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}
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else if (nmi_perfctr_msr == MSR_P6_PERFCTR0 ||
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else if (nmi_perfctr_msr == MSR_P6_PERFCTR0) {
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nmi_perfctr_msr == MSR_ARCH_PERFMON_PERFCTR0) {
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/* Only P6 based Pentium M need to re-unmask
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/* Only P6 based Pentium M need to re-unmask
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* the apic vector but it doesn't hurt
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* the apic vector but it doesn't hurt
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* other P6 variant */
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* other P6 variant */
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@ -26,7 +26,6 @@
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#include <asm/proto.h>
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#include <asm/proto.h>
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#include <asm/kdebug.h>
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#include <asm/kdebug.h>
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#include <asm/mce.h>
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#include <asm/mce.h>
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#include <asm/intel_arch_perfmon.h>
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/*
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/*
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* lapic_nmi_owner tracks the ownership of the lapic NMI hardware:
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* lapic_nmi_owner tracks the ownership of the lapic NMI hardware:
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@ -66,9 +65,6 @@ static unsigned int nmi_p4_cccr_val;
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#define K7_EVENT_CYCLES_PROCESSOR_IS_RUNNING 0x76
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#define K7_EVENT_CYCLES_PROCESSOR_IS_RUNNING 0x76
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#define K7_NMI_EVENT K7_EVENT_CYCLES_PROCESSOR_IS_RUNNING
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#define K7_NMI_EVENT K7_EVENT_CYCLES_PROCESSOR_IS_RUNNING
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#define ARCH_PERFMON_NMI_EVENT_SEL ARCH_PERFMON_UNHALTED_CORE_CYCLES_SEL
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#define ARCH_PERFMON_NMI_EVENT_UMASK ARCH_PERFMON_UNHALTED_CORE_CYCLES_UMASK
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#define MSR_P4_MISC_ENABLE 0x1A0
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#define MSR_P4_MISC_ENABLE 0x1A0
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#define MSR_P4_MISC_ENABLE_PERF_AVAIL (1<<7)
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#define MSR_P4_MISC_ENABLE_PERF_AVAIL (1<<7)
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#define MSR_P4_MISC_ENABLE_PEBS_UNAVAIL (1<<12)
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#define MSR_P4_MISC_ENABLE_PEBS_UNAVAIL (1<<12)
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@ -100,10 +96,7 @@ static __cpuinit inline int nmi_known_cpu(void)
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case X86_VENDOR_AMD:
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case X86_VENDOR_AMD:
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return boot_cpu_data.x86 == 15;
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return boot_cpu_data.x86 == 15;
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case X86_VENDOR_INTEL:
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case X86_VENDOR_INTEL:
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if (cpu_has(&boot_cpu_data, X86_FEATURE_ARCH_PERFMON))
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return boot_cpu_data.x86 == 15;
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return 1;
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else
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return (boot_cpu_data.x86 == 15);
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}
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}
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return 0;
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return 0;
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}
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}
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__setup("nmi_watchdog=", setup_nmi_watchdog);
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__setup("nmi_watchdog=", setup_nmi_watchdog);
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static void disable_intel_arch_watchdog(void);
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static void disable_lapic_nmi_watchdog(void)
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static void disable_lapic_nmi_watchdog(void)
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{
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{
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if (nmi_active <= 0)
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if (nmi_active <= 0)
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@ -223,8 +214,6 @@ static void disable_lapic_nmi_watchdog(void)
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if (boot_cpu_data.x86 == 15) {
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if (boot_cpu_data.x86 == 15) {
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wrmsr(MSR_P4_IQ_CCCR0, 0, 0);
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wrmsr(MSR_P4_IQ_CCCR0, 0, 0);
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wrmsr(MSR_P4_CRU_ESCR0, 0, 0);
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wrmsr(MSR_P4_CRU_ESCR0, 0, 0);
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} else if (cpu_has(&boot_cpu_data, X86_FEATURE_ARCH_PERFMON)) {
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disable_intel_arch_watchdog();
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}
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}
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break;
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break;
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}
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}
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@ -377,53 +366,6 @@ static void setup_k7_watchdog(void)
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wrmsr(MSR_K7_EVNTSEL0, evntsel, 0);
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wrmsr(MSR_K7_EVNTSEL0, evntsel, 0);
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}
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}
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static void disable_intel_arch_watchdog(void)
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{
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unsigned ebx;
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/*
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* Check whether the Architectural PerfMon supports
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* Unhalted Core Cycles Event or not.
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* NOTE: Corresponding bit = 0 in ebp indicates event present.
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*/
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ebx = cpuid_ebx(10);
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if (!(ebx & ARCH_PERFMON_UNHALTED_CORE_CYCLES_PRESENT))
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wrmsr(MSR_ARCH_PERFMON_EVENTSEL0, 0, 0);
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}
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static int setup_intel_arch_watchdog(void)
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{
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unsigned int evntsel;
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unsigned ebx;
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/*
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* Check whether the Architectural PerfMon supports
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* Unhalted Core Cycles Event or not.
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* NOTE: Corresponding bit = 0 in ebp indicates event present.
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*/
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ebx = cpuid_ebx(10);
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if ((ebx & ARCH_PERFMON_UNHALTED_CORE_CYCLES_PRESENT))
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return 0;
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nmi_perfctr_msr = MSR_ARCH_PERFMON_PERFCTR0;
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clear_msr_range(MSR_ARCH_PERFMON_EVENTSEL0, 2);
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clear_msr_range(MSR_ARCH_PERFMON_PERFCTR0, 2);
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evntsel = ARCH_PERFMON_EVENTSEL_INT
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| ARCH_PERFMON_EVENTSEL_OS
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| ARCH_PERFMON_EVENTSEL_USR
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| ARCH_PERFMON_NMI_EVENT_SEL
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| ARCH_PERFMON_NMI_EVENT_UMASK;
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wrmsr(MSR_ARCH_PERFMON_EVENTSEL0, evntsel, 0);
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wrmsrl(MSR_ARCH_PERFMON_PERFCTR0, -((u64)cpu_khz * 1000 / nmi_hz));
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apic_write(APIC_LVTPC, APIC_DM_NMI);
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evntsel |= ARCH_PERFMON_EVENTSEL0_ENABLE;
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wrmsr(MSR_ARCH_PERFMON_EVENTSEL0, evntsel, 0);
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return 1;
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}
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static int setup_p4_watchdog(void)
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static int setup_p4_watchdog(void)
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{
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{
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setup_k7_watchdog();
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setup_k7_watchdog();
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break;
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break;
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case X86_VENDOR_INTEL:
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case X86_VENDOR_INTEL:
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if (cpu_has(&boot_cpu_data, X86_FEATURE_ARCH_PERFMON)) {
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if (boot_cpu_data.x86 != 15)
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if (!setup_intel_arch_watchdog())
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return;
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return;
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if (!setup_p4_watchdog())
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} else if (boot_cpu_data.x86 == 15) {
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if (!setup_p4_watchdog())
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return;
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} else {
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return;
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return;
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}
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break;
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break;
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default:
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default:
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@ -571,14 +507,7 @@ void __kprobes nmi_watchdog_tick(struct pt_regs * regs, unsigned reason)
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*/
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*/
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wrmsr(MSR_P4_IQ_CCCR0, nmi_p4_cccr_val, 0);
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wrmsr(MSR_P4_IQ_CCCR0, nmi_p4_cccr_val, 0);
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apic_write(APIC_LVTPC, APIC_DM_NMI);
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apic_write(APIC_LVTPC, APIC_DM_NMI);
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} else if (nmi_perfctr_msr == MSR_ARCH_PERFMON_PERFCTR0) {
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}
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/*
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* For Intel based architectural perfmon
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* - LVTPC is masked on interrupt and must be
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* unmasked by the LVTPC handler.
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*/
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apic_write(APIC_LVTPC, APIC_DM_NMI);
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}
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wrmsrl(nmi_perfctr_msr, -((u64)cpu_khz * 1000 / nmi_hz));
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wrmsrl(nmi_perfctr_msr, -((u64)cpu_khz * 1000 / nmi_hz));
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}
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}
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}
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}
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@ -1,19 +0,0 @@
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#ifndef X86_INTEL_ARCH_PERFMON_H
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#define X86_INTEL_ARCH_PERFMON_H 1
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#define MSR_ARCH_PERFMON_PERFCTR0 0xc1
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#define MSR_ARCH_PERFMON_PERFCTR1 0xc2
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#define MSR_ARCH_PERFMON_EVENTSEL0 0x186
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#define MSR_ARCH_PERFMON_EVENTSEL1 0x187
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#define ARCH_PERFMON_EVENTSEL0_ENABLE (1 << 22)
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#define ARCH_PERFMON_EVENTSEL_INT (1 << 20)
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#define ARCH_PERFMON_EVENTSEL_OS (1 << 17)
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#define ARCH_PERFMON_EVENTSEL_USR (1 << 16)
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#define ARCH_PERFMON_UNHALTED_CORE_CYCLES_SEL (0x3c)
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#define ARCH_PERFMON_UNHALTED_CORE_CYCLES_UMASK (0x00 << 8)
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#define ARCH_PERFMON_UNHALTED_CORE_CYCLES_PRESENT (1 << 0)
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#endif /* X86_INTEL_ARCH_PERFMON_H */
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@ -1,19 +0,0 @@
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#ifndef X86_64_INTEL_ARCH_PERFMON_H
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#define X86_64_INTEL_ARCH_PERFMON_H 1
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#define MSR_ARCH_PERFMON_PERFCTR0 0xc1
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#define MSR_ARCH_PERFMON_PERFCTR1 0xc2
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#define MSR_ARCH_PERFMON_EVENTSEL0 0x186
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#define MSR_ARCH_PERFMON_EVENTSEL1 0x187
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#define ARCH_PERFMON_EVENTSEL0_ENABLE (1 << 22)
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#define ARCH_PERFMON_EVENTSEL_INT (1 << 20)
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#define ARCH_PERFMON_EVENTSEL_OS (1 << 17)
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#define ARCH_PERFMON_EVENTSEL_USR (1 << 16)
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#define ARCH_PERFMON_UNHALTED_CORE_CYCLES_SEL (0x3c)
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#define ARCH_PERFMON_UNHALTED_CORE_CYCLES_UMASK (0x00 << 8)
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#define ARCH_PERFMON_UNHALTED_CORE_CYCLES_PRESENT (1 << 0)
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#endif /* X86_64_INTEL_ARCH_PERFMON_H */
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