arm64: dts: qcom: sc8180x: Add remoteprocs, wifi and usb nodes
This patch adds remoteprocs, wifi and usb and usb phy nodes for this SoC Co-developed-by: Bjorn Andersson <bjorn.andersson@linaro.org> Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Signed-off-by: Vinod Koul <vkoul@kernel.org> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20230530162454.51708-12-vkoul@kernel.org
This commit is contained in:
Vinod Koul
Bjorn Andersson
parent
d20b6c84f5
commit
b080f53a8f
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@ -2227,6 +2227,198 @@
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wakeup-parent = <&pdc>;
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};
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remoteproc_mpss: remoteproc@4080000 {
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compatible = "qcom,sc8180x-mpss-pas";
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reg = <0x0 0x04080000 0x0 0x4040>;
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interrupts-extended = <&intc GIC_SPI 266 IRQ_TYPE_EDGE_RISING>,
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<&modem_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
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<&modem_smp2p_in 1 IRQ_TYPE_EDGE_RISING>,
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<&modem_smp2p_in 2 IRQ_TYPE_EDGE_RISING>,
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<&modem_smp2p_in 3 IRQ_TYPE_EDGE_RISING>,
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<&modem_smp2p_in 7 IRQ_TYPE_EDGE_RISING>;
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interrupt-names = "wdog", "fatal", "ready", "handover",
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"stop-ack", "shutdown-ack";
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clocks = <&rpmhcc RPMH_CXO_CLK>;
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clock-names = "xo";
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power-domains = <&rpmhpd SC8180X_CX>,
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<&rpmhpd SC8180X_MSS>;
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power-domain-names = "cx", "mss";
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qcom,qmp = <&aoss_qmp>;
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qcom,smem-states = <&modem_smp2p_out 0>;
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qcom,smem-state-names = "stop";
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glink-edge {
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interrupts = <GIC_SPI 449 IRQ_TYPE_EDGE_RISING>;
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label = "modem";
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qcom,remote-pid = <1>;
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mboxes = <&apss_shared 12>;
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};
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};
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remoteproc_cdsp: remoteproc@8300000 {
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compatible = "qcom,sc8180x-cdsp-pas";
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reg = <0x0 0x08300000 0x0 0x4040>;
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interrupts-extended = <&intc GIC_SPI 578 IRQ_TYPE_EDGE_RISING>,
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<&cdsp_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
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<&cdsp_smp2p_in 1 IRQ_TYPE_EDGE_RISING>,
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<&cdsp_smp2p_in 2 IRQ_TYPE_EDGE_RISING>,
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<&cdsp_smp2p_in 3 IRQ_TYPE_EDGE_RISING>;
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interrupt-names = "wdog", "fatal", "ready",
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"handover", "stop-ack";
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clocks = <&rpmhcc RPMH_CXO_CLK>;
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clock-names = "xo";
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power-domains = <&rpmhpd SC8180X_CX>;
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power-domain-names = "cx";
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qcom,qmp = <&aoss_qmp>;
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qcom,smem-states = <&cdsp_smp2p_out 0>;
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qcom,smem-state-names = "stop";
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status = "disabled";
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glink-edge {
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interrupts = <GIC_SPI 574 IRQ_TYPE_EDGE_RISING>;
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label = "cdsp";
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qcom,remote-pid = <5>;
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mboxes = <&apss_shared 4>;
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};
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};
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usb_prim_hsphy: phy@88e2000 {
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compatible = "qcom,sc8180x-usb-hs-phy",
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"qcom,usb-snps-hs-7nm-phy";
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reg = <0 0x088e2000 0 0x400>;
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clocks = <&rpmhcc RPMH_CXO_CLK>;
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clock-names = "ref";
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resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>;
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#phy-cells = <0>;
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status = "disabled";
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};
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usb_sec_hsphy: phy@88e3000 {
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compatible = "qcom,sc8180x-usb-hs-phy",
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"qcom,usb-snps-hs-7nm-phy";
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reg = <0 0x088e3000 0 0x400>;
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clocks = <&rpmhcc RPMH_CXO_CLK>;
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clock-names = "ref";
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resets = <&gcc GCC_QUSB2PHY_SEC_BCR>;
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#phy-cells = <0>;
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status = "disabled";
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};
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usb_prim_qmpphy: phy@88e9000 {
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compatible = "qcom,sc8180x-qmp-usb3-dp-phy";
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reg = <0 0x088e9000 0 0x18c>,
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<0 0x088e8000 0 0x38>,
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<0 0x088ea000 0 0x40>;
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reg-names = "reg-base", "dp_com";
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clocks = <&gcc GCC_USB3_PRIM_PHY_AUX_CLK>,
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<&rpmhcc RPMH_CXO_CLK>,
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<&gcc GCC_USB3_PRIM_CLKREF_CLK>,
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<&gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>;
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clock-names = "aux",
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"ref_clk_src",
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"ref",
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"com_aux";
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resets = <&gcc GCC_USB3_DP_PHY_PRIM_SP0_BCR>,
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<&gcc GCC_USB3_PHY_PRIM_SP0_BCR>;
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reset-names = "phy", "common";
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#clock-cells = <1>;
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#address-cells = <2>;
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#size-cells = <2>;
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ranges;
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status = "disabled";
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usb_prim_ssphy: usb3-phy@88e9200 {
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reg = <0 0x088e9200 0 0x200>,
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<0 0x088e9400 0 0x200>,
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<0 0x088e9c00 0 0x218>,
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<0 0x088e9600 0 0x200>,
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<0 0x088e9800 0 0x200>,
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<0 0x088e9a00 0 0x100>;
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#phy-cells = <0>;
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clocks = <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>;
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clock-names = "pipe0";
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clock-output-names = "usb3_prim_phy_pipe_clk_src";
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};
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usb_prim_dpphy: dp-phy@88ea200 {
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reg = <0 0x088ea200 0 0x200>,
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<0 0x088ea400 0 0x200>,
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<0 0x088eaa00 0 0x200>,
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<0 0x088ea600 0 0x200>,
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<0 0x088ea800 0 0x200>;
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#clock-cells = <1>;
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#phy-cells = <0>;
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};
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};
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usb_sec_qmpphy: phy@88ee000 {
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compatible = "qcom,sc8180x-qmp-usb3-dp-phy";
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reg = <0 0x088ee000 0 0x18c>,
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<0 0x088ed000 0 0x10>,
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<0 0x088ef000 0 0x40>;
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reg-names = "reg-base", "dp_com";
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clocks = <&gcc GCC_USB3_SEC_PHY_AUX_CLK>,
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<&rpmhcc RPMH_CXO_CLK>,
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<&gcc GCC_USB3_SEC_CLKREF_CLK>,
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<&gcc GCC_USB3_SEC_PHY_COM_AUX_CLK>;
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clock-names = "aux",
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"ref_clk_src",
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"ref",
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"com_aux";
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resets = <&gcc GCC_USB3_DP_PHY_SEC_BCR>,
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<&gcc GCC_USB3_PHY_SEC_BCR>;
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reset-names = "phy", "common";
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#clock-cells = <1>;
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#address-cells = <2>;
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#size-cells = <2>;
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ranges;
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status = "disabled";
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usb_sec_ssphy: usb3-phy@88e9200 {
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reg = <0 0x088ee200 0 0x200>,
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<0 0x088ee400 0 0x200>,
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<0 0x088eec00 0 0x218>,
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<0 0x088ee600 0 0x200>,
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<0 0x088ee800 0 0x200>,
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<0 0x088eea00 0 0x100>;
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#phy-cells = <0>;
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clocks = <&gcc GCC_USB3_SEC_PHY_PIPE_CLK>;
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clock-names = "pipe0";
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clock-output-names = "usb3_sec_phy_pipe_clk_src";
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};
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usb_sec_dpphy: dp-phy@88ef200 {
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reg = <0 0x088ef200 0 0x200>,
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<0 0x088ef400 0 0x200>,
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<0 0x088efa00 0 0x200>,
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<0 0x088ef600 0 0x200>,
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<0 0x088ef800 0 0x200>;
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#clock-cells = <1>;
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#phy-cells = <0>;
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clock-output-names = "qmp_dptx1_phy_pll_link_clk",
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"qmp_dptx1_phy_pll_vco_div_clk";
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};
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};
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system-cache-controller@9200000 {
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compatible = "qcom,sc8180x-llcc";
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reg = <0 0x09200000 0 0x50000>, <0 0x09600000 0 0x50000>;
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@ -2241,6 +2433,112 @@
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qcom,bcm-voters = <&apps_bcm_voter>;
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};
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usb_prim: usb@a6f8800 {
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compatible = "qcom,sc8180x-dwc3", "qcom,dwc3";
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reg = <0 0x0a6f8800 0 0x400>;
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interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 486 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 488 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 489 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-names = "hs_phy_irq",
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"ss_phy_irq",
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"dm_hs_phy_irq",
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"dp_hs_phy_irq";
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clocks = <&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>,
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<&gcc GCC_USB30_PRIM_MASTER_CLK>,
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<&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>,
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<&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>,
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<&gcc GCC_USB30_PRIM_SLEEP_CLK>,
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<&gcc GCC_USB3_SEC_CLKREF_CLK>;
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clock-names = "cfg_noc",
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"core",
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"iface",
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"mock_utmi",
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"sleep",
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"xo";
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resets = <&gcc GCC_USB30_PRIM_BCR>;
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power-domains = <&gcc USB30_PRIM_GDSC>;
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interconnects = <&aggre1_noc MASTER_USB3 0 &mc_virt SLAVE_EBI_CH0 0>,
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<&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_USB3 0>;
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interconnect-names = "usb-ddr", "apps-usb";
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assigned-clocks = <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>,
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<&gcc GCC_USB30_PRIM_MASTER_CLK>;
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assigned-clock-rates = <19200000>, <200000000>;
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#address-cells = <2>;
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#size-cells = <2>;
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ranges;
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dma-ranges;
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status = "disabled";
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usb_prim_dwc3: usb@a600000 {
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compatible = "snps,dwc3";
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reg = <0 0x0a600000 0 0xcd00>;
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interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>;
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iommus = <&apps_smmu 0x140 0>;
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snps,dis_u2_susphy_quirk;
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snps,dis_enblslpm_quirk;
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phys = <&usb_prim_hsphy>, <&usb_prim_ssphy>;
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phy-names = "usb2-phy", "usb3-phy";
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};
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};
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usb_sec: usb@a8f8800 {
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compatible = "qcom,sc8180x-dwc3", "qcom,dwc3";
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reg = <0 0x0a8f8800 0 0x400>;
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clocks = <&gcc GCC_CFG_NOC_USB3_SEC_AXI_CLK>,
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<&gcc GCC_USB30_SEC_MASTER_CLK>,
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<&gcc GCC_AGGRE_USB3_SEC_AXI_CLK>,
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<&gcc GCC_USB30_SEC_MOCK_UTMI_CLK>,
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<&gcc GCC_USB30_SEC_SLEEP_CLK>,
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<&gcc GCC_USB3_SEC_CLKREF_CLK>;
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clock-names = "cfg_noc",
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"core",
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"iface",
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"mock_utmi",
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"sleep",
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"xo";
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resets = <&gcc GCC_USB30_SEC_BCR>;
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power-domains = <&gcc USB30_SEC_GDSC>;
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interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 487 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 490 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 491 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-names = "hs_phy_irq", "ss_phy_irq",
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"dm_hs_phy_irq", "dp_hs_phy_irq";
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assigned-clocks = <&gcc GCC_USB30_SEC_MOCK_UTMI_CLK>,
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<&gcc GCC_USB30_SEC_MASTER_CLK>;
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assigned-clock-rates = <19200000>, <200000000>;
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interconnects = <&aggre1_noc MASTER_USB3_1 0 &mc_virt SLAVE_EBI_CH0 0>,
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<&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_USB3_1 0>;
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interconnect-names = "usb-ddr", "apps-usb";
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#address-cells = <2>;
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#size-cells = <2>;
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ranges;
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dma-ranges;
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status = "disabled";
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usb_sec_dwc3: usb@a800000 {
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compatible = "snps,dwc3";
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reg = <0 0x0a800000 0 0xcd00>;
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interrupts = <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>;
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iommus = <&apps_smmu 0x160 0>;
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snps,dis_u2_susphy_quirk;
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snps,dis_enblslpm_quirk;
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phys = <&usb_sec_hsphy>, <&usb_sec_ssphy>;
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phy-names = "usb2-phy", "usb3-phy";
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};
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};
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pdc: interrupt-controller@b220000 {
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compatible = "qcom,sc8180x-pdc", "qcom,pdc";
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reg = <0 0x0b220000 0 0x30000>;
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@ -2416,6 +2714,39 @@
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};
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remoteproc_adsp: remoteproc@17300000 {
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compatible = "qcom,sc8180x-adsp-pas";
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reg = <0x0 0x17300000 0x0 0x4040>;
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interrupts-extended = <&intc GIC_SPI 162 IRQ_TYPE_EDGE_RISING>,
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<&adsp_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
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<&adsp_smp2p_in 1 IRQ_TYPE_EDGE_RISING>,
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<&adsp_smp2p_in 2 IRQ_TYPE_EDGE_RISING>,
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<&adsp_smp2p_in 3 IRQ_TYPE_EDGE_RISING>;
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interrupt-names = "wdog", "fatal", "ready",
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"handover", "stop-ack";
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clocks = <&rpmhcc RPMH_CXO_CLK>;
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clock-names = "xo";
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power-domains = <&rpmhpd SC8180X_CX>;
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power-domain-names = "cx";
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qcom,qmp = <&aoss_qmp>;
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qcom,smem-states = <&adsp_smp2p_out 0>;
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qcom,smem-state-names = "stop";
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status = "disabled";
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remoteproc_adsp_glink: glink-edge {
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interrupts = <GIC_SPI 156 IRQ_TYPE_EDGE_RISING>;
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label = "lpass";
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qcom,remote-pid = <2>;
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mboxes = <&apss_shared 8>;
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};
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};
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intc: interrupt-controller@17a00000 {
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compatible = "arm,gic-v3";
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interrupt-controller;
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@ -2615,6 +2946,30 @@
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#clock-cells = <1>;
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};
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wifi: wifi@18800000 {
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compatible = "qcom,wcn3990-wifi";
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reg = <0 0x18800000 0 0x800000>;
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reg-names = "membase";
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clock-names = "cxo_ref_clk_pin";
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clocks = <&rpmhcc RPMH_RF_CLK2>;
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interrupts = <GIC_SPI 414 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 415 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 416 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 417 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 418 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 419 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 420 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 422 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 424 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 425 IRQ_TYPE_LEVEL_HIGH>;
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iommus = <&apps_smmu 0x0640 0x1>;
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qcom,msa-fixed-perm;
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status = "disabled";
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};
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};
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thermal-zones {
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cpu0-thermal {
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polling-delay-passive = <250>;
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