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ARM: dts: Group omap3 CM_CLKSEL_CORE clocks
The clksel related registers on omap3 cause unique_unit_address and node_name_chars_strict warnings with the W=1 or W=2 make flags enabled. With the clock drivers updated, we can now avoid most of these warnings by grouping the TI component clocks using the TI clksel binding, and with the use of clock-output-names property to avoid non-standard node names for the clocks. Signed-off-by: Tony Lindgren <tony@atomide.com>
This commit is contained in:
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4e28ab96e3
commit
b0985e0278
3 changed files with 78 additions and 56 deletions
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@ -77,13 +77,30 @@ ssi_ssr_gate_fck_3430es1: clock-ssi-ssr-gate-fck-3430es1 {
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};
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};
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ssi_ssr_div_fck_3430es1: ssi_ssr_div_fck_3430es1@a40 {
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#clock-cells = <0>;
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compatible = "ti,composite-divider-clock";
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clocks = <&corex2_fck>;
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ti,bit-shift = <8>;
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reg = <0x0a40>;
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ti,dividers = <0>, <1>, <2>, <3>, <4>, <0>, <6>, <0>, <8>;
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clock@a40 {
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compatible = "ti,clksel";
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reg = <0xa40>;
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#clock-cells = <2>;
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#address-cells = <0>;
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ssi_ssr_div_fck_3430es1: clock-ssi-ssr-div-fck-3430es1 {
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#clock-cells = <0>;
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compatible = "ti,composite-divider-clock";
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clock-output-names = "ssi_ssr_div_fck_3430es1";
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clocks = <&corex2_fck>;
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ti,bit-shift = <8>;
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ti,dividers = <0>, <1>, <2>, <3>, <4>, <0>, <6>, <0>, <8>;
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};
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usb_l4_div_ick: clock-usb-l4-div-ick {
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#clock-cells = <0>;
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compatible = "ti,composite-divider-clock";
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clock-output-names = "usb_l4_div_ick";
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clocks = <&l4_ick>;
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ti,bit-shift = <4>;
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ti,max-div = <1>;
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ti,index-starts-at-one;
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};
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};
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ssi_ssr_fck: ssi_ssr_fck_3430es1 {
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@ -147,16 +164,6 @@ ssi_l4_ick: ssi_l4_ick {
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clock-div = <1>;
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};
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usb_l4_div_ick: usb_l4_div_ick@a40 {
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#clock-cells = <0>;
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compatible = "ti,composite-divider-clock";
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clocks = <&l4_ick>;
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ti,bit-shift = <4>;
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ti,max-div = <1>;
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reg = <0x0a40>;
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ti,index-starts-at-one;
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};
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usb_l4_ick: usb_l4_ick {
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#clock-cells = <0>;
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compatible = "ti,composite-clock";
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@ -20,13 +20,20 @@ ssi_ssr_gate_fck_3430es2: clock-ssi-ssr-gate-fck-3430es2 {
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};
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};
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ssi_ssr_div_fck_3430es2: ssi_ssr_div_fck_3430es2@a40 {
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#clock-cells = <0>;
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compatible = "ti,composite-divider-clock";
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clocks = <&corex2_fck>;
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ti,bit-shift = <8>;
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reg = <0x0a40>;
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ti,dividers = <0>, <1>, <2>, <3>, <4>, <0>, <6>, <0>, <8>;
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clock@a40 {
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compatible = "ti,clksel";
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reg = <0xa40>;
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#clock-cells = <2>;
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#address-cells = <0>;
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ssi_ssr_div_fck_3430es2: clock-ssi-ssr-div-fck-3430es2 {
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#clock-cells = <0>;
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compatible = "ti,composite-divider-clock";
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clock-output-names = "ssi_ssr_div_fck_3430es2";
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clocks = <&corex2_fck>;
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ti,bit-shift = <8>;
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ti,dividers = <0>, <1>, <2>, <3>, <4>, <0>, <6>, <0>, <8>;
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};
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};
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ssi_ssr_fck: ssi_ssr_fck_3430es2 {
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@ -574,23 +574,47 @@ emu_mpu_alwon_ck: emu_mpu_alwon_ck {
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clock-div = <1>;
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};
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l3_ick: l3_ick@a40 {
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#clock-cells = <0>;
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compatible = "ti,divider-clock";
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clocks = <&core_ck>;
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ti,max-div = <3>;
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reg = <0x0a40>;
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ti,index-starts-at-one;
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};
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/* CM_CLKSEL_CORE */
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clock@a40 {
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compatible = "ti,clksel";
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reg = <0xa40>;
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#clock-cells = <2>;
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#address-cells = <0>;
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l4_ick: l4_ick@a40 {
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#clock-cells = <0>;
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compatible = "ti,divider-clock";
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clocks = <&l3_ick>;
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ti,bit-shift = <2>;
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ti,max-div = <3>;
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reg = <0x0a40>;
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ti,index-starts-at-one;
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l3_ick: clock-l3-ick {
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#clock-cells = <0>;
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compatible = "ti,divider-clock";
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clock-output-names = "l3_ick";
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clocks = <&core_ck>;
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ti,max-div = <3>;
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ti,index-starts-at-one;
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};
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l4_ick: clock-l4-ick {
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#clock-cells = <0>;
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compatible = "ti,divider-clock";
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clock-output-names = "l4_ick";
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clocks = <&l3_ick>;
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ti,bit-shift = <2>;
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ti,max-div = <3>;
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ti,index-starts-at-one;
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};
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gpt10_mux_fck: clock-gpt10-mux-fck {
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#clock-cells = <0>;
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compatible = "ti,composite-mux-clock";
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clock-output-names = "gpt10_mux_fck";
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clocks = <&omap_32k_fck>, <&sys_ck>;
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ti,bit-shift = <6>;
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};
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gpt11_mux_fck: clock-gpt11-mux-fck {
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#clock-cells = <0>;
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compatible = "ti,composite-mux-clock";
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clock-output-names = "gpt11_mux_fck";
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clocks = <&omap_32k_fck>, <&sys_ck>;
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ti,bit-shift = <7>;
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};
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};
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rm_ick: rm_ick@c40 {
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@ -739,28 +763,12 @@ hdq_fck: clock-hdq-fck {
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};
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};
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gpt10_mux_fck: gpt10_mux_fck@a40 {
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#clock-cells = <0>;
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compatible = "ti,composite-mux-clock";
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clocks = <&omap_32k_fck>, <&sys_ck>;
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ti,bit-shift = <6>;
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reg = <0x0a40>;
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};
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gpt10_fck: gpt10_fck {
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#clock-cells = <0>;
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compatible = "ti,composite-clock";
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clocks = <&gpt10_gate_fck>, <&gpt10_mux_fck>;
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};
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gpt11_mux_fck: gpt11_mux_fck@a40 {
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#clock-cells = <0>;
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compatible = "ti,composite-mux-clock";
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clocks = <&omap_32k_fck>, <&sys_ck>;
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ti,bit-shift = <7>;
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reg = <0x0a40>;
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};
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gpt11_fck: gpt11_fck {
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#clock-cells = <0>;
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compatible = "ti,composite-clock";
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