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iio: imu: inv_icm42600: Fix alignment for DMA safety in buffer code.

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Second fix for this driver due to different introducing patches.

____cacheline_aligned is an insufficient guarantee for non-coherent DMA
on platforms with 128 byte cachelines above L1.  Switch to the updated
IIO_DMA_MINALIGN definition.

Fixes: 7f85e42a6c ("iio: imu: inv_icm42600: add buffer support in iio devices")
Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
Cc: Jean-Baptiste Maneyrol <jmaneyrol@invensense.com>
Acked-by: Jean-Baptiste Maneyrol <jean-baptiste.maneyrol@tdk.com>
Acked-by: Nuno Sá <nuno.sa@analog.com>
Link: https://lore.kernel.org/r/20220508175712.647246-79-jic23@kernel.org
This commit is contained in:
Jonathan Cameron 2022-05-08 18:56:58 +01:00
parent 848847702b
commit b0aa05065a
1 changed files with 1 additions and 1 deletions
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2
drivers/iio/imu/inv_icm42600/inv_icm42600_buffer.h
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@ -39,7 +39,7 @@ struct inv_icm42600_fifo {
size_t accel;
size_t total;
} nb;
uint8_t data[2080] ____cacheline_aligned;
uint8_t data[2080] __aligned(IIO_DMA_MINALIGN);
};
/* FIFO data packet */