mirror of
https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git
synced 2024-10-29 23:53:32 +00:00
Merge remote-tracking branches 'asoc/topic/rl6231', 'asoc/topic/rockchip', 'asoc/topic/rt286', 'asoc/topic/rt5640' and 'asoc/topic/rt5645' into asoc-next
This commit is contained in:
Mark Brown
commit
b0ae27c477
11 changed files with 847 additions and 73 deletions
37
Documentation/devicetree/bindings/sound/rockchip-i2s.txt
Normal file
37
Documentation/devicetree/bindings/sound/rockchip-i2s.txt
Normal file
|
|
@ -0,0 +1,37 @@
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|||
* Rockchip I2S controller
|
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|
||||
The I2S bus (Inter-IC sound bus) is a serial link for digital
|
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audio data transfer between devices in the system.
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|
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Required properties:
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- compatible: should be one of the followings
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- "rockchip,rk3066-i2s": for rk3066
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- "rockchip,rk3188-i2s", "rockchip,rk3066-i2s": for rk3188
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- "rockchip,rk3288-i2s", "rockchip,rk3066-i2s": for rk3288
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- reg: physical base address of the controller and length of memory mapped
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region.
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- interrupts: should contain the I2S interrupt.
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- #address-cells: should be 1.
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- #size-cells: should be 0.
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- dmas: DMA specifiers for tx and rx dma. See the DMA client binding,
|
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Documentation/devicetree/bindings/dma/dma.txt
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- dma-names: should include "tx" and "rx".
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- clocks: a list of phandle + clock-specifer pairs, one for each entry in clock-names.
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- clock-names: should contain followings:
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- "i2s_hclk": clock for I2S BUS
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- "i2s_clk" : clock for I2S controller
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|
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Example for rk3288 I2S controller:
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i2s@ff890000 {
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compatible = "rockchip,rk3288-i2s", "rockchip,rk3066-i2s";
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reg = <0xff890000 0x10000>;
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interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
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#address-cells = <1>;
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#size-cells = <0>;
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dmas = <&pdma1 0>, <&pdma1 1>;
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dma-names = "rx", "tx";
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clock-names = "i2s_hclk", "i2s_clk";
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clocks = <&cru HCLK_I2S0>, <&cru SCLK_I2S0>;
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};
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|
|
@ -47,6 +47,7 @@ source "sound/soc/kirkwood/Kconfig"
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|||
source "sound/soc/intel/Kconfig"
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source "sound/soc/mxs/Kconfig"
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source "sound/soc/pxa/Kconfig"
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source "sound/soc/rockchip/Kconfig"
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source "sound/soc/samsung/Kconfig"
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source "sound/soc/s6000/Kconfig"
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source "sound/soc/sh/Kconfig"
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|
|
|
|||
|
|
@ -24,6 +24,7 @@ obj-$(CONFIG_SND_SOC) += nuc900/
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|||
obj-$(CONFIG_SND_SOC) += omap/
|
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obj-$(CONFIG_SND_SOC) += kirkwood/
|
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obj-$(CONFIG_SND_SOC) += pxa/
|
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obj-$(CONFIG_SND_SOC) += rockchip/
|
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obj-$(CONFIG_SND_SOC) += samsung/
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obj-$(CONFIG_SND_SOC) += s6000/
|
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obj-$(CONFIG_SND_SOC) += sh/
|
||||
|
|
|
|||
|
|
@ -11,25 +11,6 @@
|
|||
*/
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|
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#include <linux/module.h>
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#include <linux/moduleparam.h>
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#include <linux/init.h>
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#include <linux/delay.h>
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#include <linux/pm.h>
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#include <linux/gpio.h>
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#include <linux/i2c.h>
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#include <linux/regmap.h>
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#include <linux/of.h>
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#include <linux/of_gpio.h>
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#include <linux/platform_device.h>
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#include <linux/spi/spi.h>
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#include <linux/acpi.h>
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#include <sound/core.h>
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#include <sound/pcm.h>
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#include <sound/pcm_params.h>
|
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#include <sound/soc.h>
|
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#include <sound/soc-dapm.h>
|
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#include <sound/initval.h>
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#include <sound/tlv.h>
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|
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#include "rl6231.h"
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|
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|
|
|
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|
|
@ -36,7 +36,6 @@
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|||
|
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struct rt286_priv {
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struct regmap *regmap;
|
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struct snd_soc_codec *codec;
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struct rt286_platform_data pdata;
|
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struct i2c_client *i2c;
|
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struct snd_soc_jack *jack;
|
||||
|
|
@ -295,9 +294,8 @@ static int rt286_support_power_controls[] = {
|
|||
};
|
||||
#define RT286_POWER_REG_LEN ARRAY_SIZE(rt286_support_power_controls)
|
||||
|
||||
static int rt286_jack_detect(struct snd_soc_codec *codec, bool *hp, bool *mic)
|
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static int rt286_jack_detect(struct rt286_priv *rt286, bool *hp, bool *mic)
|
||||
{
|
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struct rt286_priv *rt286 = snd_soc_codec_get_drvdata(codec);
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unsigned int val, buf;
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int i;
|
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|
||||
|
|
@ -305,23 +303,23 @@ static int rt286_jack_detect(struct snd_soc_codec *codec, bool *hp, bool *mic)
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|||
*mic = false;
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|
||||
if (rt286->pdata.cbj_en) {
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buf = snd_soc_read(codec, RT286_GET_HP_SENSE);
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regmap_read(rt286->regmap, RT286_GET_HP_SENSE, &buf);
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*hp = buf & 0x80000000;
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if (*hp) {
|
||||
/* power on HV,VERF */
|
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snd_soc_update_bits(codec,
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regmap_update_bits(rt286->regmap,
|
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RT286_POWER_CTRL1, 0x1001, 0x0);
|
||||
/* power LDO1 */
|
||||
snd_soc_update_bits(codec,
|
||||
regmap_update_bits(rt286->regmap,
|
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RT286_POWER_CTRL2, 0x4, 0x4);
|
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snd_soc_write(codec, RT286_SET_MIC1, 0x24);
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val = snd_soc_read(codec, RT286_CBJ_CTRL2);
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regmap_write(rt286->regmap, RT286_SET_MIC1, 0x24);
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regmap_read(rt286->regmap, RT286_CBJ_CTRL2, &val);
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msleep(200);
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i = 40;
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while (((val & 0x0800) == 0) && (i > 0)) {
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val = snd_soc_read(codec,
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RT286_CBJ_CTRL2);
|
||||
regmap_read(rt286->regmap,
|
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RT286_CBJ_CTRL2, &val);
|
||||
i--;
|
||||
msleep(20);
|
||||
}
|
||||
|
|
@ -329,53 +327,53 @@ static int rt286_jack_detect(struct snd_soc_codec *codec, bool *hp, bool *mic)
|
|||
if (0x0400 == (val & 0x0700)) {
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*mic = false;
|
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|
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snd_soc_write(codec,
|
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regmap_write(rt286->regmap,
|
||||
RT286_SET_MIC1, 0x20);
|
||||
/* power off HV,VERF */
|
||||
snd_soc_update_bits(codec,
|
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regmap_update_bits(rt286->regmap,
|
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RT286_POWER_CTRL1, 0x1001, 0x1001);
|
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snd_soc_update_bits(codec,
|
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regmap_update_bits(rt286->regmap,
|
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RT286_A_BIAS_CTRL3, 0xc000, 0x0000);
|
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snd_soc_update_bits(codec,
|
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regmap_update_bits(rt286->regmap,
|
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RT286_CBJ_CTRL1, 0x0030, 0x0000);
|
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snd_soc_update_bits(codec,
|
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regmap_update_bits(rt286->regmap,
|
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RT286_A_BIAS_CTRL2, 0xc000, 0x0000);
|
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} else if ((0x0200 == (val & 0x0700)) ||
|
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(0x0100 == (val & 0x0700))) {
|
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*mic = true;
|
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snd_soc_update_bits(codec,
|
||||
regmap_update_bits(rt286->regmap,
|
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RT286_A_BIAS_CTRL3, 0xc000, 0x8000);
|
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snd_soc_update_bits(codec,
|
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regmap_update_bits(rt286->regmap,
|
||||
RT286_CBJ_CTRL1, 0x0030, 0x0020);
|
||||
snd_soc_update_bits(codec,
|
||||
regmap_update_bits(rt286->regmap,
|
||||
RT286_A_BIAS_CTRL2, 0xc000, 0x8000);
|
||||
} else {
|
||||
*mic = false;
|
||||
}
|
||||
|
||||
snd_soc_update_bits(codec,
|
||||
regmap_update_bits(rt286->regmap,
|
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RT286_MISC_CTRL1,
|
||||
0x0060, 0x0000);
|
||||
} else {
|
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snd_soc_update_bits(codec,
|
||||
regmap_update_bits(rt286->regmap,
|
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RT286_MISC_CTRL1,
|
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0x0060, 0x0020);
|
||||
snd_soc_update_bits(codec,
|
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regmap_update_bits(rt286->regmap,
|
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RT286_A_BIAS_CTRL3,
|
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0xc000, 0x8000);
|
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snd_soc_update_bits(codec,
|
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regmap_update_bits(rt286->regmap,
|
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RT286_CBJ_CTRL1,
|
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0x0030, 0x0020);
|
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snd_soc_update_bits(codec,
|
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regmap_update_bits(rt286->regmap,
|
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RT286_A_BIAS_CTRL2,
|
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0xc000, 0x8000);
|
||||
|
||||
*mic = false;
|
||||
}
|
||||
} else {
|
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buf = snd_soc_read(codec, RT286_GET_HP_SENSE);
|
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regmap_read(rt286->regmap, RT286_GET_HP_SENSE, &buf);
|
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*hp = buf & 0x80000000;
|
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buf = snd_soc_read(codec, RT286_GET_MIC1_SENSE);
|
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regmap_read(rt286->regmap, RT286_GET_MIC1_SENSE, &buf);
|
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*mic = buf & 0x80000000;
|
||||
}
|
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|
||||
|
|
@ -390,7 +388,7 @@ static void rt286_jack_detect_work(struct work_struct *work)
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bool hp = false;
|
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bool mic = false;
|
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|
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rt286_jack_detect(rt286->codec, &hp, &mic);
|
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rt286_jack_detect(rt286, &hp, &mic);
|
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|
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if (hp == true)
|
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status |= SND_JACK_HEADPHONE;
|
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|
|
@ -940,11 +938,10 @@ static irqreturn_t rt286_irq(int irq, void *data)
|
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bool mic = false;
|
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int status = 0;
|
||||
|
||||
rt286_jack_detect(rt286->codec, &hp, &mic);
|
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rt286_jack_detect(rt286, &hp, &mic);
|
||||
|
||||
/* Clear IRQ */
|
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snd_soc_update_bits(rt286->codec,
|
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RT286_IRQ_CTRL, 0x1, 0x1);
|
||||
regmap_update_bits(rt286->regmap, RT286_IRQ_CTRL, 0x1, 0x1);
|
||||
|
||||
if (hp == true)
|
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status |= SND_JACK_HEADPHONE;
|
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|
|
@ -965,7 +962,16 @@ static int rt286_probe(struct snd_soc_codec *codec)
|
|||
struct rt286_priv *rt286 = snd_soc_codec_get_drvdata(codec);
|
||||
|
||||
codec->dapm.bias_level = SND_SOC_BIAS_OFF;
|
||||
rt286->codec = codec;
|
||||
|
||||
if (rt286->i2c->irq) {
|
||||
regmap_update_bits(rt286->regmap,
|
||||
RT286_IRQ_CTRL, 0x2, 0x2);
|
||||
|
||||
INIT_DELAYED_WORK(&rt286->jack_detect_work,
|
||||
rt286_jack_detect_work);
|
||||
schedule_delayed_work(&rt286->jack_detect_work,
|
||||
msecs_to_jiffies(1250));
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
|
@ -1171,14 +1177,6 @@ static int rt286_i2c_probe(struct i2c_client *i2c,
|
|||
regmap_update_bits(rt286->regmap, RT286_DEPOP_CTRL4, 0x00ff, 0x003f);
|
||||
|
||||
if (rt286->i2c->irq) {
|
||||
regmap_update_bits(rt286->regmap,
|
||||
RT286_IRQ_CTRL, 0x2, 0x2);
|
||||
|
||||
INIT_DELAYED_WORK(&rt286->jack_detect_work,
|
||||
rt286_jack_detect_work);
|
||||
schedule_delayed_work(&rt286->jack_detect_work,
|
||||
msecs_to_jiffies(1250));
|
||||
|
||||
ret = request_threaded_irq(rt286->i2c->irq, NULL, rt286_irq,
|
||||
IRQF_TRIGGER_HIGH | IRQF_ONESHOT, "rt286", rt286);
|
||||
if (ret != 0) {
|
||||
|
|
|
|||
|
|
@ -2215,14 +2215,8 @@ static int rt5640_i2c_probe(struct i2c_client *i2c,
|
|||
|
||||
rt5640->hp_mute = 1;
|
||||
|
||||
ret = snd_soc_register_codec(&i2c->dev, &soc_codec_dev_rt5640,
|
||||
return snd_soc_register_codec(&i2c->dev, &soc_codec_dev_rt5640,
|
||||
rt5640_dai, ARRAY_SIZE(rt5640_dai));
|
||||
if (ret < 0)
|
||||
goto err;
|
||||
|
||||
return 0;
|
||||
err:
|
||||
return ret;
|
||||
}
|
||||
|
||||
static int rt5640_i2c_remove(struct i2c_client *i2c)
|
||||
|
|
|
|||
|
|
@ -2345,14 +2345,8 @@ static int rt5645_i2c_probe(struct i2c_client *i2c,
|
|||
|
||||
}
|
||||
|
||||
ret = snd_soc_register_codec(&i2c->dev, &soc_codec_dev_rt5645,
|
||||
return snd_soc_register_codec(&i2c->dev, &soc_codec_dev_rt5645,
|
||||
rt5645_dai, ARRAY_SIZE(rt5645_dai));
|
||||
if (ret < 0)
|
||||
goto err;
|
||||
|
||||
return 0;
|
||||
err:
|
||||
return ret;
|
||||
}
|
||||
|
||||
static int rt5645_i2c_remove(struct i2c_client *i2c)
|
||||
|
|
|
|||
12
sound/soc/rockchip/Kconfig
Normal file
12
sound/soc/rockchip/Kconfig
Normal file
|
|
@ -0,0 +1,12 @@
|
|||
config SND_SOC_ROCKCHIP
|
||||
tristate "ASoC support for Rockchip"
|
||||
depends on COMPILE_TEST || ARCH_ROCKCHIP
|
||||
select SND_SOC_GENERIC_DMAENGINE_PCM
|
||||
select SND_ROCKCHIP_I2S
|
||||
help
|
||||
Say Y or M if you want to add support for codecs attached to
|
||||
the Rockchip SoCs' Audio interfaces. You will also need to
|
||||
select the audio interfaces to support below.
|
||||
|
||||
config SND_ROCKCHIP_I2S
|
||||
tristate
|
||||
4
sound/soc/rockchip/Makefile
Normal file
4
sound/soc/rockchip/Makefile
Normal file
|
|
@ -0,0 +1,4 @@
|
|||
# ROCKCHIP Platform Support
|
||||
snd-soc-i2s-objs := rockchip_i2s.o
|
||||
|
||||
obj-$(CONFIG_SND_ROCKCHIP_I2S) += snd-soc-i2s.o
|
||||
529
sound/soc/rockchip/rockchip_i2s.c
Normal file
529
sound/soc/rockchip/rockchip_i2s.c
Normal file
|
|
@ -0,0 +1,529 @@
|
|||
/* sound/soc/rockchip/rockchip_i2s.c
|
||||
*
|
||||
* ALSA SoC Audio Layer - Rockchip I2S Controller driver
|
||||
*
|
||||
* Copyright (c) 2014 Rockchip Electronics Co. Ltd.
|
||||
* Author: Jianqun <jay.xu@rock-chips.com>
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License version 2 as
|
||||
* published by the Free Software Foundation.
|
||||
*/
|
||||
|
||||
#include <linux/module.h>
|
||||
#include <linux/delay.h>
|
||||
#include <linux/of_gpio.h>
|
||||
#include <linux/clk.h>
|
||||
#include <linux/pm_runtime.h>
|
||||
#include <linux/regmap.h>
|
||||
#include <sound/pcm_params.h>
|
||||
#include <sound/dmaengine_pcm.h>
|
||||
|
||||
#include "rockchip_i2s.h"
|
||||
|
||||
#define DRV_NAME "rockchip-i2s"
|
||||
|
||||
struct rk_i2s_dev {
|
||||
struct device *dev;
|
||||
|
||||
struct clk *hclk;
|
||||
struct clk *mclk;
|
||||
|
||||
struct snd_dmaengine_dai_dma_data capture_dma_data;
|
||||
struct snd_dmaengine_dai_dma_data playback_dma_data;
|
||||
|
||||
struct regmap *regmap;
|
||||
|
||||
/*
|
||||
* Used to indicate the tx/rx status.
|
||||
* I2S controller hopes to start the tx and rx together,
|
||||
* also to stop them when they are both try to stop.
|
||||
*/
|
||||
bool tx_start;
|
||||
bool rx_start;
|
||||
};
|
||||
|
||||
static int i2s_runtime_suspend(struct device *dev)
|
||||
{
|
||||
struct rk_i2s_dev *i2s = dev_get_drvdata(dev);
|
||||
|
||||
clk_disable_unprepare(i2s->mclk);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int i2s_runtime_resume(struct device *dev)
|
||||
{
|
||||
struct rk_i2s_dev *i2s = dev_get_drvdata(dev);
|
||||
int ret;
|
||||
|
||||
ret = clk_prepare_enable(i2s->mclk);
|
||||
if (ret) {
|
||||
dev_err(i2s->dev, "clock enable failed %d\n", ret);
|
||||
return ret;
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static inline struct rk_i2s_dev *to_info(struct snd_soc_dai *dai)
|
||||
{
|
||||
return snd_soc_dai_get_drvdata(dai);
|
||||
}
|
||||
|
||||
static void rockchip_snd_txctrl(struct rk_i2s_dev *i2s, int on)
|
||||
{
|
||||
unsigned int val = 0;
|
||||
int retry = 10;
|
||||
|
||||
if (on) {
|
||||
regmap_update_bits(i2s->regmap, I2S_DMACR,
|
||||
I2S_DMACR_TDE_ENABLE, I2S_DMACR_TDE_ENABLE);
|
||||
|
||||
regmap_update_bits(i2s->regmap, I2S_XFER,
|
||||
I2S_XFER_TXS_START | I2S_XFER_RXS_START,
|
||||
I2S_XFER_TXS_START | I2S_XFER_RXS_START);
|
||||
|
||||
i2s->tx_start = true;
|
||||
} else {
|
||||
i2s->tx_start = false;
|
||||
|
||||
regmap_update_bits(i2s->regmap, I2S_DMACR,
|
||||
I2S_DMACR_TDE_ENABLE, I2S_DMACR_TDE_DISABLE);
|
||||
|
||||
if (!i2s->rx_start) {
|
||||
regmap_update_bits(i2s->regmap, I2S_XFER,
|
||||
I2S_XFER_TXS_START |
|
||||
I2S_XFER_RXS_START,
|
||||
I2S_XFER_TXS_STOP |
|
||||
I2S_XFER_RXS_STOP);
|
||||
|
||||
regmap_update_bits(i2s->regmap, I2S_CLR,
|
||||
I2S_CLR_TXC | I2S_CLR_RXC,
|
||||
I2S_CLR_TXC | I2S_CLR_RXC);
|
||||
|
||||
regmap_read(i2s->regmap, I2S_CLR, &val);
|
||||
|
||||
/* Should wait for clear operation to finish */
|
||||
while (val) {
|
||||
regmap_read(i2s->regmap, I2S_CLR, &val);
|
||||
retry--;
|
||||
if (!retry)
|
||||
dev_warn(i2s->dev, "fail to clear\n");
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
static void rockchip_snd_rxctrl(struct rk_i2s_dev *i2s, int on)
|
||||
{
|
||||
unsigned int val = 0;
|
||||
int retry = 10;
|
||||
|
||||
if (on) {
|
||||
regmap_update_bits(i2s->regmap, I2S_DMACR,
|
||||
I2S_DMACR_RDE_ENABLE, I2S_DMACR_RDE_ENABLE);
|
||||
|
||||
regmap_update_bits(i2s->regmap, I2S_XFER,
|
||||
I2S_XFER_TXS_START | I2S_XFER_RXS_START,
|
||||
I2S_XFER_TXS_START | I2S_XFER_RXS_START);
|
||||
|
||||
i2s->rx_start = true;
|
||||
} else {
|
||||
i2s->rx_start = false;
|
||||
|
||||
regmap_update_bits(i2s->regmap, I2S_DMACR,
|
||||
I2S_DMACR_RDE_ENABLE, I2S_DMACR_RDE_DISABLE);
|
||||
|
||||
if (!i2s->tx_start) {
|
||||
regmap_update_bits(i2s->regmap, I2S_XFER,
|
||||
I2S_XFER_TXS_START |
|
||||
I2S_XFER_RXS_START,
|
||||
I2S_XFER_TXS_STOP |
|
||||
I2S_XFER_RXS_STOP);
|
||||
|
||||
regmap_update_bits(i2s->regmap, I2S_CLR,
|
||||
I2S_CLR_TXC | I2S_CLR_RXC,
|
||||
I2S_CLR_TXC | I2S_CLR_RXC);
|
||||
|
||||
regmap_read(i2s->regmap, I2S_CLR, &val);
|
||||
|
||||
/* Should wait for clear operation to finish */
|
||||
while (val) {
|
||||
regmap_read(i2s->regmap, I2S_CLR, &val);
|
||||
retry--;
|
||||
if (!retry)
|
||||
dev_warn(i2s->dev, "fail to clear\n");
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
static int rockchip_i2s_set_fmt(struct snd_soc_dai *cpu_dai,
|
||||
unsigned int fmt)
|
||||
{
|
||||
struct rk_i2s_dev *i2s = to_info(cpu_dai);
|
||||
unsigned int mask = 0, val = 0;
|
||||
|
||||
mask = I2S_CKR_MSS_SLAVE;
|
||||
switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
|
||||
case SND_SOC_DAIFMT_CBS_CFS:
|
||||
val = I2S_CKR_MSS_SLAVE;
|
||||
break;
|
||||
case SND_SOC_DAIFMT_CBM_CFM:
|
||||
val = I2S_CKR_MSS_MASTER;
|
||||
break;
|
||||
default:
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
regmap_update_bits(i2s->regmap, I2S_CKR, mask, val);
|
||||
|
||||
mask = I2S_TXCR_IBM_MASK;
|
||||
switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
|
||||
case SND_SOC_DAIFMT_RIGHT_J:
|
||||
val = I2S_TXCR_IBM_RSJM;
|
||||
break;
|
||||
case SND_SOC_DAIFMT_LEFT_J:
|
||||
val = I2S_TXCR_IBM_LSJM;
|
||||
break;
|
||||
case SND_SOC_DAIFMT_I2S:
|
||||
val = I2S_TXCR_IBM_NORMAL;
|
||||
break;
|
||||
default:
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
regmap_update_bits(i2s->regmap, I2S_TXCR, mask, val);
|
||||
|
||||
mask = I2S_RXCR_IBM_MASK;
|
||||
switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
|
||||
case SND_SOC_DAIFMT_RIGHT_J:
|
||||
val = I2S_RXCR_IBM_RSJM;
|
||||
break;
|
||||
case SND_SOC_DAIFMT_LEFT_J:
|
||||
val = I2S_RXCR_IBM_LSJM;
|
||||
break;
|
||||
case SND_SOC_DAIFMT_I2S:
|
||||
val = I2S_RXCR_IBM_NORMAL;
|
||||
break;
|
||||
default:
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
regmap_update_bits(i2s->regmap, I2S_RXCR, mask, val);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int rockchip_i2s_hw_params(struct snd_pcm_substream *substream,
|
||||
struct snd_pcm_hw_params *params,
|
||||
struct snd_soc_dai *dai)
|
||||
{
|
||||
struct rk_i2s_dev *i2s = to_info(dai);
|
||||
unsigned int val = 0;
|
||||
|
||||
switch (params_format(params)) {
|
||||
case SNDRV_PCM_FORMAT_S8:
|
||||
val |= I2S_TXCR_VDW(8);
|
||||
break;
|
||||
case SNDRV_PCM_FORMAT_S16_LE:
|
||||
val |= I2S_TXCR_VDW(16);
|
||||
break;
|
||||
case SNDRV_PCM_FORMAT_S20_3LE:
|
||||
val |= I2S_TXCR_VDW(20);
|
||||
break;
|
||||
case SNDRV_PCM_FORMAT_S24_LE:
|
||||
val |= I2S_TXCR_VDW(24);
|
||||
break;
|
||||
default:
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
regmap_update_bits(i2s->regmap, I2S_TXCR, I2S_TXCR_VDW_MASK, val);
|
||||
regmap_update_bits(i2s->regmap, I2S_RXCR, I2S_RXCR_VDW_MASK, val);
|
||||
|
||||
if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
|
||||
dai->playback_dma_data = &i2s->playback_dma_data;
|
||||
regmap_update_bits(i2s->regmap, I2S_DMACR, I2S_DMACR_TDL_MASK,
|
||||
I2S_DMACR_TDL(1) | I2S_DMACR_TDE_ENABLE);
|
||||
} else {
|
||||
dai->capture_dma_data = &i2s->capture_dma_data;
|
||||
regmap_update_bits(i2s->regmap, I2S_DMACR, I2S_DMACR_RDL_MASK,
|
||||
I2S_DMACR_RDL(1) | I2S_DMACR_RDE_ENABLE);
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int rockchip_i2s_trigger(struct snd_pcm_substream *substream,
|
||||
int cmd, struct snd_soc_dai *dai)
|
||||
{
|
||||
struct rk_i2s_dev *i2s = to_info(dai);
|
||||
int ret = 0;
|
||||
|
||||
switch (cmd) {
|
||||
case SNDRV_PCM_TRIGGER_START:
|
||||
case SNDRV_PCM_TRIGGER_RESUME:
|
||||
case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
|
||||
if (substream->stream == SNDRV_PCM_STREAM_CAPTURE)
|
||||
rockchip_snd_rxctrl(i2s, 1);
|
||||
else
|
||||
rockchip_snd_txctrl(i2s, 1);
|
||||
break;
|
||||
case SNDRV_PCM_TRIGGER_SUSPEND:
|
||||
case SNDRV_PCM_TRIGGER_STOP:
|
||||
case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
|
||||
if (substream->stream == SNDRV_PCM_STREAM_CAPTURE)
|
||||
rockchip_snd_rxctrl(i2s, 0);
|
||||
else
|
||||
rockchip_snd_txctrl(i2s, 0);
|
||||
break;
|
||||
default:
|
||||
ret = -EINVAL;
|
||||
break;
|
||||
}
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
static int rockchip_i2s_set_sysclk(struct snd_soc_dai *cpu_dai, int clk_id,
|
||||
unsigned int freq, int dir)
|
||||
{
|
||||
struct rk_i2s_dev *i2s = to_info(cpu_dai);
|
||||
int ret;
|
||||
|
||||
ret = clk_set_rate(i2s->mclk, freq);
|
||||
if (ret)
|
||||
dev_err(i2s->dev, "Fail to set mclk %d\n", ret);
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
static const struct snd_soc_dai_ops rockchip_i2s_dai_ops = {
|
||||
.hw_params = rockchip_i2s_hw_params,
|
||||
.set_sysclk = rockchip_i2s_set_sysclk,
|
||||
.set_fmt = rockchip_i2s_set_fmt,
|
||||
.trigger = rockchip_i2s_trigger,
|
||||
};
|
||||
|
||||
static struct snd_soc_dai_driver rockchip_i2s_dai = {
|
||||
.playback = {
|
||||
.channels_min = 2,
|
||||
.channels_max = 8,
|
||||
.rates = SNDRV_PCM_RATE_8000_192000,
|
||||
.formats = (SNDRV_PCM_FMTBIT_S8 |
|
||||
SNDRV_PCM_FMTBIT_S16_LE |
|
||||
SNDRV_PCM_FMTBIT_S20_3LE |
|
||||
SNDRV_PCM_FMTBIT_S24_LE),
|
||||
},
|
||||
.capture = {
|
||||
.channels_min = 2,
|
||||
.channels_max = 2,
|
||||
.rates = SNDRV_PCM_RATE_8000_192000,
|
||||
.formats = (SNDRV_PCM_FMTBIT_S8 |
|
||||
SNDRV_PCM_FMTBIT_S16_LE |
|
||||
SNDRV_PCM_FMTBIT_S20_3LE |
|
||||
SNDRV_PCM_FMTBIT_S24_LE),
|
||||
},
|
||||
.ops = &rockchip_i2s_dai_ops,
|
||||
};
|
||||
|
||||
static const struct snd_soc_component_driver rockchip_i2s_component = {
|
||||
.name = DRV_NAME,
|
||||
};
|
||||
|
||||
static bool rockchip_i2s_wr_reg(struct device *dev, unsigned int reg)
|
||||
{
|
||||
switch (reg) {
|
||||
case I2S_TXCR:
|
||||
case I2S_RXCR:
|
||||
case I2S_CKR:
|
||||
case I2S_DMACR:
|
||||
case I2S_INTCR:
|
||||
case I2S_XFER:
|
||||
case I2S_CLR:
|
||||
case I2S_TXDR:
|
||||
return true;
|
||||
default:
|
||||
return false;
|
||||
}
|
||||
}
|
||||
|
||||
static bool rockchip_i2s_rd_reg(struct device *dev, unsigned int reg)
|
||||
{
|
||||
switch (reg) {
|
||||
case I2S_TXCR:
|
||||
case I2S_RXCR:
|
||||
case I2S_CKR:
|
||||
case I2S_DMACR:
|
||||
case I2S_INTCR:
|
||||
case I2S_XFER:
|
||||
case I2S_CLR:
|
||||
case I2S_RXDR:
|
||||
return true;
|
||||
default:
|
||||
return false;
|
||||
}
|
||||
}
|
||||
|
||||
static bool rockchip_i2s_volatile_reg(struct device *dev, unsigned int reg)
|
||||
{
|
||||
switch (reg) {
|
||||
case I2S_FIFOLR:
|
||||
case I2S_INTSR:
|
||||
return true;
|
||||
default:
|
||||
return false;
|
||||
}
|
||||
}
|
||||
|
||||
static bool rockchip_i2s_precious_reg(struct device *dev, unsigned int reg)
|
||||
{
|
||||
switch (reg) {
|
||||
case I2S_FIFOLR:
|
||||
return true;
|
||||
default:
|
||||
return false;
|
||||
}
|
||||
}
|
||||
|
||||
static const struct regmap_config rockchip_i2s_regmap_config = {
|
||||
.reg_bits = 32,
|
||||
.reg_stride = 4,
|
||||
.val_bits = 32,
|
||||
.max_register = I2S_RXDR,
|
||||
.writeable_reg = rockchip_i2s_wr_reg,
|
||||
.readable_reg = rockchip_i2s_rd_reg,
|
||||
.volatile_reg = rockchip_i2s_volatile_reg,
|
||||
.precious_reg = rockchip_i2s_precious_reg,
|
||||
.cache_type = REGCACHE_FLAT,
|
||||
};
|
||||
|
||||
static int rockchip_i2s_probe(struct platform_device *pdev)
|
||||
{
|
||||
struct rk_i2s_dev *i2s;
|
||||
struct resource *res;
|
||||
void __iomem *regs;
|
||||
int ret;
|
||||
|
||||
i2s = devm_kzalloc(&pdev->dev, sizeof(*i2s), GFP_KERNEL);
|
||||
if (!i2s) {
|
||||
dev_err(&pdev->dev, "Can't allocate rk_i2s_dev\n");
|
||||
return -ENOMEM;
|
||||
}
|
||||
|
||||
/* try to prepare related clocks */
|
||||
i2s->hclk = devm_clk_get(&pdev->dev, "i2s_hclk");
|
||||
if (IS_ERR(i2s->hclk)) {
|
||||
dev_err(&pdev->dev, "Can't retrieve i2s bus clock\n");
|
||||
return PTR_ERR(i2s->hclk);
|
||||
}
|
||||
|
||||
i2s->mclk = devm_clk_get(&pdev->dev, "i2s_clk");
|
||||
if (IS_ERR(i2s->mclk)) {
|
||||
dev_err(&pdev->dev, "Can't retrieve i2s master clock\n");
|
||||
return PTR_ERR(i2s->mclk);
|
||||
}
|
||||
|
||||
res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
|
||||
regs = devm_ioremap_resource(&pdev->dev, res);
|
||||
if (IS_ERR(regs))
|
||||
return PTR_ERR(regs);
|
||||
|
||||
i2s->regmap = devm_regmap_init_mmio(&pdev->dev, regs,
|
||||
&rockchip_i2s_regmap_config);
|
||||
if (IS_ERR(i2s->regmap)) {
|
||||
dev_err(&pdev->dev,
|
||||
"Failed to initialise managed register map\n");
|
||||
return PTR_ERR(i2s->regmap);
|
||||
}
|
||||
|
||||
i2s->playback_dma_data.addr = res->start + I2S_TXDR;
|
||||
i2s->playback_dma_data.addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
|
||||
i2s->playback_dma_data.maxburst = 16;
|
||||
|
||||
i2s->capture_dma_data.addr = res->start + I2S_RXDR;
|
||||
i2s->capture_dma_data.addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
|
||||
i2s->capture_dma_data.maxburst = 16;
|
||||
|
||||
i2s->dev = &pdev->dev;
|
||||
dev_set_drvdata(&pdev->dev, i2s);
|
||||
|
||||
pm_runtime_enable(&pdev->dev);
|
||||
if (!pm_runtime_enabled(&pdev->dev)) {
|
||||
ret = i2s_runtime_resume(&pdev->dev);
|
||||
if (ret)
|
||||
goto err_pm_disable;
|
||||
}
|
||||
|
||||
ret = devm_snd_soc_register_component(&pdev->dev,
|
||||
&rockchip_i2s_component,
|
||||
&rockchip_i2s_dai, 1);
|
||||
if (ret) {
|
||||
dev_err(&pdev->dev, "Could not register DAI\n");
|
||||
goto err_suspend;
|
||||
}
|
||||
|
||||
ret = snd_dmaengine_pcm_register(&pdev->dev, NULL, 0);
|
||||
if (ret) {
|
||||
dev_err(&pdev->dev, "Could not register PCM\n");
|
||||
goto err_pcm_register;
|
||||
}
|
||||
|
||||
return 0;
|
||||
|
||||
err_pcm_register:
|
||||
snd_dmaengine_pcm_unregister(&pdev->dev);
|
||||
err_suspend:
|
||||
if (!pm_runtime_status_suspended(&pdev->dev))
|
||||
i2s_runtime_suspend(&pdev->dev);
|
||||
err_pm_disable:
|
||||
pm_runtime_disable(&pdev->dev);
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
static int rockchip_i2s_remove(struct platform_device *pdev)
|
||||
{
|
||||
struct rk_i2s_dev *i2s = dev_get_drvdata(&pdev->dev);
|
||||
|
||||
pm_runtime_disable(&pdev->dev);
|
||||
if (!pm_runtime_status_suspended(&pdev->dev))
|
||||
i2s_runtime_suspend(&pdev->dev);
|
||||
|
||||
clk_disable_unprepare(i2s->mclk);
|
||||
clk_disable_unprepare(i2s->hclk);
|
||||
snd_dmaengine_pcm_unregister(&pdev->dev);
|
||||
snd_soc_unregister_component(&pdev->dev);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static const struct of_device_id rockchip_i2s_match[] = {
|
||||
{ .compatible = "rockchip,rk3066-i2s", },
|
||||
{},
|
||||
};
|
||||
|
||||
static const struct dev_pm_ops rockchip_i2s_pm_ops = {
|
||||
SET_RUNTIME_PM_OPS(i2s_runtime_suspend, i2s_runtime_resume,
|
||||
NULL)
|
||||
};
|
||||
|
||||
static struct platform_driver rockchip_i2s_driver = {
|
||||
.probe = rockchip_i2s_probe,
|
||||
.remove = rockchip_i2s_remove,
|
||||
.driver = {
|
||||
.name = DRV_NAME,
|
||||
.owner = THIS_MODULE,
|
||||
.of_match_table = of_match_ptr(rockchip_i2s_match),
|
||||
.pm = &rockchip_i2s_pm_ops,
|
||||
},
|
||||
};
|
||||
module_platform_driver(rockchip_i2s_driver);
|
||||
|
||||
MODULE_DESCRIPTION("ROCKCHIP IIS ASoC Interface");
|
||||
MODULE_AUTHOR("jianqun <jay.xu@rock-chips.com>");
|
||||
MODULE_LICENSE("GPL v2");
|
||||
MODULE_ALIAS("platform:" DRV_NAME);
|
||||
MODULE_DEVICE_TABLE(of, rockchip_i2s_match);
|
||||
223
sound/soc/rockchip/rockchip_i2s.h
Normal file
223
sound/soc/rockchip/rockchip_i2s.h
Normal file
|
|
@ -0,0 +1,223 @@
|
|||
/*
|
||||
* sound/soc/rockchip/rockchip_i2s.h
|
||||
*
|
||||
* ALSA SoC Audio Layer - Rockchip I2S Controller driver
|
||||
*
|
||||
* Copyright (c) 2014 Rockchip Electronics Co. Ltd.
|
||||
* Author: Jianqun xu <jay.xu@rock-chips.com>
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License version 2 as
|
||||
* published by the Free Software Foundation.
|
||||
*/
|
||||
|
||||
#ifndef _ROCKCHIP_IIS_H
|
||||
#define _ROCKCHIP_IIS_H
|
||||
|
||||
/*
|
||||
* TXCR
|
||||
* transmit operation control register
|
||||
*/
|
||||
#define I2S_TXCR_RCNT_SHIFT 17
|
||||
#define I2S_TXCR_RCNT_MASK (0x3f << I2S_TXCR_RCNT_SHIFT)
|
||||
#define I2S_TXCR_CSR_SHIFT 15
|
||||
#define I2S_TXCR_CSR(x) (x << I2S_TXCR_CSR_SHIFT)
|
||||
#define I2S_TXCR_CSR_MASK (3 << I2S_TXCR_CSR_SHIFT)
|
||||
#define I2S_TXCR_HWT BIT(14)
|
||||
#define I2S_TXCR_SJM_SHIFT 12
|
||||
#define I2S_TXCR_SJM_R (0 << I2S_TXCR_SJM_SHIFT)
|
||||
#define I2S_TXCR_SJM_L (1 << I2S_TXCR_SJM_SHIFT)
|
||||
#define I2S_TXCR_FBM_SHIFT 11
|
||||
#define I2S_TXCR_FBM_MSB (0 << I2S_TXCR_FBM_SHIFT)
|
||||
#define I2S_TXCR_FBM_LSB (1 << I2S_TXCR_FBM_SHIFT)
|
||||
#define I2S_TXCR_IBM_SHIFT 9
|
||||
#define I2S_TXCR_IBM_NORMAL (0 << I2S_TXCR_IBM_SHIFT)
|
||||
#define I2S_TXCR_IBM_LSJM (1 << I2S_TXCR_IBM_SHIFT)
|
||||
#define I2S_TXCR_IBM_RSJM (2 << I2S_TXCR_IBM_SHIFT)
|
||||
#define I2S_TXCR_IBM_MASK (3 << I2S_TXCR_IBM_SHIFT)
|
||||
#define I2S_TXCR_PBM_SHIFT 7
|
||||
#define I2S_TXCR_PBM_MODE(x) (x << I2S_TXCR_PBM_SHIFT)
|
||||
#define I2S_TXCR_PBM_MASK (3 << I2S_TXCR_PBM_SHIFT)
|
||||
#define I2S_TXCR_TFS_SHIFT 5
|
||||
#define I2S_TXCR_TFS_I2S (0 << I2S_TXCR_TFS_SHIFT)
|
||||
#define I2S_TXCR_TFS_PCM (1 << I2S_TXCR_TFS_SHIFT)
|
||||
#define I2S_TXCR_VDW_SHIFT 0
|
||||
#define I2S_TXCR_VDW(x) ((x - 1) << I2S_TXCR_VDW_SHIFT)
|
||||
#define I2S_TXCR_VDW_MASK (0x1f << I2S_TXCR_VDW_SHIFT)
|
||||
|
||||
/*
|
||||
* RXCR
|
||||
* receive operation control register
|
||||
*/
|
||||
#define I2S_RXCR_HWT BIT(14)
|
||||
#define I2S_RXCR_SJM_SHIFT 12
|
||||
#define I2S_RXCR_SJM_R (0 << I2S_RXCR_SJM_SHIFT)
|
||||
#define I2S_RXCR_SJM_L (1 << I2S_RXCR_SJM_SHIFT)
|
||||
#define I2S_RXCR_FBM_SHIFT 11
|
||||
#define I2S_RXCR_FBM_MSB (0 << I2S_RXCR_FBM_SHIFT)
|
||||
#define I2S_RXCR_FBM_LSB (1 << I2S_RXCR_FBM_SHIFT)
|
||||
#define I2S_RXCR_IBM_SHIFT 9
|
||||
#define I2S_RXCR_IBM_NORMAL (0 << I2S_RXCR_IBM_SHIFT)
|
||||
#define I2S_RXCR_IBM_LSJM (1 << I2S_RXCR_IBM_SHIFT)
|
||||
#define I2S_RXCR_IBM_RSJM (2 << I2S_RXCR_IBM_SHIFT)
|
||||
#define I2S_RXCR_IBM_MASK (3 << I2S_RXCR_IBM_SHIFT)
|
||||
#define I2S_RXCR_PBM_SHIFT 7
|
||||
#define I2S_RXCR_PBM_MODE(x) (x << I2S_RXCR_PBM_SHIFT)
|
||||
#define I2S_RXCR_PBM_MASK (3 << I2S_RXCR_PBM_SHIFT)
|
||||
#define I2S_RXCR_TFS_SHIFT 5
|
||||
#define I2S_RXCR_TFS_I2S (0 << I2S_RXCR_TFS_SHIFT)
|
||||
#define I2S_RXCR_TFS_PCM (1 << I2S_RXCR_TFS_SHIFT)
|
||||
#define I2S_RXCR_VDW_SHIFT 0
|
||||
#define I2S_RXCR_VDW(x) ((x - 1) << I2S_RXCR_VDW_SHIFT)
|
||||
#define I2S_RXCR_VDW_MASK (0x1f << I2S_RXCR_VDW_SHIFT)
|
||||
|
||||
/*
|
||||
* CKR
|
||||
* clock generation register
|
||||
*/
|
||||
#define I2S_CKR_MSS_SHIFT 27
|
||||
#define I2S_CKR_MSS_MASTER (0 << I2S_CKR_MSS_SHIFT)
|
||||
#define I2S_CKR_MSS_SLAVE (1 << I2S_CKR_MSS_SHIFT)
|
||||
#define I2S_CKR_MSS_MASK (1 << I2S_CKR_MSS_SHIFT)
|
||||
#define I2S_CKR_CKP_SHIFT 26
|
||||
#define I2S_CKR_CKP_NEG (0 << I2S_CKR_CKP_SHIFT)
|
||||
#define I2S_CKR_CKP_POS (1 << I2S_CKR_CKP_SHIFT)
|
||||
#define I2S_CKR_RLP_SHIFT 25
|
||||
#define I2S_CKR_RLP_NORMAL (0 << I2S_CKR_RLP_SHIFT)
|
||||
#define I2S_CKR_RLP_OPPSITE (1 << I2S_CKR_RLP_SHIFT)
|
||||
#define I2S_CKR_TLP_SHIFT 24
|
||||
#define I2S_CKR_TLP_NORMAL (0 << I2S_CKR_TLP_SHIFT)
|
||||
#define I2S_CKR_TLP_OPPSITE (1 << I2S_CKR_TLP_SHIFT)
|
||||
#define I2S_CKR_MDIV_SHIFT 16
|
||||
#define I2S_CKR_MDIV(x) ((x - 1) << I2S_CKR_MDIV_SHIFT)
|
||||
#define I2S_CKR_MDIV_MASK (0xff << I2S_CKR_MDIV_SHIFT)
|
||||
#define I2S_CKR_RSD_SHIFT 8
|
||||
#define I2S_CKR_RSD(x) ((x - 1) << I2S_CKR_RSD_SHIFT)
|
||||
#define I2S_CKR_RSD_MASK (0xff << I2S_CKR_RSD_SHIFT)
|
||||
#define I2S_CKR_TSD_SHIFT 0
|
||||
#define I2S_CKR_TSD(x) ((x - 1) << I2S_CKR_TSD_SHIFT)
|
||||
#define I2S_CKR_TSD_MASK (0xff << I2S_CKR_TSD_SHIFT)
|
||||
|
||||
/*
|
||||
* FIFOLR
|
||||
* FIFO level register
|
||||
*/
|
||||
#define I2S_FIFOLR_RFL_SHIFT 24
|
||||
#define I2S_FIFOLR_RFL_MASK (0x3f << I2S_FIFOLR_RFL_SHIFT)
|
||||
#define I2S_FIFOLR_TFL3_SHIFT 18
|
||||
#define I2S_FIFOLR_TFL3_MASK (0x3f << I2S_FIFOLR_TFL3_SHIFT)
|
||||
#define I2S_FIFOLR_TFL2_SHIFT 12
|
||||
#define I2S_FIFOLR_TFL2_MASK (0x3f << I2S_FIFOLR_TFL2_SHIFT)
|
||||
#define I2S_FIFOLR_TFL1_SHIFT 6
|
||||
#define I2S_FIFOLR_TFL1_MASK (0x3f << I2S_FIFOLR_TFL1_SHIFT)
|
||||
#define I2S_FIFOLR_TFL0_SHIFT 0
|
||||
#define I2S_FIFOLR_TFL0_MASK (0x3f << I2S_FIFOLR_TFL0_SHIFT)
|
||||
|
||||
/*
|
||||
* DMACR
|
||||
* DMA control register
|
||||
*/
|
||||
#define I2S_DMACR_RDE_SHIFT 24
|
||||
#define I2S_DMACR_RDE_DISABLE (0 << I2S_DMACR_RDE_SHIFT)
|
||||
#define I2S_DMACR_RDE_ENABLE (1 << I2S_DMACR_RDE_SHIFT)
|
||||
#define I2S_DMACR_RDL_SHIFT 16
|
||||
#define I2S_DMACR_RDL(x) ((x - 1) << I2S_DMACR_RDL_SHIFT)
|
||||
#define I2S_DMACR_RDL_MASK (0x1f << I2S_DMACR_RDL_SHIFT)
|
||||
#define I2S_DMACR_TDE_SHIFT 8
|
||||
#define I2S_DMACR_TDE_DISABLE (0 << I2S_DMACR_TDE_SHIFT)
|
||||
#define I2S_DMACR_TDE_ENABLE (1 << I2S_DMACR_TDE_SHIFT)
|
||||
#define I2S_DMACR_TDL_SHIFT 0
|
||||
#define I2S_DMACR_TDL(x) ((x - 1) << I2S_DMACR_TDL_SHIFT)
|
||||
#define I2S_DMACR_TDL_MASK (0x1f << I2S_DMACR_TDL_SHIFT)
|
||||
|
||||
/*
|
||||
* INTCR
|
||||
* interrupt control register
|
||||
*/
|
||||
#define I2S_INTCR_RFT_SHIFT 20
|
||||
#define I2S_INTCR_RFT(x) ((x - 1) << I2S_INTCR_RFT_SHIFT)
|
||||
#define I2S_INTCR_RXOIC BIT(18)
|
||||
#define I2S_INTCR_RXOIE_SHIFT 17
|
||||
#define I2S_INTCR_RXOIE_DISABLE (0 << I2S_INTCR_RXOIE_SHIFT)
|
||||
#define I2S_INTCR_RXOIE_ENABLE (1 << I2S_INTCR_RXOIE_SHIFT)
|
||||
#define I2S_INTCR_RXFIE_SHIFT 16
|
||||
#define I2S_INTCR_RXFIE_DISABLE (0 << I2S_INTCR_RXFIE_SHIFT)
|
||||
#define I2S_INTCR_RXFIE_ENABLE (1 << I2S_INTCR_RXFIE_SHIFT)
|
||||
#define I2S_INTCR_TFT_SHIFT 4
|
||||
#define I2S_INTCR_TFT(x) ((x - 1) << I2S_INTCR_TFT_SHIFT)
|
||||
#define I2S_INTCR_TFT_MASK (0x1f << I2S_INTCR_TFT_SHIFT)
|
||||
#define I2S_INTCR_TXUIC BIT(2)
|
||||
#define I2S_INTCR_TXUIE_SHIFT 1
|
||||
#define I2S_INTCR_TXUIE_DISABLE (0 << I2S_INTCR_TXUIE_SHIFT)
|
||||
#define I2S_INTCR_TXUIE_ENABLE (1 << I2S_INTCR_TXUIE_SHIFT)
|
||||
|
||||
/*
|
||||
* INTSR
|
||||
* interrupt status register
|
||||
*/
|
||||
#define I2S_INTSR_TXEIE_SHIFT 0
|
||||
#define I2S_INTSR_TXEIE_DISABLE (0 << I2S_INTSR_TXEIE_SHIFT)
|
||||
#define I2S_INTSR_TXEIE_ENABLE (1 << I2S_INTSR_TXEIE_SHIFT)
|
||||
#define I2S_INTSR_RXOI_SHIFT 17
|
||||
#define I2S_INTSR_RXOI_INA (0 << I2S_INTSR_RXOI_SHIFT)
|
||||
#define I2S_INTSR_RXOI_ACT (1 << I2S_INTSR_RXOI_SHIFT)
|
||||
#define I2S_INTSR_RXFI_SHIFT 16
|
||||
#define I2S_INTSR_RXFI_INA (0 << I2S_INTSR_RXFI_SHIFT)
|
||||
#define I2S_INTSR_RXFI_ACT (1 << I2S_INTSR_RXFI_SHIFT)
|
||||
#define I2S_INTSR_TXUI_SHIFT 1
|
||||
#define I2S_INTSR_TXUI_INA (0 << I2S_INTSR_TXUI_SHIFT)
|
||||
#define I2S_INTSR_TXUI_ACT (1 << I2S_INTSR_TXUI_SHIFT)
|
||||
#define I2S_INTSR_TXEI_SHIFT 0
|
||||
#define I2S_INTSR_TXEI_INA (0 << I2S_INTSR_TXEI_SHIFT)
|
||||
#define I2S_INTSR_TXEI_ACT (1 << I2S_INTSR_TXEI_SHIFT)
|
||||
|
||||
/*
|
||||
* XFER
|
||||
* Transfer start register
|
||||
*/
|
||||
#define I2S_XFER_RXS_SHIFT 1
|
||||
#define I2S_XFER_RXS_STOP (0 << I2S_XFER_RXS_SHIFT)
|
||||
#define I2S_XFER_RXS_START (1 << I2S_XFER_RXS_SHIFT)
|
||||
#define I2S_XFER_TXS_SHIFT 0
|
||||
#define I2S_XFER_TXS_STOP (0 << I2S_XFER_TXS_SHIFT)
|
||||
#define I2S_XFER_TXS_START (1 << I2S_XFER_TXS_SHIFT)
|
||||
|
||||
/*
|
||||
* CLR
|
||||
* clear SCLK domain logic register
|
||||
*/
|
||||
#define I2S_CLR_RXC BIT(1)
|
||||
#define I2S_CLR_TXC BIT(0)
|
||||
|
||||
/*
|
||||
* TXDR
|
||||
* Transimt FIFO data register, write only.
|
||||
*/
|
||||
#define I2S_TXDR_MASK (0xff)
|
||||
|
||||
/*
|
||||
* RXDR
|
||||
* Receive FIFO data register, write only.
|
||||
*/
|
||||
#define I2S_RXDR_MASK (0xff)
|
||||
|
||||
/* Clock divider id */
|
||||
enum {
|
||||
ROCKCHIP_DIV_MCLK = 0,
|
||||
ROCKCHIP_DIV_BCLK,
|
||||
};
|
||||
|
||||
/* I2S REGS */
|
||||
#define I2S_TXCR (0x0000)
|
||||
#define I2S_RXCR (0x0004)
|
||||
#define I2S_CKR (0x0008)
|
||||
#define I2S_FIFOLR (0x000c)
|
||||
#define I2S_DMACR (0x0010)
|
||||
#define I2S_INTCR (0x0014)
|
||||
#define I2S_INTSR (0x0018)
|
||||
#define I2S_XFER (0x001c)
|
||||
#define I2S_CLR (0x0020)
|
||||
#define I2S_TXDR (0x0024)
|
||||
#define I2S_RXDR (0x0028)
|
||||
|
||||
#endif /* _ROCKCHIP_IIS_H */
|
||||
Loading…
Reference in a new issue