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ath9k: remove pointless sc_txintrperiod and spin_lock_bh on tx prepare
sc_txintrperiod is currently set to 0 and never updated. We won't be using this, if anything we will consider using TX interrupt mitigation but that is different and not yet tested. So remove sc_txintrperiod and the pointless spin_lock_bh() on tx prepare. Signed-off-by: Luis R. Rodriguez <lrodriguez@atheros.com> Signed-off-by: John W. Linville <linville@tuxdriver.com>
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d9d2925713
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3 changed files with 15 additions and 29 deletions
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@ -138,6 +138,19 @@ struct ath_desc {
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#define ATH9K_TXDESC_NOACK 0x0002
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#define ATH9K_TXDESC_RTSENA 0x0004
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#define ATH9K_TXDESC_CTSENA 0x0008
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/* ATH9K_TXDESC_INTREQ forces a tx interrupt to be generated for
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* the descriptor its marked on. We take a tx interrupt to reap
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* descriptors when the h/w hits an EOL condition or
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* when the descriptor is specifically marked to generate
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* an interrupt with this flag. Descriptors should be
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* marked periodically to insure timely replenishing of the
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* supply needed for sending frames. Defering interrupts
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* reduces system load and potentially allows more concurrent
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* work to be done but if done to aggressively can cause
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* senders to backup. When the hardware queue is left too
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* large rate control information may also be too out of
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* date. An Alternative for this is TX interrupt mitigation
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* but this needs more testing. */
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#define ATH9K_TXDESC_INTREQ 0x0010
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#define ATH9K_TXDESC_VEOL 0x0020
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#define ATH9K_TXDESC_EXT_ONLY 0x0040
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@ -443,9 +443,6 @@ struct ath_txq {
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u8 axq_aggr_depth; /* aggregates queued */
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u32 axq_totalqueued; /* total ever queued */
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/* count to determine if descriptor should generate int on this txq. */
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u32 axq_intrcnt;
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bool stopped; /* Is mac80211 queue stopped ? */
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struct ath_buf *axq_linkbuf; /* virtual addr of last buffer*/
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@ -1007,7 +1004,6 @@ struct ath_softc {
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struct ath_txq sc_txq[ATH9K_NUM_TX_QUEUES];
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struct ath_descdma sc_txdma;
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u32 sc_txqsetup;
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u32 sc_txintrperiod; /* tx interrupt batching */
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int sc_haltype2q[ATH9K_WME_AC_VO+1]; /* HAL WME AC -> h/w qnum */
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u16 seq_no; /* TX sequence number */
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@ -286,7 +286,8 @@ static int ath_tx_prepare(struct ath_softc *sc,
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/* Fill flags */
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txctl->flags |= ATH9K_TXDESC_CLRDMASK; /* needed for crypto errors */
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txctl->flags |= ATH9K_TXDESC_CLRDMASK /* needed for crypto errors */
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| ATH9K_TXDESC_INTREQ; /* Generate an interrupt */
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if (tx_info->flags & IEEE80211_TX_CTL_NO_ACK)
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txctl->flags |= ATH9K_TXDESC_NOACK;
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@ -363,28 +364,6 @@ static int ath_tx_prepare(struct ath_softc *sc,
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rcs[0].tries = ATH_TXMAXTRY;
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}
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/*
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* Determine if a tx interrupt should be generated for
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* this descriptor. We take a tx interrupt to reap
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* descriptors when the h/w hits an EOL condition or
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* when the descriptor is specifically marked to generate
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* an interrupt. We periodically mark descriptors in this
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* way to insure timely replenishing of the supply needed
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* for sending frames. Defering interrupts reduces system
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* load and potentially allows more concurrent work to be
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* done but if done to aggressively can cause senders to
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* backup.
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*
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* NB: use >= to deal with sc_txintrperiod changing
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* dynamically through sysctl.
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*/
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spin_lock_bh(&txq->axq_lock);
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if ((++txq->axq_intrcnt >= sc->sc_txintrperiod)) {
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txctl->flags |= ATH9K_TXDESC_INTREQ;
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txq->axq_intrcnt = 0;
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}
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spin_unlock_bh(&txq->axq_lock);
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if (is_multicast_ether_addr(hdr->addr1)) {
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antenna = sc->sc_mcastantenna + 1;
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sc->sc_mcastantenna = (sc->sc_mcastantenna + 1) & 0x1;
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@ -1166,7 +1145,6 @@ static int ath_tx_processq(struct ath_softc *sc, struct ath_txq *txq)
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nacked = 0;
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for (;;) {
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spin_lock_bh(&txq->axq_lock);
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txq->axq_intrcnt = 0; /* reset periodic desc intr count */
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if (list_empty(&txq->axq_q)) {
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txq->axq_link = NULL;
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txq->axq_linkbuf = NULL;
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@ -2164,7 +2142,6 @@ struct ath_txq *ath_txq_setup(struct ath_softc *sc, int qtype, int subtype)
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txq->axq_depth = 0;
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txq->axq_aggr_depth = 0;
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txq->axq_totalqueued = 0;
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txq->axq_intrcnt = 0;
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txq->axq_linkbuf = NULL;
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sc->sc_txqsetup |= 1<<qnum;
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}
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