x86/bugs: Cache the value of MSR_IA32_ARCH_CAPABILITIES
commitcb2db5bb04
upstream. There's no need to keep reading MSR_IA32_ARCH_CAPABILITIES over and over. It's even read in the BHI sysfs function which is a big no-no. Just read it once and cache it. Fixes:ec9404e40e
("x86/bhi: Add BHI mitigation knob") Signed-off-by: Josh Poimboeuf <jpoimboe@kernel.org> Signed-off-by: Ingo Molnar <mingo@kernel.org> Reviewed-by: Nikolay Borisov <nik.borisov@suse.com> Cc: Linus Torvalds <torvalds@linux-foundation.org> Cc: Sean Christopherson <seanjc@google.com> Link: https://lore.kernel.org/r/9592a18a814368e75f8f4b9d74d3883aa4fd1eaf.1712813475.git.jpoimboe@kernel.org Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
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@ -60,6 +60,8 @@ EXPORT_SYMBOL_GPL(x86_spec_ctrl_current);
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u64 x86_pred_cmd __ro_after_init = PRED_CMD_IBPB;
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EXPORT_SYMBOL_GPL(x86_pred_cmd);
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static u64 __ro_after_init ia32_cap;
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static DEFINE_MUTEX(spec_ctrl_mutex);
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void (*x86_return_thunk)(void) __ro_after_init = &__x86_return_thunk;
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@ -143,6 +145,8 @@ void __init cpu_select_mitigations(void)
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x86_spec_ctrl_base &= ~SPEC_CTRL_MITIGATIONS_MASK;
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}
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ia32_cap = x86_read_arch_cap_msr();
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/* Select the proper CPU mitigations before patching alternatives: */
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spectre_v1_select_mitigation();
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spectre_v2_select_mitigation();
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@ -300,8 +304,6 @@ static const char * const taa_strings[] = {
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static void __init taa_select_mitigation(void)
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{
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u64 ia32_cap;
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if (!boot_cpu_has_bug(X86_BUG_TAA)) {
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taa_mitigation = TAA_MITIGATION_OFF;
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return;
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@ -340,7 +342,6 @@ static void __init taa_select_mitigation(void)
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* On MDS_NO=1 CPUs if ARCH_CAP_TSX_CTRL_MSR is not set, microcode
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* update is required.
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*/
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ia32_cap = x86_read_arch_cap_msr();
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if ( (ia32_cap & ARCH_CAP_MDS_NO) &&
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!(ia32_cap & ARCH_CAP_TSX_CTRL_MSR))
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taa_mitigation = TAA_MITIGATION_UCODE_NEEDED;
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@ -400,8 +401,6 @@ static const char * const mmio_strings[] = {
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static void __init mmio_select_mitigation(void)
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{
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u64 ia32_cap;
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if (!boot_cpu_has_bug(X86_BUG_MMIO_STALE_DATA) ||
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boot_cpu_has_bug(X86_BUG_MMIO_UNKNOWN) ||
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cpu_mitigations_off()) {
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@ -412,8 +411,6 @@ static void __init mmio_select_mitigation(void)
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if (mmio_mitigation == MMIO_MITIGATION_OFF)
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return;
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ia32_cap = x86_read_arch_cap_msr();
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/*
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* Enable CPU buffer clear mitigation for host and VMM, if also affected
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* by MDS or TAA. Otherwise, enable mitigation for VMM only.
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@ -507,7 +504,7 @@ static void __init rfds_select_mitigation(void)
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if (rfds_mitigation == RFDS_MITIGATION_OFF)
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return;
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if (x86_read_arch_cap_msr() & ARCH_CAP_RFDS_CLEAR)
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if (ia32_cap & ARCH_CAP_RFDS_CLEAR)
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setup_force_cpu_cap(X86_FEATURE_CLEAR_CPU_BUF);
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else
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rfds_mitigation = RFDS_MITIGATION_UCODE_NEEDED;
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@ -658,8 +655,6 @@ void update_srbds_msr(void)
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static void __init srbds_select_mitigation(void)
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{
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u64 ia32_cap;
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if (!boot_cpu_has_bug(X86_BUG_SRBDS))
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return;
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@ -668,7 +663,6 @@ static void __init srbds_select_mitigation(void)
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* are only exposed to SRBDS when TSX is enabled or when CPU is affected
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* by Processor MMIO Stale Data vulnerability.
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*/
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ia32_cap = x86_read_arch_cap_msr();
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if ((ia32_cap & ARCH_CAP_MDS_NO) && !boot_cpu_has(X86_FEATURE_RTM) &&
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!boot_cpu_has_bug(X86_BUG_MMIO_STALE_DATA))
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srbds_mitigation = SRBDS_MITIGATION_TSX_OFF;
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@ -812,7 +806,7 @@ static void __init gds_select_mitigation(void)
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/* Will verify below that mitigation _can_ be disabled */
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/* No microcode */
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if (!(x86_read_arch_cap_msr() & ARCH_CAP_GDS_CTRL)) {
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if (!(ia32_cap & ARCH_CAP_GDS_CTRL)) {
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if (gds_mitigation == GDS_MITIGATION_FORCE) {
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/*
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* This only needs to be done on the boot CPU so do it
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@ -1884,8 +1878,6 @@ static void update_indir_branch_cond(void)
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/* Update the static key controlling the MDS CPU buffer clear in idle */
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static void update_mds_branch_idle(void)
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{
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u64 ia32_cap = x86_read_arch_cap_msr();
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/*
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* Enable the idle clearing if SMT is active on CPUs which are
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* affected only by MSBDS and not any other MDS variant.
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@ -2797,7 +2789,7 @@ static const char *spectre_bhi_state(void)
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else if (boot_cpu_has(X86_FEATURE_CLEAR_BHB_LOOP))
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return "; BHI: SW loop, KVM: SW loop";
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else if (boot_cpu_has(X86_FEATURE_RETPOLINE) &&
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!(x86_read_arch_cap_msr() & ARCH_CAP_RRSBA))
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!(ia32_cap & ARCH_CAP_RRSBA))
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return "; BHI: Retpoline";
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else if (boot_cpu_has(X86_FEATURE_CLEAR_BHB_LOOP_ON_VMEXIT))
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return "; BHI: Syscall hardening, KVM: SW loop";
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