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misc: rtsx: add rts5261 efuse function
move rts5261_fetch_vendor_settings() to rts5261_init_from_hw() make sure it be called from S3 or D3 add more register setting when efuse is set read efuse setting to register on init flow Signed-off-by: Ricky Wu <Ricky_wu@realtek.com> Link: https://lore.kernel.org/r/18101ecb0f0749ccb9f564eda171ba40@realtek.com Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
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parent
35a7609639
commit
b1c5f30851
2 changed files with 65 additions and 53 deletions
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@ -57,40 +57,6 @@ static void rts5261_fill_driving(struct rtsx_pcr *pcr, u8 voltage)
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0xFF, driving[drive_sel][2]);
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}
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static void rtsx5261_fetch_vendor_settings(struct rtsx_pcr *pcr)
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{
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struct pci_dev *pdev = pcr->pci;
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u32 reg;
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/* 0x814~0x817 */
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pci_read_config_dword(pdev, PCR_SETTING_REG2, ®);
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pcr_dbg(pcr, "Cfg 0x%x: 0x%x\n", PCR_SETTING_REG2, reg);
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if (!rts5261_vendor_setting_valid(reg)) {
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/* Not support MMC default */
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pcr->extra_caps |= EXTRA_CAPS_NO_MMC;
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pcr_dbg(pcr, "skip fetch vendor setting\n");
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return;
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}
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if (!rts5261_reg_check_mmc_support(reg))
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pcr->extra_caps |= EXTRA_CAPS_NO_MMC;
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/* TO do: need to add rtd3 function */
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pcr->rtd3_en = rts5261_reg_to_rtd3(reg);
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if (rts5261_reg_check_reverse_socket(reg))
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pcr->flags |= PCR_REVERSE_SOCKET;
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/* 0x724~0x727 */
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pci_read_config_dword(pdev, PCR_SETTING_REG1, ®);
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pcr_dbg(pcr, "Cfg 0x%x: 0x%x\n", PCR_SETTING_REG1, reg);
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pcr->aspm_en = rts5261_reg_to_aspm(reg);
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pcr->sd30_drive_sel_1v8 = rts5261_reg_to_sd30_drive_sel_1v8(reg);
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pcr->sd30_drive_sel_3v3 = rts5261_reg_to_sd30_drive_sel_3v3(reg);
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}
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static void rts5261_force_power_down(struct rtsx_pcr *pcr, u8 pm_state, bool runtime)
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{
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/* Set relink_time to 0 */
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@ -391,11 +357,11 @@ static void rts5261_process_ocp(struct rtsx_pcr *pcr)
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}
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static int rts5261_init_from_hw(struct rtsx_pcr *pcr)
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static void rts5261_init_from_hw(struct rtsx_pcr *pcr)
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{
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struct pci_dev *pdev = pcr->pci;
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int retval;
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u32 lval, i;
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u32 lval1, lval2, i;
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u16 setting_reg1, setting_reg2;
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u8 valid, efuse_valid, tmp;
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rtsx_pci_write_register(pcr, RTS5261_REG_PME_FORCE_CTL,
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@ -418,26 +384,70 @@ static int rts5261_init_from_hw(struct rtsx_pcr *pcr)
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efuse_valid = ((tmp & 0x0C) >> 2);
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pcr_dbg(pcr, "Load efuse valid: 0x%x\n", efuse_valid);
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if (efuse_valid == 0) {
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retval = pci_read_config_dword(pdev, PCR_SETTING_REG2, &lval);
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if (retval != 0)
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pcr_dbg(pcr, "read 0x814 DW fail\n");
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pcr_dbg(pcr, "DW from 0x814: 0x%x\n", lval);
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/* 0x816 */
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valid = (u8)((lval >> 16) & 0x03);
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pcr_dbg(pcr, "0x816: %d\n", valid);
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}
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pci_read_config_dword(pdev, PCR_SETTING_REG2, &lval2);
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pcr_dbg(pcr, "Cfg 0x%x: 0x%x\n", PCR_SETTING_REG2, lval2);
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/* 0x816 */
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valid = (u8)((lval2 >> 16) & 0x03);
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rtsx_pci_write_register(pcr, RTS5261_REG_PME_FORCE_CTL,
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REG_EFUSE_POR, 0);
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pcr_dbg(pcr, "Disable efuse por!\n");
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pci_read_config_dword(pdev, PCR_SETTING_REG2, &lval);
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lval = lval & 0x00FFFFFF;
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retval = pci_write_config_dword(pdev, PCR_SETTING_REG2, lval);
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if (retval != 0)
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pcr_dbg(pcr, "write config fail\n");
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if (efuse_valid == 2 || efuse_valid == 3) {
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if (valid == 3) {
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/* Bypass efuse */
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setting_reg1 = PCR_SETTING_REG1;
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setting_reg2 = PCR_SETTING_REG2;
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} else {
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/* Use efuse data */
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setting_reg1 = PCR_SETTING_REG4;
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setting_reg2 = PCR_SETTING_REG5;
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}
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} else if (efuse_valid == 0) {
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// default
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setting_reg1 = PCR_SETTING_REG1;
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setting_reg2 = PCR_SETTING_REG2;
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}
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return retval;
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pci_read_config_dword(pdev, setting_reg2, &lval2);
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pcr_dbg(pcr, "Cfg 0x%x: 0x%x\n", setting_reg2, lval2);
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if (!rts5261_vendor_setting_valid(lval2)) {
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/* Not support MMC default */
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pcr->extra_caps |= EXTRA_CAPS_NO_MMC;
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pcr_dbg(pcr, "skip fetch vendor setting\n");
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return;
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}
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if (!rts5261_reg_check_mmc_support(lval2))
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pcr->extra_caps |= EXTRA_CAPS_NO_MMC;
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pcr->rtd3_en = rts5261_reg_to_rtd3(lval2);
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if (rts5261_reg_check_reverse_socket(lval2))
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pcr->flags |= PCR_REVERSE_SOCKET;
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pci_read_config_dword(pdev, setting_reg1, &lval1);
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pcr_dbg(pcr, "Cfg 0x%x: 0x%x\n", setting_reg1, lval1);
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pcr->aspm_en = rts5261_reg_to_aspm(lval1);
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pcr->sd30_drive_sel_1v8 = rts5261_reg_to_sd30_drive_sel_1v8(lval1);
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pcr->sd30_drive_sel_3v3 = rts5261_reg_to_sd30_drive_sel_3v3(lval1);
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if (setting_reg1 == PCR_SETTING_REG1) {
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/* store setting */
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rtsx_pci_write_register(pcr, 0xFF0C, 0xFF, (u8)(lval1 & 0xFF));
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rtsx_pci_write_register(pcr, 0xFF0D, 0xFF, (u8)((lval1 >> 8) & 0xFF));
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rtsx_pci_write_register(pcr, 0xFF0E, 0xFF, (u8)((lval1 >> 16) & 0xFF));
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rtsx_pci_write_register(pcr, 0xFF0F, 0xFF, (u8)((lval1 >> 24) & 0xFF));
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rtsx_pci_write_register(pcr, 0xFF10, 0xFF, (u8)(lval2 & 0xFF));
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rtsx_pci_write_register(pcr, 0xFF11, 0xFF, (u8)((lval2 >> 8) & 0xFF));
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rtsx_pci_write_register(pcr, 0xFF12, 0xFF, (u8)((lval2 >> 16) & 0xFF));
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pci_write_config_dword(pdev, PCR_SETTING_REG4, lval1);
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lval2 = lval2 & 0x00FFFFFF;
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pci_write_config_dword(pdev, PCR_SETTING_REG5, lval2);
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}
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}
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static void rts5261_init_from_cfg(struct rtsx_pcr *pcr)
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@ -636,7 +646,6 @@ static void rts5261_set_l1off_cfg_sub_d0(struct rtsx_pcr *pcr, int active)
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}
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static const struct pcr_ops rts5261_pcr_ops = {
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.fetch_vendor_settings = rtsx5261_fetch_vendor_settings,
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.turn_on_led = rts5261_turn_on_led,
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.turn_off_led = rts5261_turn_off_led,
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.extra_init_hw = rts5261_extra_init_hw,
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@ -1067,6 +1067,9 @@
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#define PCR_SETTING_REG1 0x724
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#define PCR_SETTING_REG2 0x814
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#define PCR_SETTING_REG3 0x747
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#define PCR_SETTING_REG4 0x818
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#define PCR_SETTING_REG5 0x81C
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#define rtsx_pci_init_cmd(pcr) ((pcr)->ci = 0)
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