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davinci: use divide ratio limits from pll_data
This patch modifies the sysclk rate setting code to use the divider mask specified in pll_data. Without this, devices with different divider ranges (e.g. tnetv107x) fail. Signed-off-by: Cyril Chemparathy <cyril@ti.com> Signed-off-by: Kevin Hilman <khilman@deeprootsystems.com>
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1 changed files with 2 additions and 2 deletions
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@ -336,7 +336,7 @@ int davinci_set_sysclk_rate(struct clk *clk, unsigned long rate)
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ratio--;
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}
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if (ratio > PLLDIV_RATIO_MASK)
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if (ratio > pll->div_ratio_mask)
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return -EINVAL;
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do {
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@ -344,7 +344,7 @@ int davinci_set_sysclk_rate(struct clk *clk, unsigned long rate)
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} while (v & PLLSTAT_GOSTAT);
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v = __raw_readl(pll->base + clk->div_reg);
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v &= ~PLLDIV_RATIO_MASK;
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v &= ~pll->div_ratio_mask;
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v |= ratio | PLLDIV_EN;
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__raw_writel(v, pll->base + clk->div_reg);
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