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spi: spi-imx: fix MX51_ECSPI_* macros when cs > 3
[ Upstream commit 87c614175b
]
When using gpio based chip select the cs value can go outside the range
0 – 3. The various MX51_ECSPI_* macros did not take this into consideration
resulting in possible corruption of the configuration.
For example for any cs value over 3 the SCLKPHA bits would not be set and
other values in the register possibly corrupted.
One way to fix this is to just mask the cs bits to 2 bits. This still
allows all 4 native chip selects to work as well as gpio chip selects
(which can use any of the 4 chip select configurations).
Signed-off-by: Kevin Groeneveld <kgroeneveld@lenbrook.com>
Link: https://lore.kernel.org/r/20230318222132.3373-1-kgroeneveld@lenbrook.com
Signed-off-by: Mark Brown <broonie@kernel.org>
Signed-off-by: Sasha Levin <sashal@kernel.org>
This commit is contained in:
parent
6293d0533c
commit
b2069cfe1b
1 changed files with 18 additions and 6 deletions
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@ -247,6 +247,18 @@ static bool spi_imx_can_dma(struct spi_master *master, struct spi_device *spi,
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return true;
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}
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/*
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* Note the number of natively supported chip selects for MX51 is 4. Some
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* devices may have less actual SS pins but the register map supports 4. When
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* using gpio chip selects the cs values passed into the macros below can go
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* outside the range 0 - 3. We therefore need to limit the cs value to avoid
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* corrupting bits outside the allocated locations.
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*
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* The simplest way to do this is to just mask the cs bits to 2 bits. This
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* still allows all 4 native chip selects to work as well as gpio chip selects
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* (which can use any of the 4 chip select configurations).
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*/
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#define MX51_ECSPI_CTRL 0x08
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#define MX51_ECSPI_CTRL_ENABLE (1 << 0)
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#define MX51_ECSPI_CTRL_XCH (1 << 2)
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@ -255,16 +267,16 @@ static bool spi_imx_can_dma(struct spi_master *master, struct spi_device *spi,
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#define MX51_ECSPI_CTRL_DRCTL(drctl) ((drctl) << 16)
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#define MX51_ECSPI_CTRL_POSTDIV_OFFSET 8
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#define MX51_ECSPI_CTRL_PREDIV_OFFSET 12
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#define MX51_ECSPI_CTRL_CS(cs) ((cs) << 18)
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#define MX51_ECSPI_CTRL_CS(cs) ((cs & 3) << 18)
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#define MX51_ECSPI_CTRL_BL_OFFSET 20
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#define MX51_ECSPI_CTRL_BL_MASK (0xfff << 20)
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#define MX51_ECSPI_CONFIG 0x0c
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#define MX51_ECSPI_CONFIG_SCLKPHA(cs) (1 << ((cs) + 0))
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#define MX51_ECSPI_CONFIG_SCLKPOL(cs) (1 << ((cs) + 4))
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#define MX51_ECSPI_CONFIG_SBBCTRL(cs) (1 << ((cs) + 8))
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#define MX51_ECSPI_CONFIG_SSBPOL(cs) (1 << ((cs) + 12))
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#define MX51_ECSPI_CONFIG_SCLKCTL(cs) (1 << ((cs) + 20))
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#define MX51_ECSPI_CONFIG_SCLKPHA(cs) (1 << ((cs & 3) + 0))
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#define MX51_ECSPI_CONFIG_SCLKPOL(cs) (1 << ((cs & 3) + 4))
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#define MX51_ECSPI_CONFIG_SBBCTRL(cs) (1 << ((cs & 3) + 8))
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#define MX51_ECSPI_CONFIG_SSBPOL(cs) (1 << ((cs & 3) + 12))
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#define MX51_ECSPI_CONFIG_SCLKCTL(cs) (1 << ((cs & 3) + 20))
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#define MX51_ECSPI_INT 0x10
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#define MX51_ECSPI_INT_TEEN (1 << 0)
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