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Merge branch 'pm-devfreq'
* pm-devfreq: PM / devfreq: imx8m-ddrc: Remove unneeded of_match_ptr() PM / devfreq: imx-bus: Remove unneeded of_match_ptr() PM / devfreq: imx8m-ddrc: Remove imx8m_ddrc_get_dev_status PM / devfreq: Remove the invalid description for get_target_freq PM / devfreq: Check get_dev_status in devfreq_update_stats PM / devfreq: Fix the wrong set_freq path for userspace governor in Kconfig dt-bindings: devfreq: rk3399_dmc: Remove references of unexistant defines dt-bindings: devfreq: rk3399_dmc: Add rockchip,pmu phandle. PM / devfreq: rk3399_dmc: Simplify with dev_err_probe() PM / devfreq: Use more accurate returned new_freq as resume_freq PM / devfreq: Unlock mutex and free devfreq struct in error path PM / devfreq: Register devfreq as a cooling device on demand
This commit is contained in:
commit
b20f7dbdca
9 changed files with 70 additions and 78 deletions
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@ -97,10 +97,7 @@ Description:
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object. The values are represented in ms. If the value is
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less than 1 jiffy, it is considered to be 0, which means
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no polling. This value is meaningless if the governor is
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not polling; thus. If the governor is not using
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devfreq-provided central polling
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(/sys/class/devfreq/.../central_polling is 0), this value
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may be useless.
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not polling.
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A list of governors that support the node:
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- simple_ondmenad
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@ -12,6 +12,8 @@ Required properties:
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for details.
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- center-supply: DMC supply node.
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- status: Marks the node enabled/disabled.
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- rockchip,pmu: Phandle to the syscon managing the "PMU general register
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files".
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Optional properties:
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- interrupts: The CPU interrupt number. The interrupt specifier
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@ -77,24 +79,23 @@ Following properties relate to DDR timing:
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- rockchip,ddr3_drv : When the DRAM type is DDR3, this parameter defines
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the DRAM side driver strength in ohms. Default
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value is DDR3_DS_40ohm.
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value is 40.
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- rockchip,ddr3_odt : When the DRAM type is DDR3, this parameter defines
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the DRAM side ODT strength in ohms. Default value
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is DDR3_ODT_120ohm.
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is 120.
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- rockchip,phy_ddr3_ca_drv : When the DRAM type is DDR3, this parameter defines
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the phy side CA line (incluing command line,
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address line and clock line) driver strength.
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Default value is PHY_DRV_ODT_40.
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Default value is 40.
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- rockchip,phy_ddr3_dq_drv : When the DRAM type is DDR3, this parameter defines
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the PHY side DQ line (including DQS/DQ/DM line)
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driver strength. Default value is PHY_DRV_ODT_40.
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driver strength. Default value is 40.
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- rockchip,phy_ddr3_odt : When the DRAM type is DDR3, this parameter defines
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the PHY side ODT strength. Default value is
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PHY_DRV_ODT_240.
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the PHY side ODT strength. Default value is 240.
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- rockchip,lpddr3_odt_dis_freq : When the DRAM type is LPDDR3, this parameter defines
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then ODT disable frequency in MHz (Mega Hz).
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@ -104,25 +105,23 @@ Following properties relate to DDR timing:
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- rockchip,lpddr3_drv : When the DRAM type is LPDDR3, this parameter defines
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the DRAM side driver strength in ohms. Default
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value is LP3_DS_34ohm.
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value is 34.
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- rockchip,lpddr3_odt : When the DRAM type is LPDDR3, this parameter defines
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the DRAM side ODT strength in ohms. Default value
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is LP3_ODT_240ohm.
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is 240.
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- rockchip,phy_lpddr3_ca_drv : When the DRAM type is LPDDR3, this parameter defines
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the PHY side CA line (including command line,
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address line and clock line) driver strength.
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Default value is PHY_DRV_ODT_40.
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Default value is 40.
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- rockchip,phy_lpddr3_dq_drv : When the DRAM type is LPDDR3, this parameter defines
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the PHY side DQ line (including DQS/DQ/DM line)
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driver strength. Default value is
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PHY_DRV_ODT_40.
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driver strength. Default value is 40.
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- rockchip,phy_lpddr3_odt : When dram type is LPDDR3, this parameter define
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the phy side odt strength, default value is
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PHY_DRV_ODT_240.
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the phy side odt strength, default value is 240.
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- rockchip,lpddr4_odt_dis_freq : When the DRAM type is LPDDR4, this parameter
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defines the ODT disable frequency in
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@ -132,32 +131,30 @@ Following properties relate to DDR timing:
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- rockchip,lpddr4_drv : When the DRAM type is LPDDR4, this parameter defines
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the DRAM side driver strength in ohms. Default
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value is LP4_PDDS_60ohm.
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value is 60.
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- rockchip,lpddr4_dq_odt : When the DRAM type is LPDDR4, this parameter defines
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the DRAM side ODT on DQS/DQ line strength in ohms.
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Default value is LP4_DQ_ODT_40ohm.
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Default value is 40.
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- rockchip,lpddr4_ca_odt : When the DRAM type is LPDDR4, this parameter defines
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the DRAM side ODT on CA line strength in ohms.
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Default value is LP4_CA_ODT_40ohm.
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Default value is 40.
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- rockchip,phy_lpddr4_ca_drv : When the DRAM type is LPDDR4, this parameter defines
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the PHY side CA line (including command address
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line) driver strength. Default value is
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PHY_DRV_ODT_40.
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line) driver strength. Default value is 40.
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- rockchip,phy_lpddr4_ck_cs_drv : When the DRAM type is LPDDR4, this parameter defines
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the PHY side clock line and CS line driver
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strength. Default value is PHY_DRV_ODT_80.
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strength. Default value is 80.
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- rockchip,phy_lpddr4_dq_drv : When the DRAM type is LPDDR4, this parameter defines
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the PHY side DQ line (including DQS/DQ/DM line)
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driver strength. Default value is PHY_DRV_ODT_80.
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driver strength. Default value is 80.
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- rockchip,phy_lpddr4_odt : When the DRAM type is LPDDR4, this parameter defines
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the PHY side ODT strength. Default value is
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PHY_DRV_ODT_60.
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the PHY side ODT strength. Default value is 60.
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Example:
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dmc_opp_table: dmc_opp_table {
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@ -193,23 +190,23 @@ Example:
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rockchip,phy_dll_dis_freq = <125>;
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rockchip,auto_pd_dis_freq = <666>;
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rockchip,ddr3_odt_dis_freq = <333>;
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rockchip,ddr3_drv = <DDR3_DS_40ohm>;
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rockchip,ddr3_odt = <DDR3_ODT_120ohm>;
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rockchip,phy_ddr3_ca_drv = <PHY_DRV_ODT_40>;
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rockchip,phy_ddr3_dq_drv = <PHY_DRV_ODT_40>;
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rockchip,phy_ddr3_odt = <PHY_DRV_ODT_240>;
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rockchip,ddr3_drv = <40>;
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rockchip,ddr3_odt = <120>;
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rockchip,phy_ddr3_ca_drv = <40>;
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rockchip,phy_ddr3_dq_drv = <40>;
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rockchip,phy_ddr3_odt = <240>;
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rockchip,lpddr3_odt_dis_freq = <333>;
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rockchip,lpddr3_drv = <LP3_DS_34ohm>;
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rockchip,lpddr3_odt = <LP3_ODT_240ohm>;
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rockchip,phy_lpddr3_ca_drv = <PHY_DRV_ODT_40>;
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rockchip,phy_lpddr3_dq_drv = <PHY_DRV_ODT_40>;
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rockchip,phy_lpddr3_odt = <PHY_DRV_ODT_240>;
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rockchip,lpddr3_drv = <34>;
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rockchip,lpddr3_odt = <240>;
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rockchip,phy_lpddr3_ca_drv = <40>;
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rockchip,phy_lpddr3_dq_drv = <40>;
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rockchip,phy_lpddr3_odt = <240>;
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rockchip,lpddr4_odt_dis_freq = <333>;
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rockchip,lpddr4_drv = <LP4_PDDS_60ohm>;
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rockchip,lpddr4_dq_odt = <LP4_DQ_ODT_40ohm>;
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rockchip,lpddr4_ca_odt = <LP4_CA_ODT_40ohm>;
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rockchip,phy_lpddr4_ca_drv = <PHY_DRV_ODT_40>;
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rockchip,phy_lpddr4_ck_cs_drv = <PHY_DRV_ODT_80>;
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rockchip,phy_lpddr4_dq_drv = <PHY_DRV_ODT_80>;
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rockchip,phy_lpddr4_odt = <PHY_DRV_ODT_60>;
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rockchip,lpddr4_drv = <60>;
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rockchip,lpddr4_dq_odt = <40>;
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rockchip,lpddr4_ca_odt = <40>;
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rockchip,phy_lpddr4_ca_drv = <40>;
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rockchip,phy_lpddr4_ck_cs_drv = <80>;
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rockchip,phy_lpddr4_dq_drv = <80>;
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rockchip,phy_lpddr4_odt = <60>;
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};
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@ -62,7 +62,7 @@ config DEVFREQ_GOV_USERSPACE
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help
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Sets the frequency at the user specified one.
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This governor returns the user configured frequency if there
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has been an input to /sys/devices/.../power/devfreq_set_freq.
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has been an input to /sys/devices/.../userspace/set_freq.
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Otherwise, the governor does not change the frequency
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given at the initialization.
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@ -11,6 +11,7 @@
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#include <linux/kmod.h>
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#include <linux/sched.h>
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#include <linux/debugfs.h>
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#include <linux/devfreq_cooling.h>
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#include <linux/errno.h>
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#include <linux/err.h>
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#include <linux/init.h>
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@ -387,7 +388,7 @@ static int devfreq_set_target(struct devfreq *devfreq, unsigned long new_freq,
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devfreq->previous_freq = new_freq;
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if (devfreq->suspend_freq)
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devfreq->resume_freq = cur_freq;
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devfreq->resume_freq = new_freq;
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return err;
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}
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@ -821,7 +822,8 @@ struct devfreq *devfreq_add_device(struct device *dev,
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if (devfreq->profile->timer < 0
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|| devfreq->profile->timer >= DEVFREQ_TIMER_NUM) {
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goto err_out;
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mutex_unlock(&devfreq->lock);
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goto err_dev;
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}
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if (!devfreq->profile->max_state && !devfreq->profile->freq_table) {
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mutex_unlock(&devfreq_list_lock);
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if (devfreq->profile->is_cooling_device) {
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devfreq->cdev = devfreq_cooling_em_register(devfreq, NULL);
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if (IS_ERR(devfreq->cdev))
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devfreq->cdev = NULL;
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}
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return devfreq;
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err_init:
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if (!devfreq)
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return -EINVAL;
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devfreq_cooling_unregister(devfreq->cdev);
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if (devfreq->governor) {
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devfreq->governor->event_handler(devfreq,
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DEVFREQ_GOV_STOP, NULL);
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@ -57,8 +57,6 @@
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* Basically, get_target_freq will run
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* devfreq_dev_profile.get_dev_status() to get the
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* status of the device (load = busy_time / total_time).
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* If no_central_polling is set, this callback is called
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* only with update_devfreq() notified by OPP.
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* @event_handler: Callback for devfreq core framework to notify events
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* to governors. Events include per device governor
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* init and exit, opp changes out of devfreq, suspend
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@ -91,6 +89,9 @@ int devfreq_update_target(struct devfreq *devfreq, unsigned long freq);
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static inline int devfreq_update_stats(struct devfreq *df)
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{
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if (!df->profile->get_dev_status)
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return -EINVAL;
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return df->profile->get_dev_status(df->dev.parent, &df->last_status);
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}
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#endif /* _GOVERNOR_H */
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@ -169,7 +169,7 @@ static struct platform_driver imx_bus_platdrv = {
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.probe = imx_bus_probe,
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.driver = {
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.name = "imx-bus-devfreq",
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.of_match_table = of_match_ptr(imx_bus_of_match),
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.of_match_table = imx_bus_of_match,
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},
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};
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module_platform_driver(imx_bus_platdrv);
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@ -280,18 +280,6 @@ static int imx8m_ddrc_get_cur_freq(struct device *dev, unsigned long *freq)
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return 0;
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}
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static int imx8m_ddrc_get_dev_status(struct device *dev,
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struct devfreq_dev_status *stat)
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{
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struct imx8m_ddrc *priv = dev_get_drvdata(dev);
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stat->busy_time = 0;
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stat->total_time = 0;
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stat->current_frequency = clk_get_rate(priv->dram_core);
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return 0;
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}
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static int imx8m_ddrc_init_freq_info(struct device *dev)
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{
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struct imx8m_ddrc *priv = dev_get_drvdata(dev);
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@ -429,9 +417,7 @@ static int imx8m_ddrc_probe(struct platform_device *pdev)
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if (ret < 0)
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goto err;
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priv->profile.polling_ms = 1000;
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priv->profile.target = imx8m_ddrc_target;
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priv->profile.get_dev_status = imx8m_ddrc_get_dev_status;
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priv->profile.exit = imx8m_ddrc_exit;
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priv->profile.get_cur_freq = imx8m_ddrc_get_cur_freq;
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priv->profile.initial_freq = clk_get_rate(priv->dram_core);
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@ -461,7 +447,7 @@ static struct platform_driver imx8m_ddrc_platdrv = {
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.probe = imx8m_ddrc_probe,
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.driver = {
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.name = "imx8m-ddrc-devfreq",
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.of_match_table = of_match_ptr(imx8m_ddrc_of_match),
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.of_match_table = imx8m_ddrc_of_match,
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},
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};
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module_platform_driver(imx8m_ddrc_platdrv);
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@ -324,22 +324,14 @@ static int rk3399_dmcfreq_probe(struct platform_device *pdev)
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mutex_init(&data->lock);
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data->vdd_center = devm_regulator_get(dev, "center");
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if (IS_ERR(data->vdd_center)) {
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if (PTR_ERR(data->vdd_center) == -EPROBE_DEFER)
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return -EPROBE_DEFER;
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dev_err(dev, "Cannot get the regulator \"center\"\n");
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return PTR_ERR(data->vdd_center);
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}
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if (IS_ERR(data->vdd_center))
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return dev_err_probe(dev, PTR_ERR(data->vdd_center),
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"Cannot get the regulator \"center\"\n");
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data->dmc_clk = devm_clk_get(dev, "dmc_clk");
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if (IS_ERR(data->dmc_clk)) {
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if (PTR_ERR(data->dmc_clk) == -EPROBE_DEFER)
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return -EPROBE_DEFER;
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dev_err(dev, "Cannot get the clk dmc_clk\n");
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return PTR_ERR(data->dmc_clk);
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}
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if (IS_ERR(data->dmc_clk))
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return dev_err_probe(dev, PTR_ERR(data->dmc_clk),
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"Cannot get the clk dmc_clk\n");
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data->edev = devfreq_event_get_edev_by_phandle(dev, "devfreq-events", 0);
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if (IS_ERR(data->edev))
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@ -38,6 +38,7 @@ enum devfreq_timer {
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struct devfreq;
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struct devfreq_governor;
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struct thermal_cooling_device;
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/**
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* struct devfreq_dev_status - Data given from devfreq user device to
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@ -98,11 +99,15 @@ struct devfreq_dev_status {
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* @freq_table: Optional list of frequencies to support statistics
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* and freq_table must be generated in ascending order.
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* @max_state: The size of freq_table.
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*
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* @is_cooling_device: A self-explanatory boolean giving the device a
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* cooling effect property.
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*/
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struct devfreq_dev_profile {
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unsigned long initial_freq;
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unsigned int polling_ms;
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enum devfreq_timer timer;
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bool is_cooling_device;
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int (*target)(struct device *dev, unsigned long *freq, u32 flags);
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int (*get_dev_status)(struct device *dev,
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@ -156,6 +161,7 @@ struct devfreq_stats {
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* @suspend_count: suspend requests counter for a device.
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* @stats: Statistics of devfreq device behavior
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* @transition_notifier_list: list head of DEVFREQ_TRANSITION_NOTIFIER notifier
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* @cdev: Cooling device pointer if the devfreq has cooling property
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* @nb_min: Notifier block for DEV_PM_QOS_MIN_FREQUENCY
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* @nb_max: Notifier block for DEV_PM_QOS_MAX_FREQUENCY
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*
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@ -198,6 +204,9 @@ struct devfreq {
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struct srcu_notifier_head transition_notifier_list;
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/* Pointer to the cooling device if used for thermal mitigation */
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struct thermal_cooling_device *cdev;
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struct notifier_block nb_min;
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struct notifier_block nb_max;
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};
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