mirror of
https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git
synced 2024-09-29 13:53:33 +00:00
- Multi-cast register fix (Matt)
- Fix workarounds on gen2-3 (Tvrtko) - Bigjoiner fix (Ville) - Make Guc default_list a const data (Jani) - Acquire forcewake before uncore read (Umesh) - Selftest fix (Umesh) - HuC related fixes (Daniele) - Fix some incorrect return values (Janusz) - Fix a memory leak in bios related code (Xia) - Fix VBT send packet port selection (Mikko) - DG2's DMC fix bump for Register noclaims and few restore (Gustavo) -----BEGIN PGP SIGNATURE----- iQEzBAABCAAdFiEEbSBwaO7dZQkcLOKj+mJfZA7rE8oFAmOI1sUACgkQ+mJfZA7r E8rYGwf/ZCchljqHFMHONnKpsMEZyk+M6VPStZV4/0INKC8ov9zoe0GG+yYj6vNG mE9+b6ZKUPJ5kLroiMIrkAu9fgRDKRlpToj7KQeMNQh0tjwGiXosfVsFO5snFAM2 /Z5WZGHpn0Wy9S9RJE6E6T25lqjqHPM5fp49jZsXNkG0jtKmG2sCkDSzudvxNitI 3X8NoCMX++7UE6206fwRCoYAJCiaW6Zgkx9uU2AacqK4CIq28mOftLNEcdTN0Ip4 wUjZLamPxbmHr5apINuSdRybj9HIDCq15Am5mrgKqU2CqB82s30XR3XFKzugSR7n H/23fVxGMx/O2Ha7jBugHzXwMF7nFQ== =k8G7 -----END PGP SIGNATURE----- Merge tag 'drm-intel-next-fixes-2022-12-01' of git://anongit.freedesktop.org/drm/drm-intel into drm-next - Multi-cast register fix (Matt) - Fix workarounds on gen2-3 (Tvrtko) - Bigjoiner fix (Ville) - Make Guc default_list a const data (Jani) - Acquire forcewake before uncore read (Umesh) - Selftest fix (Umesh) - HuC related fixes (Daniele) - Fix some incorrect return values (Janusz) - Fix a memory leak in bios related code (Xia) - Fix VBT send packet port selection (Mikko) - DG2's DMC fix bump for Register noclaims and few restore (Gustavo) Signed-off-by: Dave Airlie <airlied@redhat.com> From: Rodrigo Vivi <rodrigo.vivi@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/Y4jZBRw9KvlKgkr6@intel.com
This commit is contained in:
commit
b2268e2686
14 changed files with 113 additions and 65 deletions
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@ -414,7 +414,7 @@ static void *generate_lfp_data_ptrs(struct drm_i915_private *i915,
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ptrs->lvds_entries++;
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if (size != 0 || ptrs->lvds_entries != 3) {
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kfree(ptrs);
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kfree(ptrs_block);
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return NULL;
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}
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@ -3733,12 +3733,16 @@ static bool ilk_get_pipe_config(struct intel_crtc *crtc,
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static u8 bigjoiner_pipes(struct drm_i915_private *i915)
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{
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u8 pipes;
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if (DISPLAY_VER(i915) >= 12)
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return BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C) | BIT(PIPE_D);
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pipes = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C) | BIT(PIPE_D);
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else if (DISPLAY_VER(i915) >= 11)
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return BIT(PIPE_B) | BIT(PIPE_C);
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pipes = BIT(PIPE_B) | BIT(PIPE_C);
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else
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return 0;
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pipes = 0;
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return pipes & RUNTIME_INFO(i915)->pipe_mask;
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}
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static bool transcoder_ddi_func_is_enabled(struct drm_i915_private *dev_priv,
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@ -52,8 +52,8 @@
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#define DISPLAY_VER12_DMC_MAX_FW_SIZE ICL_DMC_MAX_FW_SIZE
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#define DG2_DMC_PATH DMC_PATH(dg2, 2, 07)
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#define DG2_DMC_VERSION_REQUIRED DMC_VERSION(2, 07)
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#define DG2_DMC_PATH DMC_PATH(dg2, 2, 08)
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#define DG2_DMC_VERSION_REQUIRED DMC_VERSION(2, 8)
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MODULE_FIRMWARE(DG2_DMC_PATH);
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#define ADLP_DMC_PATH DMC_PATH(adlp, 2, 16)
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@ -137,9 +137,9 @@ static enum port intel_dsi_seq_port_to_port(struct intel_dsi *intel_dsi,
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return ffs(intel_dsi->ports) - 1;
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if (seq_port) {
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if (intel_dsi->ports & PORT_B)
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if (intel_dsi->ports & BIT(PORT_B))
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return PORT_B;
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else if (intel_dsi->ports & PORT_C)
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else if (intel_dsi->ports & BIT(PORT_C))
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return PORT_C;
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}
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@ -677,8 +677,13 @@ int intel_gt_wait_for_idle(struct intel_gt *gt, long timeout)
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return -EINTR;
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}
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return timeout ? timeout : intel_uc_wait_for_idle(>->uc,
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remaining_timeout);
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if (timeout)
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return timeout;
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if (remaining_timeout < 0)
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remaining_timeout = 0;
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return intel_uc_wait_for_idle(>->uc, remaining_timeout);
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}
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int intel_gt_init(struct intel_gt *gt)
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@ -1035,9 +1040,9 @@ get_reg_and_bit(const struct intel_engine_cs *engine, const bool gen8,
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static int wait_for_invalidate(struct intel_gt *gt, struct reg_and_bit rb)
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{
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if (GRAPHICS_VER_FULL(gt->i915) >= IP_VER(12, 50))
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return intel_gt_mcr_wait_for_reg_fw(gt, rb.mcr_reg, rb.bit, 0,
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TLB_INVAL_TIMEOUT_US,
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TLB_INVAL_TIMEOUT_MS);
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return intel_gt_mcr_wait_for_reg(gt, rb.mcr_reg, rb.bit, 0,
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TLB_INVAL_TIMEOUT_US,
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TLB_INVAL_TIMEOUT_MS);
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else
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return __intel_wait_for_register_fw(gt->uncore, rb.reg, rb.bit, 0,
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TLB_INVAL_TIMEOUT_US,
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@ -730,17 +730,19 @@ void intel_gt_mcr_get_ss_steering(struct intel_gt *gt, unsigned int dss,
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*
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* Return: 0 if the register matches the desired condition, or -ETIMEDOUT.
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*/
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int intel_gt_mcr_wait_for_reg_fw(struct intel_gt *gt,
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i915_mcr_reg_t reg,
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u32 mask,
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u32 value,
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unsigned int fast_timeout_us,
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unsigned int slow_timeout_ms)
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int intel_gt_mcr_wait_for_reg(struct intel_gt *gt,
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i915_mcr_reg_t reg,
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u32 mask,
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u32 value,
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unsigned int fast_timeout_us,
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unsigned int slow_timeout_ms)
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{
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u32 reg_value = 0;
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#define done (((reg_value = intel_gt_mcr_read_any_fw(gt, reg)) & mask) == value)
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int ret;
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lockdep_assert_not_held(>->uncore->lock);
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#define done ((intel_gt_mcr_read_any(gt, reg) & mask) == value)
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/* Catch any overuse of this function */
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might_sleep_if(slow_timeout_ms);
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GEM_BUG_ON(fast_timeout_us > 20000);
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@ -37,12 +37,12 @@ void intel_gt_mcr_report_steering(struct drm_printer *p, struct intel_gt *gt,
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void intel_gt_mcr_get_ss_steering(struct intel_gt *gt, unsigned int dss,
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unsigned int *group, unsigned int *instance);
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int intel_gt_mcr_wait_for_reg_fw(struct intel_gt *gt,
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i915_mcr_reg_t reg,
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u32 mask,
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u32 value,
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unsigned int fast_timeout_us,
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unsigned int slow_timeout_ms);
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int intel_gt_mcr_wait_for_reg(struct intel_gt *gt,
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i915_mcr_reg_t reg,
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u32 mask,
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u32 value,
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unsigned int fast_timeout_us,
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unsigned int slow_timeout_ms);
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/*
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* Helper for for_each_ss_steering loop. On pre-Xe_HP platforms, subslice
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@ -199,7 +199,7 @@ out_active: spin_lock(&timelines->lock);
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if (remaining_timeout)
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*remaining_timeout = timeout;
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return active_count ? timeout : 0;
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return active_count ? timeout ?: -ETIME : 0;
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}
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static void retire_work_handler(struct work_struct *work)
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@ -3011,7 +3011,7 @@ general_render_compute_wa_init(struct intel_engine_cs *engine, struct i915_wa_li
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static void
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engine_init_workarounds(struct intel_engine_cs *engine, struct i915_wa_list *wal)
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{
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if (I915_SELFTEST_ONLY(GRAPHICS_VER(engine->i915) < 4))
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if (GRAPHICS_VER(engine->i915) < 4)
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return;
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engine_fake_wa_init(engine, wal);
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@ -3036,9 +3036,6 @@ void intel_engine_init_workarounds(struct intel_engine_cs *engine)
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{
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struct i915_wa_list *wal = &engine->wa_list;
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if (GRAPHICS_VER(engine->i915) < 4)
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return;
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wa_init_start(wal, engine->gt, "engine", engine->name);
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engine_init_workarounds(engine, wal);
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wa_init_finish(wal);
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@ -317,7 +317,7 @@ static int live_engine_busy_stats(void *arg)
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ENGINE_TRACE(engine, "measuring busy time\n");
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preempt_disable();
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de = intel_engine_get_busy_time(engine, &t[0]);
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mdelay(10);
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mdelay(100);
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de = ktime_sub(intel_engine_get_busy_time(engine, &t[1]), de);
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preempt_enable();
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dt = ktime_sub(t[1], t[0]);
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@ -170,7 +170,7 @@ static const struct __guc_mmio_reg_descr empty_regs_list[] = {
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}
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/* List of lists */
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static struct __guc_mmio_reg_descr_group default_lists[] = {
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static const struct __guc_mmio_reg_descr_group default_lists[] = {
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MAKE_REGLIST(default_global_regs, PF, GLOBAL, 0),
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MAKE_REGLIST(default_rc_class_regs, PF, ENGINE_CLASS, GUC_RENDER_CLASS),
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MAKE_REGLIST(xe_lpd_rc_inst_regs, PF, ENGINE_INSTANCE, GUC_RENDER_CLASS),
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@ -211,6 +211,30 @@ void intel_huc_unregister_gsc_notifier(struct intel_huc *huc, struct bus_type *b
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huc->delayed_load.nb.notifier_call = NULL;
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}
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static void delayed_huc_load_init(struct intel_huc *huc)
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{
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/*
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* Initialize fence to be complete as this is expected to be complete
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* unless there is a delayed HuC load in progress.
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*/
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i915_sw_fence_init(&huc->delayed_load.fence,
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sw_fence_dummy_notify);
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i915_sw_fence_commit(&huc->delayed_load.fence);
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hrtimer_init(&huc->delayed_load.timer, CLOCK_MONOTONIC, HRTIMER_MODE_REL);
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huc->delayed_load.timer.function = huc_delayed_load_timer_callback;
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}
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static void delayed_huc_load_fini(struct intel_huc *huc)
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{
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/*
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* the fence is initialized in init_early, so we need to clean it up
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* even if HuC loading is off.
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*/
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delayed_huc_load_complete(huc);
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i915_sw_fence_fini(&huc->delayed_load.fence);
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}
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static bool vcs_supported(struct intel_gt *gt)
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{
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intel_engine_mask_t mask = gt->info.engine_mask;
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@ -241,6 +265,15 @@ void intel_huc_init_early(struct intel_huc *huc)
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intel_uc_fw_init_early(&huc->fw, INTEL_UC_FW_TYPE_HUC);
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/*
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* we always init the fence as already completed, even if HuC is not
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* supported. This way we don't have to distinguish between HuC not
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* supported/disabled or already loaded, and can focus on if the load
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* is currently in progress (fence not complete) or not, which is what
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* we care about for stalling userspace submissions.
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*/
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delayed_huc_load_init(huc);
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if (!vcs_supported(gt)) {
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intel_uc_fw_change_status(&huc->fw, INTEL_UC_FIRMWARE_NOT_SUPPORTED);
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return;
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@ -255,17 +288,6 @@ void intel_huc_init_early(struct intel_huc *huc)
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huc->status.mask = HUC_FW_VERIFIED;
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huc->status.value = HUC_FW_VERIFIED;
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}
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/*
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* Initialize fence to be complete as this is expected to be complete
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* unless there is a delayed HuC reload in progress.
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*/
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i915_sw_fence_init(&huc->delayed_load.fence,
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sw_fence_dummy_notify);
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i915_sw_fence_commit(&huc->delayed_load.fence);
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hrtimer_init(&huc->delayed_load.timer, CLOCK_MONOTONIC, HRTIMER_MODE_REL);
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huc->delayed_load.timer.function = huc_delayed_load_timer_callback;
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}
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#define HUC_LOAD_MODE_STRING(x) (x ? "GSC" : "legacy")
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@ -329,13 +351,14 @@ int intel_huc_init(struct intel_huc *huc)
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void intel_huc_fini(struct intel_huc *huc)
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{
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if (!intel_uc_fw_is_loadable(&huc->fw))
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return;
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/*
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* the fence is initialized in init_early, so we need to clean it up
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* even if HuC loading is off.
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*/
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delayed_huc_load_fini(huc);
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delayed_huc_load_complete(huc);
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i915_sw_fence_fini(&huc->delayed_load.fence);
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intel_uc_fw_fini(&huc->fw);
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if (intel_uc_fw_is_loadable(&huc->fw))
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intel_uc_fw_fini(&huc->fw);
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}
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void intel_huc_suspend(struct intel_huc *huc)
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@ -722,6 +722,7 @@ int intel_uc_runtime_resume(struct intel_uc *uc)
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static const struct intel_uc_ops uc_ops_off = {
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.init_hw = __uc_check_hw,
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.fini = __uc_fini, /* to clean-up the init_early initialization */
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};
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static const struct intel_uc_ops uc_ops_on = {
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@ -382,20 +382,6 @@ __uncore_write(write_notrace, 32, l, false)
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*/
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__uncore_read(read64, 64, q, true)
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static inline u64
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intel_uncore_read64_2x32(struct intel_uncore *uncore,
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i915_reg_t lower_reg, i915_reg_t upper_reg)
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{
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u32 upper, lower, old_upper, loop = 0;
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upper = intel_uncore_read(uncore, upper_reg);
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do {
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old_upper = upper;
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lower = intel_uncore_read(uncore, lower_reg);
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upper = intel_uncore_read(uncore, upper_reg);
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} while (upper != old_upper && loop++ < 2);
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return (u64)upper << 32 | lower;
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}
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#define intel_uncore_posting_read(...) ((void)intel_uncore_read_notrace(__VA_ARGS__))
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#define intel_uncore_posting_read16(...) ((void)intel_uncore_read16_notrace(__VA_ARGS__))
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@ -455,6 +441,36 @@ static inline void intel_uncore_rmw_fw(struct intel_uncore *uncore,
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intel_uncore_write_fw(uncore, reg, val);
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}
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static inline u64
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intel_uncore_read64_2x32(struct intel_uncore *uncore,
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i915_reg_t lower_reg, i915_reg_t upper_reg)
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{
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u32 upper, lower, old_upper, loop = 0;
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enum forcewake_domains fw_domains;
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unsigned long flags;
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fw_domains = intel_uncore_forcewake_for_reg(uncore, lower_reg,
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FW_REG_READ);
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fw_domains |= intel_uncore_forcewake_for_reg(uncore, upper_reg,
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FW_REG_READ);
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spin_lock_irqsave(&uncore->lock, flags);
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intel_uncore_forcewake_get__locked(uncore, fw_domains);
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upper = intel_uncore_read_fw(uncore, upper_reg);
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do {
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old_upper = upper;
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lower = intel_uncore_read_fw(uncore, lower_reg);
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upper = intel_uncore_read_fw(uncore, upper_reg);
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} while (upper != old_upper && loop++ < 2);
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intel_uncore_forcewake_put__locked(uncore, fw_domains);
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spin_unlock_irqrestore(&uncore->lock, flags);
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return (u64)upper << 32 | lower;
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}
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static inline int intel_uncore_write_and_verify(struct intel_uncore *uncore,
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i915_reg_t reg, u32 val,
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u32 mask, u32 expected_val)
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Reference in a new issue