arm: dts: Update cache properties for broadcom

The DeviceTree Specification v0.3 specifies that the cache node
'compatible' and 'cache-level' properties are 'required'. Cf.
s3.8 Multi-level and Shared Cache Nodes
The 'cache-unified' property should be present if one of the
properties for unified cache is present ('cache-size', ...).

Update the Device Trees accordingly.

Signed-off-by: Pierre Gondois <pierre.gondois@arm.com>
Link: https://lore.kernel.org/r/20221122163208.3810985-2-pierre.gondois@arm.com
Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>

arch/arm/boot/dts/bcm2711.dtsi

@@ -536,6 +536,7 @@ cpu3: cpu@3 {
 		 */
 		l2: l2-cache0 {
 			compatible = "cache";
+			cache-unified;
 			cache-size = <0x100000>;
 			cache-line-size = <64>;
 			cache-sets = <1024>; // 1MiB(size)/64(line-size)=16384ways/16-way set

arch/arm/boot/dts/bcm2836.dtsi

@@ -112,6 +112,7 @@ v7_cpu3: cpu@3 {
 		 */
 		l2: l2-cache0 {
 			compatible = "cache";
+			cache-unified;
 			cache-size = <0x80000>;
 			cache-line-size = <64>;
 			cache-sets = <1024>; // 512KiB(size)/64(line-size)=8192ways/8-way set

arch/arm/boot/dts/bcm2837.dtsi

@@ -114,6 +114,7 @@ cpu3: cpu@3 {
 		 */
 		l2: l2-cache0 {
 			compatible = "cache";
+			cache-unified;
 			cache-size = <0x80000>;
 			cache-line-size = <64>;
 			cache-sets = <512>; // 512KiB(size)/64(line-size)=8192ways/16-way set

arch/arm/boot/dts/bcm47622.dtsi

@@ -51,6 +51,7 @@ CA7_3: cpu@3 {
 
 		L2_0: l2-cache0 {
 			compatible = "cache";
+			cache-level = <2>;
 		};
 	};
 

arch/arm/boot/dts/bcm63148.dtsi

@@ -35,6 +35,7 @@ B15_1: cpu@1 {
 
 		L2_0: l2-cache0 {
 			compatible = "cache";
+			cache-level = <2>;
 		};
 	};
 

arch/arm/boot/dts/bcm63178.dtsi

@@ -43,6 +43,7 @@ CA7_2: cpu@2 {
 
 		L2_0: l2-cache0 {
 			compatible = "cache";
+			cache-level = <2>;
 		};
 	};
 

arch/arm/boot/dts/bcm6756.dtsi

@@ -51,6 +51,7 @@ CA7_3: cpu@3 {
 
 		L2_0: l2-cache0 {
 			compatible = "cache";
+			cache-level = <2>;
 		};
 	};
 

arch/arm/boot/dts/bcm6846.dtsi

@@ -35,6 +35,7 @@ CA7_1: cpu@1 {
 
 		L2_0: l2-cache0 {
 			compatible = "cache";
+			cache-level = <2>;
 		};
 	};
 

arch/arm/boot/dts/bcm6855.dtsi

@@ -43,6 +43,7 @@ CA7_2: cpu@2 {
 
 		L2_0: l2-cache0 {
 			compatible = "cache";
+			cache-level = <2>;
 		};
 	};
 

arch/arm/boot/dts/bcm6878.dtsi

@@ -35,6 +35,7 @@ CA7_1: cpu@1 {
 
 		L2_0: l2-cache0 {
 			compatible = "cache";
+			cache-level = <2>;
 		};
 	};