mirrors/linux-stable
1
0
Fork 0
mirror of https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git synced 2024-10-14 12:37:32 +00:00
Code Issues Releases Wiki Activity

PCI: tegra: Increase the deskew retry time

Browse source 
Sometimes link speed change from Gen2 to Gen1 fails due to instability
in deskew logic on lane-0 in Tegra210. Increase the deskew retry time
to resolve this issue.

Signed-off-by: Manikanta Maddireddy <mmaddireddy@nvidia.com>
Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Acked-by: Thierry Reding <treding@nvidia.com>
This commit is contained in:
Manikanta Maddireddy 2019-06-18 23:31:52 +05:30 committed by Lorenzo Pieralisi
parent f1178099a6
commit b2634cd0d2
1 changed files with 30 additions and 0 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

30
drivers/pci/controller/pci-tegra.c
View file

@ -209,6 +209,10 @@
#define RP_VEND_XP_OPPORTUNISTIC_ACK (1 << 27)
#define RP_VEND_XP_OPPORTUNISTIC_UPDATEFC (1 << 28)
#define RP_VEND_CTL0 0x00000f44
#define RP_VEND_CTL0_DSK_RST_PULSE_WIDTH_MASK (0xf << 12)
#define RP_VEND_CTL0_DSK_RST_PULSE_WIDTH (0x9 << 12)
#define RP_VEND_CTL1 0x00000f48
#define RP_VEND_CTL1_ERPT (1 << 13)
@ -305,6 +309,7 @@ struct tegra_pcie_soc {
bool force_pca_enable;
bool program_uphy;
bool update_clamp_threshold;
bool program_deskew_time;
struct {
struct {
u32 rp_ectl_2_r1;
@ -620,6 +625,24 @@ static void tegra_pcie_program_ectl_settings(struct tegra_pcie_port *port)
writel(value, port->base + RP_ECTL_6_R2);
}
static void tegra_pcie_apply_sw_fixup(struct tegra_pcie_port *port)
{
const struct tegra_pcie_soc *soc = port->pcie->soc;
u32 value;
/*
* Sometimes link speed change from Gen2 to Gen1 fails due to
* instability in deskew logic on lane-0. Increase the deskew
* retry time to resolve this issue.
*/
if (soc->program_deskew_time) {
value = readl(port->base + RP_VEND_CTL0);
value &= ~RP_VEND_CTL0_DSK_RST_PULSE_WIDTH_MASK;
value |= RP_VEND_CTL0_DSK_RST_PULSE_WIDTH;
writel(value, port->base + RP_VEND_CTL0);
}
}
static void tegra_pcie_port_enable(struct tegra_pcie_port *port)
{
unsigned long ctrl = tegra_pcie_port_get_pex_ctrl(port);
@ -649,6 +672,8 @@ static void tegra_pcie_port_enable(struct tegra_pcie_port *port)
if (soc->ectl.enable)
tegra_pcie_program_ectl_settings(port);
tegra_pcie_apply_sw_fixup(port);
}
static void tegra_pcie_port_disable(struct tegra_pcie_port *port)
@ -2375,6 +2400,7 @@ static const struct tegra_pcie_soc tegra20_pcie = {
.force_pca_enable = false,
.program_uphy = true,
.update_clamp_threshold = false,
.program_deskew_time = false,
.ectl.enable = false,
};
@ -2400,6 +2426,7 @@ static const struct tegra_pcie_soc tegra30_pcie = {
.force_pca_enable = false,
.program_uphy = true,
.update_clamp_threshold = false,
.program_deskew_time = false,
.ectl.enable = false,
};
@ -2418,6 +2445,7 @@ static const struct tegra_pcie_soc tegra124_pcie = {
.force_pca_enable = false,
.program_uphy = true,
.update_clamp_threshold = true,
.program_deskew_time = false,
.ectl.enable = false,
};
@ -2436,6 +2464,7 @@ static const struct tegra_pcie_soc tegra210_pcie = {
.force_pca_enable = true,
.program_uphy = true,
.update_clamp_threshold = true,
.program_deskew_time = true,
.ectl = {
.regs = {
.rp_ectl_2_r1 = 0x0000000f,
@ -2473,6 +2502,7 @@ static const struct tegra_pcie_soc tegra186_pcie = {
.force_pca_enable = false,
.program_uphy = false,
.update_clamp_threshold = false,
.program_deskew_time = false,
.ectl.enable = false,
};