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drm: rcar-du: Add r8a779a0 device support

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Extend the rcar_du_device_info structure and rcar_du_output enum to
support DSI outputs and utilise these additions to provide support for
the R8A779A0 V3U platform.

Signed-off-by: Kieran Bingham <kieran.bingham+renesas@ideasonboard.com>
Reviewed-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
This commit is contained in:
Kieran Bingham 2021-09-23 00:47:26 +01:00 committed by Laurent Pinchart
parent cc6f88b96b
commit b291fdcf51
4 changed files with 27 additions and 0 deletions
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20
drivers/gpu/drm/rcar-du/rcar_du_drv.c
View file

@ -490,6 +490,25 @@ static const struct rcar_du_device_info rcar_du_r8a7799x_info = {
.lvds_clk_mask = BIT(1) | BIT(0),
};
static const struct rcar_du_device_info rcar_du_r8a779a0_info = {
.gen = 3,
.features = RCAR_DU_FEATURE_CRTC_IRQ
| RCAR_DU_FEATURE_VSP1_SOURCE,
.channels_mask = BIT(1) | BIT(0),
.routes = {
/* R8A779A0 has two MIPI DSI outputs. */
[RCAR_DU_OUTPUT_DSI0] = {
.possible_crtcs = BIT(0),
.port = 0,
},
[RCAR_DU_OUTPUT_DSI1] = {
.possible_crtcs = BIT(1),
.port = 1,
},
},
.dsi_clk_mask = BIT(1) | BIT(0),
};
static const struct of_device_id rcar_du_of_table[] = {
{ .compatible = "renesas,du-r8a7742", .data = &rcar_du_r8a7790_info },
{ .compatible = "renesas,du-r8a7743", .data = &rzg1_du_r8a7743_info },
@ -514,6 +533,7 @@ static const struct of_device_id rcar_du_of_table[] = {
{ .compatible = "renesas,du-r8a77980", .data = &rcar_du_r8a77970_info },
{ .compatible = "renesas,du-r8a77990", .data = &rcar_du_r8a7799x_info },
{ .compatible = "renesas,du-r8a77995", .data = &rcar_du_r8a7799x_info },
{ .compatible = "renesas,du-r8a779a0", .data = &rcar_du_r8a779a0_info },
{ }
};

4
drivers/gpu/drm/rcar-du/rcar_du_drv.h
View file

@ -37,6 +37,8 @@ struct rcar_du_device;
enum rcar_du_output {
RCAR_DU_OUTPUT_DPAD0,
RCAR_DU_OUTPUT_DPAD1,
RCAR_DU_OUTPUT_DSI0,
RCAR_DU_OUTPUT_DSI1,
RCAR_DU_OUTPUT_HDMI0,
RCAR_DU_OUTPUT_HDMI1,
RCAR_DU_OUTPUT_LVDS0,
@ -68,6 +70,7 @@ struct rcar_du_output_routing {
* @routes: array of CRTC to output routes, indexed by output (RCAR_DU_OUTPUT_*)
* @num_lvds: number of internal LVDS encoders
* @dpll_mask: bit mask of DU channels equipped with a DPLL
* @dsi_clk_mask: bitmask of channels that can use the DSI clock as dot clock
* @lvds_clk_mask: bitmask of channels that can use the LVDS clock as dot clock
*/
struct rcar_du_device_info {
@ -78,6 +81,7 @@ struct rcar_du_device_info {
struct rcar_du_output_routing routes[RCAR_DU_OUTPUT_MAX];
unsigned int num_lvds;
unsigned int dpll_mask;
unsigned int dsi_clk_mask;
unsigned int lvds_clk_mask;
};

2
drivers/gpu/drm/rcar-du/rcar_du_group.c
View file

@ -124,6 +124,8 @@ static void rcar_du_group_setup_didsr(struct rcar_du_group *rgrp)
if (rcdu->info->lvds_clk_mask & BIT(rcrtc->index))
didsr |= DIDSR_LDCS_LVDS0(i)
| DIDSR_PDCS_CLK(i, 0);
else if (rcdu->info->dsi_clk_mask & BIT(rcrtc->index))
didsr |= DIDSR_LDCS_DSI(i);
else
didsr |= DIDSR_LDCS_DCLKIN(i)
| DIDSR_PDCS_CLK(i, 0);

1
drivers/gpu/drm/rcar-du/rcar_du_regs.h
View file

@ -258,6 +258,7 @@
#define DIDSR 0x20028
#define DIDSR_CODE (0x7790 << 16)
#define DIDSR_LDCS_DCLKIN(n) (0 << (8 + (n) * 2))
#define DIDSR_LDCS_DSI(n) (2 << (8 + (n) * 2)) /* V3U only */
#define DIDSR_LDCS_LVDS0(n) (2 << (8 + (n) * 2))
#define DIDSR_LDCS_LVDS1(n) (3 << (8 + (n) * 2))
#define DIDSR_LDCS_MASK(n) (3 << (8 + (n) * 2))