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clk: qcom: gcc-ipq806x: add CryptoEngine clocks
Add missing CryptoEngine clocks and pll11 required clock. Signed-off-by: Ansuel Smith <ansuelsmth@gmail.com> Reviewed-by: Stephen Boyd <sboyd@kernel.org> Tested-by: Jonathan McDowell <noodles@earth.li> Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Link: https://lore.kernel.org/r/20220226135235.10051-13-ansuelsmth@gmail.com
This commit is contained in:
Ansuel Smith
Bjorn Andersson
parent
b565d66403
commit
b293510f39
1 changed files with 244 additions and 0 deletions
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@ -256,6 +256,24 @@ static struct clk_pll pll18 = {
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},
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};
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static struct clk_pll pll11 = {
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.l_reg = 0x3184,
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.m_reg = 0x3188,
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.n_reg = 0x318c,
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.config_reg = 0x3194,
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.mode_reg = 0x3180,
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.status_reg = 0x3198,
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.status_bit = 16,
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.clkr.hw.init = &(struct clk_init_data){
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.name = "pll11",
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.parent_data = &(const struct clk_parent_data){
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.fw_name = "pxo",
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},
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.num_parents = 1,
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.ops = &clk_pll_ops,
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},
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};
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enum {
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P_PXO,
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P_PLL8,
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@ -264,6 +282,7 @@ enum {
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P_CXO,
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P_PLL14,
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P_PLL18,
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P_PLL11,
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};
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static const struct parent_map gcc_pxo_pll8_map[] = {
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@ -331,6 +350,44 @@ static const struct clk_parent_data gcc_pxo_pll8_pll14_pll18_pll0[] = {
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{ .hw = &pll18.clkr.hw },
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};
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static const struct parent_map gcc_pxo_pll8_pll0_pll14_pll18_pll11_map[] = {
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{ P_PXO, 0 },
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{ P_PLL8, 4 },
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{ P_PLL0, 2 },
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{ P_PLL14, 5 },
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{ P_PLL18, 1 },
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{ P_PLL11, 3 },
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};
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static const struct clk_parent_data gcc_pxo_pll8_pll0_pll14_pll18_pll11[] = {
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{ .fw_name = "pxo" },
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{ .hw = &pll8_vote.hw },
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{ .hw = &pll0_vote.hw },
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{ .hw = &pll14.clkr.hw },
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{ .hw = &pll18.clkr.hw },
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{ .hw = &pll11.clkr.hw },
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};
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static const struct parent_map gcc_pxo_pll3_pll0_pll14_pll18_pll11_map[] = {
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{ P_PXO, 0 },
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{ P_PLL3, 6 },
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{ P_PLL0, 2 },
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{ P_PLL14, 5 },
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{ P_PLL18, 1 },
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{ P_PLL11, 3 },
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};
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static const struct clk_parent_data gcc_pxo_pll3_pll0_pll14_pll18_pll11[] = {
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{ .fw_name = "pxo" },
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{ .hw = &pll3.clkr.hw },
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{ .hw = &pll0_vote.hw },
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{ .hw = &pll14.clkr.hw },
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{ .hw = &pll18.clkr.hw },
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{ .hw = &pll11.clkr.hw },
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};
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static struct freq_tbl clk_tbl_gsbi_uart[] = {
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{ 1843200, P_PLL8, 2, 6, 625 },
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{ 3686400, P_PLL8, 2, 12, 625 },
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@ -2824,6 +2881,186 @@ static struct clk_dyn_rcg ubi32_core2_src_clk = {
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},
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};
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static const struct freq_tbl clk_tbl_ce5_core[] = {
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{ 150000000, P_PLL3, 8, 1, 1 },
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{ 213200000, P_PLL11, 5, 1, 1 },
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{ }
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};
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static struct clk_dyn_rcg ce5_core_src = {
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.ns_reg[0] = 0x36C4,
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.ns_reg[1] = 0x36C8,
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.bank_reg = 0x36C0,
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.s[0] = {
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.src_sel_shift = 0,
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.parent_map = gcc_pxo_pll3_pll0_pll14_pll18_pll11_map,
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},
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.s[1] = {
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.src_sel_shift = 0,
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.parent_map = gcc_pxo_pll3_pll0_pll14_pll18_pll11_map,
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},
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.p[0] = {
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.pre_div_shift = 3,
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.pre_div_width = 4,
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},
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.p[1] = {
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.pre_div_shift = 3,
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.pre_div_width = 4,
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},
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.mux_sel_bit = 0,
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.freq_tbl = clk_tbl_ce5_core,
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.clkr = {
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.enable_reg = 0x36C0,
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.enable_mask = BIT(1),
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.hw.init = &(struct clk_init_data){
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.name = "ce5_core_src",
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.parent_data = gcc_pxo_pll3_pll0_pll14_pll18_pll11,
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.num_parents = ARRAY_SIZE(gcc_pxo_pll3_pll0_pll14_pll18_pll11),
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.ops = &clk_dyn_rcg_ops,
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},
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},
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};
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static struct clk_branch ce5_core_clk = {
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.halt_reg = 0x2FDC,
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.halt_bit = 5,
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.hwcg_reg = 0x36CC,
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.hwcg_bit = 6,
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.clkr = {
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.enable_reg = 0x36CC,
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.enable_mask = BIT(4),
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.hw.init = &(struct clk_init_data){
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.name = "ce5_core_clk",
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.parent_hws = (const struct clk_hw*[]){
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&ce5_core_src.clkr.hw,
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},
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.num_parents = 1,
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.ops = &clk_branch_ops,
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.flags = CLK_SET_RATE_PARENT,
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},
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},
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};
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static const struct freq_tbl clk_tbl_ce5_a_clk[] = {
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{ 160000000, P_PLL0, 5, 1, 1 },
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{ 213200000, P_PLL11, 5, 1, 1 },
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{ }
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};
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static struct clk_dyn_rcg ce5_a_clk_src = {
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.ns_reg[0] = 0x3d84,
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.ns_reg[1] = 0x3d88,
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.bank_reg = 0x3d80,
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.s[0] = {
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.src_sel_shift = 0,
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.parent_map = gcc_pxo_pll8_pll0_pll14_pll18_pll11_map,
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},
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.s[1] = {
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.src_sel_shift = 0,
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.parent_map = gcc_pxo_pll8_pll0_pll14_pll18_pll11_map,
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},
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.p[0] = {
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.pre_div_shift = 3,
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.pre_div_width = 4,
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},
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.p[1] = {
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.pre_div_shift = 3,
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.pre_div_width = 4,
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},
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.mux_sel_bit = 0,
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.freq_tbl = clk_tbl_ce5_a_clk,
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.clkr = {
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.enable_reg = 0x3d80,
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.enable_mask = BIT(1),
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.hw.init = &(struct clk_init_data){
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.name = "ce5_a_clk_src",
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.parent_data = gcc_pxo_pll8_pll0_pll14_pll18_pll11,
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.num_parents = ARRAY_SIZE(gcc_pxo_pll8_pll0_pll14_pll18_pll11),
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.ops = &clk_dyn_rcg_ops,
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},
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},
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};
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static struct clk_branch ce5_a_clk = {
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.halt_reg = 0x3c20,
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.halt_bit = 12,
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.hwcg_reg = 0x3d8c,
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.hwcg_bit = 6,
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.clkr = {
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.enable_reg = 0x3d8c,
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.enable_mask = BIT(4),
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.hw.init = &(struct clk_init_data){
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.name = "ce5_a_clk",
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.parent_hws = (const struct clk_hw*[]){
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&ce5_a_clk_src.clkr.hw,
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},
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.num_parents = 1,
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.ops = &clk_branch_ops,
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.flags = CLK_SET_RATE_PARENT,
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},
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},
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};
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static const struct freq_tbl clk_tbl_ce5_h_clk[] = {
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{ 160000000, P_PLL0, 5, 1, 1 },
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{ 213200000, P_PLL11, 5, 1, 1 },
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{ }
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};
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static struct clk_dyn_rcg ce5_h_clk_src = {
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.ns_reg[0] = 0x3c64,
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.ns_reg[1] = 0x3c68,
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.bank_reg = 0x3c60,
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.s[0] = {
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.src_sel_shift = 0,
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.parent_map = gcc_pxo_pll8_pll0_pll14_pll18_pll11_map,
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},
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.s[1] = {
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.src_sel_shift = 0,
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.parent_map = gcc_pxo_pll8_pll0_pll14_pll18_pll11_map,
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},
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.p[0] = {
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.pre_div_shift = 3,
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.pre_div_width = 4,
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},
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.p[1] = {
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.pre_div_shift = 3,
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.pre_div_width = 4,
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},
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.mux_sel_bit = 0,
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.freq_tbl = clk_tbl_ce5_h_clk,
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.clkr = {
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.enable_reg = 0x3c60,
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.enable_mask = BIT(1),
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.hw.init = &(struct clk_init_data){
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.name = "ce5_h_clk_src",
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.parent_data = gcc_pxo_pll8_pll0_pll14_pll18_pll11,
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.num_parents = ARRAY_SIZE(gcc_pxo_pll8_pll0_pll14_pll18_pll11),
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.ops = &clk_dyn_rcg_ops,
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},
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},
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};
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static struct clk_branch ce5_h_clk = {
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.halt_reg = 0x3c20,
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.halt_bit = 11,
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.hwcg_reg = 0x3c6c,
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.hwcg_bit = 6,
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.clkr = {
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.enable_reg = 0x3c6c,
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.enable_mask = BIT(4),
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.hw.init = &(struct clk_init_data){
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.name = "ce5_h_clk",
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.parent_hws = (const struct clk_hw*[]){
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&ce5_h_clk_src.clkr.hw,
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},
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.num_parents = 1,
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.ops = &clk_branch_ops,
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.flags = CLK_SET_RATE_PARENT,
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},
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},
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};
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static struct clk_regmap *gcc_ipq806x_clks[] = {
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[PLL0] = &pll0.clkr,
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[PLL0_VOTE] = &pll0_vote,
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@ -2831,6 +3068,7 @@ static struct clk_regmap *gcc_ipq806x_clks[] = {
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[PLL4_VOTE] = &pll4_vote,
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[PLL8] = &pll8.clkr,
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[PLL8_VOTE] = &pll8_vote,
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[PLL11] = &pll11.clkr,
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[PLL14] = &pll14.clkr,
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[PLL14_VOTE] = &pll14_vote,
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[PLL18] = &pll18.clkr,
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@ -2945,6 +3183,12 @@ static struct clk_regmap *gcc_ipq806x_clks[] = {
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[PLL9] = &hfpll0.clkr,
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[PLL10] = &hfpll1.clkr,
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[PLL12] = &hfpll_l2.clkr,
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[CE5_A_CLK_SRC] = &ce5_a_clk_src.clkr,
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[CE5_A_CLK] = &ce5_a_clk.clkr,
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[CE5_H_CLK_SRC] = &ce5_h_clk_src.clkr,
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[CE5_H_CLK] = &ce5_h_clk.clkr,
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[CE5_CORE_CLK_SRC] = &ce5_core_src.clkr,
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[CE5_CORE_CLK] = &ce5_core_clk.clkr,
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};
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static const struct qcom_reset_map gcc_ipq806x_resets[] = {
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