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OMAP3 SRAM: renumber registers to make space for argument passing
Renumber registers in omap3_sram_configure_core_dpll() assembly code to make space for additional parameters. Signed-off-by: Paul Walmsley <paul@pwsan.com>
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parent
98cfe5abf2
commit
b2abb271a5
1 changed files with 57 additions and 57 deletions
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@ -63,50 +63,50 @@ ENTRY(omap3_sram_configure_core_dpll)
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mov r0, #0 @ return value
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ldmfd sp!, {r1-r12, pc} @ restore regs and return
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unlock_dll:
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ldr r4, omap3_sdrc_dlla_ctrl
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ldr r5, [r4]
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orr r5, r5, #0x4
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str r5, [r4] @ (no OCP barrier needed)
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ldr r11, omap3_sdrc_dlla_ctrl
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ldr r12, [r11]
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orr r12, r12, #0x4
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str r12, [r11] @ (no OCP barrier needed)
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bx lr
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lock_dll:
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ldr r4, omap3_sdrc_dlla_ctrl
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ldr r5, [r4]
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bic r5, r5, #0x4
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str r5, [r4] @ (no OCP barrier needed)
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ldr r11, omap3_sdrc_dlla_ctrl
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ldr r12, [r11]
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bic r12, r12, #0x4
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str r12, [r11] @ (no OCP barrier needed)
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bx lr
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sdram_in_selfrefresh:
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ldr r4, omap3_sdrc_power @ read the SDRC_POWER register
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ldr r5, [r4] @ read the contents of SDRC_POWER
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mov r9, r5 @ keep a copy of SDRC_POWER bits
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orr r5, r5, #0x40 @ enable self refresh on idle req
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bic r5, r5, #0x4 @ clear PWDENA
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str r5, [r4] @ write back to SDRC_POWER register
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ldr r5, [r4] @ posted-write barrier for SDRC
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ldr r4, omap3_cm_iclken1_core @ read the CM_ICLKEN1_CORE reg
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ldr r5, [r4]
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bic r5, r5, #0x2 @ disable iclk bit for SDRC
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str r5, [r4]
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ldr r11, omap3_sdrc_power @ read the SDRC_POWER register
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ldr r12, [r11] @ read the contents of SDRC_POWER
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mov r9, r12 @ keep a copy of SDRC_POWER bits
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orr r12, r12, #0x40 @ enable self refresh on idle req
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bic r12, r12, #0x4 @ clear PWDENA
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str r12, [r11] @ write back to SDRC_POWER register
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ldr r12, [r11] @ posted-write barrier for SDRC
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ldr r11, omap3_cm_iclken1_core @ read the CM_ICLKEN1_CORE reg
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ldr r12, [r11]
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bic r12, r12, #0x2 @ disable iclk bit for SDRC
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str r12, [r11]
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wait_sdrc_idle:
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ldr r4, omap3_cm_idlest1_core
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ldr r5, [r4]
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and r5, r5, #0x2 @ check for SDRC idle
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cmp r5, #2
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ldr r11, omap3_cm_idlest1_core
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ldr r12, [r11]
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and r12, r12, #0x2 @ check for SDRC idle
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cmp r12, #2
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bne wait_sdrc_idle
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bx lr
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configure_core_dpll:
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ldr r4, omap3_cm_clksel1_pll
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ldr r5, [r4]
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ldr r6, core_m2_mask_val @ modify m2 for core dpll
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and r5, r5, r6
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orr r5, r5, r3, lsl #0x1B @ r3 contains the M2 val
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str r5, [r4]
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ldr r5, [r4] @ posted-write barrier for CM
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mov r5, #0x800 @ wait for the clock to stabilise
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ldr r11, omap3_cm_clksel1_pll
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ldr r12, [r11]
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ldr r10, core_m2_mask_val @ modify m2 for core dpll
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and r12, r12, r10
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orr r12, r12, r3, lsl #0x1B @ r3 contains the M2 val
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str r12, [r11]
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ldr r12, [r11] @ posted-write barrier for CM
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mov r12, #0x800 @ wait for the clock to stabilise
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cmp r3, #2
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bne wait_clk_stable
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bx lr
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wait_clk_stable:
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subs r5, r5, #1
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subs r12, r12, #1
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bne wait_clk_stable
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nop
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nop
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@ -120,42 +120,42 @@ wait_clk_stable:
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nop
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bx lr
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enable_sdrc:
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ldr r4, omap3_cm_iclken1_core
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ldr r5, [r4]
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orr r5, r5, #0x2 @ enable iclk bit for SDRC
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str r5, [r4]
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ldr r11, omap3_cm_iclken1_core
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ldr r12, [r11]
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orr r12, r12, #0x2 @ enable iclk bit for SDRC
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str r12, [r11]
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wait_sdrc_idle1:
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ldr r4, omap3_cm_idlest1_core
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ldr r5, [r4]
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and r5, r5, #0x2
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cmp r5, #0
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ldr r11, omap3_cm_idlest1_core
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ldr r12, [r11]
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and r12, r12, #0x2
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cmp r12, #0
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bne wait_sdrc_idle1
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restore_sdrc_power_val:
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ldr r4, omap3_sdrc_power
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str r9, [r4] @ restore SDRC_POWER, no barrier needed
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ldr r11, omap3_sdrc_power
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str r9, [r11] @ restore SDRC_POWER, no barrier needed
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bx lr
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wait_dll_lock:
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ldr r4, omap3_sdrc_dlla_status
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ldr r5, [r4]
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and r5, r5, #0x4
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cmp r5, #0x4
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ldr r11, omap3_sdrc_dlla_status
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ldr r12, [r11]
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and r12, r12, #0x4
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cmp r12, #0x4
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bne wait_dll_lock
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bx lr
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wait_dll_unlock:
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ldr r4, omap3_sdrc_dlla_status
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ldr r5, [r4]
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and r5, r5, #0x4
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cmp r5, #0x0
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ldr r11, omap3_sdrc_dlla_status
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ldr r12, [r11]
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and r12, r12, #0x4
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cmp r12, #0x0
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bne wait_dll_unlock
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bx lr
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configure_sdrc:
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ldr r4, omap3_sdrc_rfr_ctrl
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str r0, [r4]
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ldr r4, omap3_sdrc_actim_ctrla
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str r1, [r4]
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ldr r4, omap3_sdrc_actim_ctrlb
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str r2, [r4]
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ldr r2, [r4] @ posted-write barrier for SDRC
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ldr r11, omap3_sdrc_rfr_ctrl
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str r0, [r11]
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ldr r11, omap3_sdrc_actim_ctrla
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str r1, [r11]
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ldr r11, omap3_sdrc_actim_ctrlb
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str r2, [r11]
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ldr r2, [r11] @ posted-write barrier for SDRC
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bx lr
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omap3_sdrc_power:
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