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drm/i915: Make i915_spin_request() static
No users now outside of i915_wait_request(), so we can make it private to i915_gem_request.c, and assume the caller knows the seqno. In the process, also remove i915_gem_request_started() as that was only ever used by i915_spin_request(). Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk> Cc: Michal Winiarski <michal.winiarski@intel.com> Cc: Tvrtko Ursulin <tvrtko.ursulin@intel.com> Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20170922120333.25535-1-chris@chris-wilson.co.uk Reviewed-by: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
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7fd0b1a259
commit
b2f2f0fc69
2 changed files with 21 additions and 41 deletions
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@ -1021,12 +1021,28 @@ static bool busywait_stop(unsigned long timeout, unsigned int cpu)
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return this_cpu != cpu;
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}
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bool __i915_spin_request(const struct drm_i915_gem_request *req,
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u32 seqno, int state, unsigned long timeout_us)
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static bool __i915_spin_request(const struct drm_i915_gem_request *req,
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u32 seqno, int state, unsigned long timeout_us)
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{
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struct intel_engine_cs *engine = req->engine;
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unsigned int irq, cpu;
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GEM_BUG_ON(!seqno);
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/*
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* Only wait for the request if we know it is likely to complete.
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*
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* We don't track the timestamps around requests, nor the average
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* request length, so we do not have a good indicator that this
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* request will complete within the timeout. What we do know is the
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* order in which requests are executed by the engine and so we can
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* tell if the request has started. If the request hasn't started yet,
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* it is a fair assumption that it will not complete within our
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* relatively short timeout.
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*/
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if (!i915_seqno_passed(intel_engine_get_seqno(engine), seqno - 1))
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return false;
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/* When waiting for high frequency requests, e.g. during synchronous
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* rendering split between the CPU and GPU, the finite amount of time
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* required to set up the irq and wait upon it limits the response
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@ -1040,8 +1056,7 @@ bool __i915_spin_request(const struct drm_i915_gem_request *req,
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irq = atomic_read(&engine->irq_count);
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timeout_us += local_clock_us(&cpu);
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do {
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if (i915_seqno_passed(intel_engine_get_seqno(req->engine),
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seqno))
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if (i915_seqno_passed(intel_engine_get_seqno(engine), seqno))
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return seqno == i915_gem_request_global_seqno(req);
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/* Seqno are meant to be ordered *before* the interrupt. If
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@ -1153,7 +1168,7 @@ long i915_wait_request(struct drm_i915_gem_request *req,
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GEM_BUG_ON(!i915_sw_fence_signaled(&req->submit));
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/* Optimistic short spin before touching IRQs */
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if (i915_spin_request(req, state, 5))
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if (__i915_spin_request(req, wait.seqno, state, 5))
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goto complete;
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set_current_state(state);
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@ -1210,7 +1225,7 @@ long i915_wait_request(struct drm_i915_gem_request *req,
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continue;
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/* Only spin if we know the GPU is processing this request */
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if (i915_spin_request(req, state, 2))
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if (__i915_spin_request(req, wait.seqno, state, 2))
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break;
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if (!intel_wait_check_request(&wait, req)) {
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@ -312,26 +312,6 @@ static inline bool i915_seqno_passed(u32 seq1, u32 seq2)
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return (s32)(seq1 - seq2) >= 0;
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}
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static inline bool
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__i915_gem_request_started(const struct drm_i915_gem_request *req, u32 seqno)
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{
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GEM_BUG_ON(!seqno);
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return i915_seqno_passed(intel_engine_get_seqno(req->engine),
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seqno - 1);
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}
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static inline bool
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i915_gem_request_started(const struct drm_i915_gem_request *req)
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{
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u32 seqno;
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seqno = i915_gem_request_global_seqno(req);
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if (!seqno)
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return false;
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return __i915_gem_request_started(req, seqno);
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}
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static inline bool
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__i915_gem_request_completed(const struct drm_i915_gem_request *req, u32 seqno)
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{
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@ -352,21 +332,6 @@ i915_gem_request_completed(const struct drm_i915_gem_request *req)
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return __i915_gem_request_completed(req, seqno);
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}
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bool __i915_spin_request(const struct drm_i915_gem_request *request,
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u32 seqno, int state, unsigned long timeout_us);
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static inline bool i915_spin_request(const struct drm_i915_gem_request *request,
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int state, unsigned long timeout_us)
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{
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u32 seqno;
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seqno = i915_gem_request_global_seqno(request);
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if (!seqno)
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return 0;
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return (__i915_gem_request_started(request, seqno) &&
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__i915_spin_request(request, seqno, state, timeout_us));
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}
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/* We treat requests as fences. This is not be to confused with our
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* "fence registers" but pipeline synchronisation objects ala GL_ARB_sync.
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* We use the fences to synchronize access from the CPU with activity on the
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