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ARM: dts: imx6qdl: Fix CODA960 interrupt order
Commit a04a0b6fed
("ARM: dts: imx6qdl: Enable CODA960 VPU") lost the
fix for the CODA960 interrupt order during a rebase before being applied.
This patch adds the missing bit and brings the interrupts and
interrupt-names properties back in sync.
Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de>
Reviewed-by: Fabio Estevam <fabio.estevam@freescale.com>
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
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parent
4fe6be0fe0
commit
b2faf1a1af
1 changed files with 2 additions and 2 deletions
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@ -335,8 +335,8 @@ spba@0203c000 {
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vpu: vpu@02040000 {
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compatible = "cnm,coda960";
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reg = <0x02040000 0x3c000>;
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interrupts = <0 3 IRQ_TYPE_LEVEL_HIGH>,
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<0 12 IRQ_TYPE_LEVEL_HIGH>;
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interrupts = <0 12 IRQ_TYPE_LEVEL_HIGH>,
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<0 3 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-names = "bit", "jpeg";
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clocks = <&clks IMX6QDL_CLK_VPU_AXI>,
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<&clks IMX6QDL_CLK_MMDC_CH0_AXI>,
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