mirror of
https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git
synced 2024-09-05 02:19:51 +00:00
MIPS: MIPSsim: Remove the MIPSsim platform.
The MIPSsim platform is no longer supported or used. [ralf@linux-mips.org: Also remove mipssim from arch/mips/Kbuild.platforms and delete arch/mips/include/asm/mach-mipssim/*.] Signed-off-by: Steven J. Hill <sjhill@mips.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/4350/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
This commit is contained in:
parent
b1c561845d
commit
b30fdd6f73
15 changed files with 0 additions and 845 deletions
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@ -15,7 +15,6 @@ platforms += lantiq
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platforms += lasat
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platforms += loongson
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platforms += loongson1
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platforms += mipssim
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platforms += mti-malta
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platforms += netlogic
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platforms += pmc-sierra
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@ -319,25 +319,6 @@ config MIPS_MALTA
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This enables support for the MIPS Technologies Malta evaluation
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board.
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config MIPS_SIM
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bool 'MIPS simulator (MIPSsim)'
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select CEVT_R4K
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select CSRC_R4K
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select DMA_NONCOHERENT
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select SYS_HAS_EARLY_PRINTK
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select IRQ_CPU
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select BOOT_RAW
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select SYS_HAS_CPU_MIPS32_R1
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select SYS_HAS_CPU_MIPS32_R2
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select SYS_HAS_EARLY_PRINTK
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select SYS_SUPPORTS_32BIT_KERNEL
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select SYS_SUPPORTS_BIG_ENDIAN
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select SYS_SUPPORTS_MULTITHREADING
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select SYS_SUPPORTS_LITTLE_ENDIAN
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help
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This option enables support for MIPS Technologies MIPSsim software
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emulator.
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config NEC_MARKEINS
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bool "NEC EMMA2RH Mark-eins board"
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select SOC_EMMA2RH
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@ -1,64 +0,0 @@
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CONFIG_MIPS_SIM=y
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CONFIG_CPU_LITTLE_ENDIAN=y
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CONFIG_HZ_100=y
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# CONFIG_SECCOMP is not set
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CONFIG_EXPERIMENTAL=y
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# CONFIG_SWAP is not set
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CONFIG_SYSVIPC=y
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CONFIG_LOG_BUF_SHIFT=14
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# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set
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CONFIG_EXPERT=y
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CONFIG_SLAB=y
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CONFIG_MODULES=y
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CONFIG_MODULE_UNLOAD=y
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CONFIG_MODVERSIONS=y
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CONFIG_MODULE_SRCVERSION_ALL=y
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# CONFIG_BLK_DEV_BSG is not set
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CONFIG_NET=y
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CONFIG_PACKET=y
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CONFIG_UNIX=y
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CONFIG_INET=y
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CONFIG_IP_MULTICAST=y
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CONFIG_IP_ADVANCED_ROUTER=y
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CONFIG_IP_PNP=y
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CONFIG_IP_PNP_DHCP=y
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CONFIG_IP_PNP_BOOTP=y
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# CONFIG_INET_XFRM_MODE_TRANSPORT is not set
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# CONFIG_INET_XFRM_MODE_TUNNEL is not set
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# CONFIG_INET_XFRM_MODE_BEET is not set
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# CONFIG_INET_LRO is not set
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# CONFIG_IPV6 is not set
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CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
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# CONFIG_STANDALONE is not set
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# CONFIG_PREVENT_FIRMWARE_BUILD is not set
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# CONFIG_FW_LOADER is not set
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CONFIG_BLK_DEV_LOOP=y
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CONFIG_BLK_DEV_NBD=y
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# CONFIG_MISC_DEVICES is not set
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CONFIG_NETDEVICES=y
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CONFIG_NET_ETHERNET=y
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CONFIG_MIPS_SIM_NET=y
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# CONFIG_NETDEV_1000 is not set
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# CONFIG_NETDEV_10000 is not set
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# CONFIG_INPUT is not set
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# CONFIG_SERIO is not set
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# CONFIG_VT is not set
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CONFIG_SERIAL_8250=y
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CONFIG_SERIAL_8250_CONSOLE=y
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CONFIG_SERIAL_8250_NR_UARTS=1
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CONFIG_SERIAL_8250_RUNTIME_UARTS=1
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# CONFIG_HW_RANDOM is not set
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# CONFIG_HWMON is not set
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# CONFIG_USB_SUPPORT is not set
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# CONFIG_DNOTIFY is not set
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CONFIG_TMPFS=y
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CONFIG_ROMFS_FS=y
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CONFIG_NFS_FS=y
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CONFIG_NFS_V3=y
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CONFIG_ROOT_NFS=y
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CONFIG_DEBUG_KERNEL=y
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# CONFIG_SCHED_DEBUG is not set
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CONFIG_DEBUG_INFO=y
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CONFIG_CMDLINE_BOOL=y
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CONFIG_CMDLINE="nfsroot=192.168.192.169:/u1/mipsel,timeo=20 ip=dhcp"
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# CONFIG_CRC32 is not set
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@ -1,67 +0,0 @@
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/*
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* This file is subject to the terms and conditions of the GNU General Public
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* License. See the file "COPYING" in the main directory of this archive
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* for more details.
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*
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* Copyright (C) 2003, 2004 Chris Dearman
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*/
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#ifndef __ASM_MACH_SIM_CPU_FEATURE_OVERRIDES_H
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#define __ASM_MACH_SIM_CPU_FEATURE_OVERRIDES_H
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/*
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* CPU feature overrides for MIPS boards
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*/
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#ifdef CONFIG_CPU_MIPS32
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#define cpu_has_tlb 1
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#define cpu_has_4kex 1
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#define cpu_has_4k_cache 1
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#define cpu_has_fpu 0
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/* #define cpu_has_32fpr ? */
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#define cpu_has_counter 1
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/* #define cpu_has_watch ? */
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#define cpu_has_divec 1
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#define cpu_has_vce 0
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/* #define cpu_has_cache_cdex_p ? */
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/* #define cpu_has_cache_cdex_s ? */
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/* #define cpu_has_prefetch ? */
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#define cpu_has_mcheck 1
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/* #define cpu_has_ejtag ? */
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#define cpu_has_llsc 1
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/* #define cpu_has_vtag_icache ? */
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/* #define cpu_has_dc_aliases ? */
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/* #define cpu_has_ic_fills_f_dc ? */
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#define cpu_has_clo_clz 1
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#define cpu_has_nofpuex 0
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/* #define cpu_has_64bits ? */
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/* #define cpu_has_64bit_zero_reg ? */
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/* #define cpu_has_inclusive_pcaches ? */
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#endif
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#ifdef CONFIG_CPU_MIPS64
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#define cpu_has_tlb 1
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#define cpu_has_4kex 1
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#define cpu_has_4k_cache 1
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/* #define cpu_has_fpu ? */
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/* #define cpu_has_32fpr ? */
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#define cpu_has_counter 1
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/* #define cpu_has_watch ? */
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#define cpu_has_divec 1
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#define cpu_has_vce 0
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/* #define cpu_has_cache_cdex_p ? */
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/* #define cpu_has_cache_cdex_s ? */
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/* #define cpu_has_prefetch ? */
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#define cpu_has_mcheck 1
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/* #define cpu_has_ejtag ? */
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#define cpu_has_llsc 1
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/* #define cpu_has_vtag_icache ? */
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/* #define cpu_has_dc_aliases ? */
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/* #define cpu_has_ic_fills_f_dc ? */
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#define cpu_has_clo_clz 1
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#define cpu_has_nofpuex 0
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/* #define cpu_has_64bits ? */
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/* #define cpu_has_64bit_zero_reg ? */
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/* #define cpu_has_inclusive_pcaches ? */
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#endif
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#endif /* __ASM_MACH_MIPS_CPU_FEATURE_OVERRIDES_H */
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@ -1,25 +0,0 @@
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/*
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* This file is subject to the terms and conditions of the GNU General Public
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* License. See the file "COPYING" in the main directory of this archive
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* for more details.
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*
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* Copyright (C) 2002, 2004, 2007 by Ralf Baechle <ralf@linux-mips.org>
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*/
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#ifndef __ASM_MIPS_MACH_MIPSSIM_WAR_H
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#define __ASM_MIPS_MACH_MIPSSIM_WAR_H
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#define R4600_V1_INDEX_ICACHEOP_WAR 0
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#define R4600_V1_HIT_CACHEOP_WAR 0
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#define R4600_V2_HIT_CACHEOP_WAR 0
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#define R5432_CP0_INTERRUPT_WAR 0
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#define BCM1250_M3_WAR 0
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#define SIBYTE_1956_WAR 0
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#define MIPS4K_ICACHE_REFILL_WAR 0
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#define MIPS_CACHE_SYNC_WAR 0
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#define TX49XX_ICACHE_INDEX_INV_WAR 0
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#define RM9000_CDEX_SMP_WAR 0
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#define ICACHE_REFILLS_WORKAROUND_WAR 0
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#define R10000_LLSC_WAR 0
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#define MIPS34K_MISSED_ITLB_WAR 0
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#endif /* __ASM_MIPS_MACH_MIPSSIM_WAR_H */
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@ -1,31 +0,0 @@
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/*
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* Copyright (C) 2005 MIPS Technologies, Inc. All rights reserved.
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*
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* This program is free software; you can distribute it and/or modify it
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* under the terms of the GNU General Public License (Version 2) as
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* published by the Free Software Foundation.
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*
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* This program is distributed in the hope it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
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* for more details.
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*
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* You should have received a copy of the GNU General Public License along
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* with this program; if not, write to the Free Software Foundation, Inc.,
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* 59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
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*/
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#ifndef _MIPS_SIMINT_H
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#define _MIPS_SIMINT_H
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#include <irq.h>
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#define SIM_INT_BASE 0
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#define MIPSCPU_INT_MB0 2
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#define MIPS_CPU_TIMER_IRQ 7
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#define MSC01E_INT_BASE 64
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#define MSC01E_INT_CPUCTR 11
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#endif
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@ -1,23 +0,0 @@
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#
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# Copyright (C) 2005 MIPS Technologies, Inc. All rights reserved.
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# Copyright (C) 2007 MIPS Technologies, Inc.
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# written by Ralf Baechle (ralf@linux-mips.org)
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#
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# This program is free software; you can distribute it and/or modify it
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# under the terms of the GNU General Public License (Version 2) as
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# published by the Free Software Foundation.
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#
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# This program is distributed in the hope it will be useful, but WITHOUT
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# ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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# FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
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# for more details.
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#
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# You should have received a copy of the GNU General Public License along
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# with this program; if not, write to the Free Software Foundation, Inc.,
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# 59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
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#
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obj-y := sim_platform.o sim_setup.o sim_mem.o sim_time.o sim_int.o
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obj-$(CONFIG_EARLY_PRINTK) += sim_console.o
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obj-$(CONFIG_MIPS_MT_SMTC) += sim_smtc.o
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@ -1,6 +0,0 @@
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#
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# MIPS SIM
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#
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platform-$(CONFIG_MIPS_SIM) += mipssim/
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cflags-$(CONFIG_MIPS_SIM) += -I$(srctree)/arch/mips/include/asm/mach-mipssim
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load-$(CONFIG_MIPS_SIM) += 0x80100000
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@ -1,40 +0,0 @@
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/*
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* This program is free software; you can distribute it and/or modify it
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* under the terms of the GNU General Public License (Version 2) as
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* published by the Free Software Foundation.
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*
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* This program is distributed in the hope it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
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* for more details.
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*
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* You should have received a copy of the GNU General Public License along
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* with this program; if not, write to the Free Software Foundation, Inc.,
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* 59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
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*
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* Carsten Langgaard, carstenl@mips.com
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* Copyright (C) 1999,2000 MIPS Technologies, Inc. All rights reserved.
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* Copyright (C) 2007 MIPS Technologies, Inc.
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* written by Ralf Baechle
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*/
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#include <linux/init.h>
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#include <linux/io.h>
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#include <linux/serial_reg.h>
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static inline unsigned int serial_in(int offset)
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{
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return inb(0x3f8 + offset);
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}
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static inline void serial_out(int offset, int value)
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{
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outb(value, 0x3f8 + offset);
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}
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void __init prom_putchar(char c)
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{
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while ((serial_in(UART_LSR) & UART_LSR_THRE) == 0)
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;
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serial_out(UART_TX, c);
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}
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@ -1,87 +0,0 @@
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/*
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* Copyright (C) 1999, 2005 MIPS Technologies, Inc. All rights reserved.
|
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*
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* This program is free software; you can distribute it and/or modify it
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* under the terms of the GNU General Public License (Version 2) as
|
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* published by the Free Software Foundation.
|
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*
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* This program is distributed in the hope it will be useful, but WITHOUT
|
||||
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
||||
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
|
||||
* for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License along
|
||||
* with this program; if not, write to the Free Software Foundation, Inc.,
|
||||
* 59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
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*
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*/
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#include <linux/init.h>
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#include <linux/sched.h>
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#include <linux/interrupt.h>
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#include <linux/kernel_stat.h>
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#include <asm/mips-boards/simint.h>
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#include <asm/irq_cpu.h>
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static inline int clz(unsigned long x)
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{
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__asm__(
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" .set push \n"
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" .set mips32 \n"
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" clz %0, %1 \n"
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" .set pop \n"
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: "=r" (x)
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: "r" (x));
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return x;
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}
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/*
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* Version of ffs that only looks at bits 12..15.
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*/
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static inline unsigned int irq_ffs(unsigned int pending)
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{
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#if defined(CONFIG_CPU_MIPS32) || defined(CONFIG_CPU_MIPS64)
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return -clz(pending) + 31 - CAUSEB_IP;
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#else
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unsigned int a0 = 7;
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unsigned int t0;
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t0 = s0 & 0xf000;
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t0 = t0 < 1;
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t0 = t0 << 2;
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a0 = a0 - t0;
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s0 = s0 << t0;
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t0 = s0 & 0xc000;
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t0 = t0 < 1;
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t0 = t0 << 1;
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a0 = a0 - t0;
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s0 = s0 << t0;
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|
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t0 = s0 & 0x8000;
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t0 = t0 < 1;
|
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/* t0 = t0 << 2; */
|
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a0 = a0 - t0;
|
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/* s0 = s0 << t0; */
|
||||
|
||||
return a0;
|
||||
#endif
|
||||
}
|
||||
|
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asmlinkage void plat_irq_dispatch(void)
|
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{
|
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unsigned int pending = read_c0_cause() & read_c0_status() & ST0_IM;
|
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int irq;
|
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|
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irq = irq_ffs(pending);
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||||
|
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if (irq > 0)
|
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do_IRQ(MIPS_CPU_IRQ_BASE + irq);
|
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else
|
||||
spurious_interrupt();
|
||||
}
|
||||
|
||||
void __init arch_init_irq(void)
|
||||
{
|
||||
mips_cpu_irq_init();
|
||||
}
|
|
@ -1,115 +0,0 @@
|
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/*
|
||||
* Copyright (C) 2005 MIPS Technologies, Inc. All rights reserved.
|
||||
*
|
||||
* This program is free software; you can distribute it and/or modify it
|
||||
* under the terms of the GNU General Public License (Version 2) as
|
||||
* published by the Free Software Foundation.
|
||||
*
|
||||
* This program is distributed in the hope it will be useful, but WITHOUT
|
||||
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
||||
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
|
||||
* for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License along
|
||||
* with this program; if not, write to the Free Software Foundation, Inc.,
|
||||
* 59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
|
||||
*
|
||||
*/
|
||||
#include <linux/init.h>
|
||||
#include <linux/mm.h>
|
||||
#include <linux/bootmem.h>
|
||||
#include <linux/pfn.h>
|
||||
|
||||
#include <asm/bootinfo.h>
|
||||
#include <asm/page.h>
|
||||
#include <asm/sections.h>
|
||||
|
||||
#include <asm/mips-boards/prom.h>
|
||||
|
||||
/*#define DEBUG*/
|
||||
|
||||
enum simmem_memtypes {
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simmem_reserved = 0,
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||||
simmem_free,
|
||||
};
|
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struct prom_pmemblock mdesc[PROM_MAX_PMEMBLOCKS];
|
||||
|
||||
#ifdef DEBUG
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static char *mtypes[3] = {
|
||||
"SIM reserved memory",
|
||||
"SIM free memory",
|
||||
};
|
||||
#endif
|
||||
|
||||
struct prom_pmemblock * __init prom_getmdesc(void)
|
||||
{
|
||||
unsigned int memsize;
|
||||
|
||||
memsize = 0x02000000;
|
||||
pr_info("Setting default memory size 0x%08x\n", memsize);
|
||||
|
||||
memset(mdesc, 0, sizeof(mdesc));
|
||||
|
||||
mdesc[0].type = simmem_reserved;
|
||||
mdesc[0].base = 0x00000000;
|
||||
mdesc[0].size = 0x00001000;
|
||||
|
||||
mdesc[1].type = simmem_free;
|
||||
mdesc[1].base = 0x00001000;
|
||||
mdesc[1].size = 0x000ff000;
|
||||
|
||||
mdesc[2].type = simmem_reserved;
|
||||
mdesc[2].base = 0x00100000;
|
||||
mdesc[2].size = CPHYSADDR(PFN_ALIGN(&_end)) - mdesc[2].base;
|
||||
|
||||
mdesc[3].type = simmem_free;
|
||||
mdesc[3].base = CPHYSADDR(PFN_ALIGN(&_end));
|
||||
mdesc[3].size = memsize - mdesc[3].base;
|
||||
|
||||
return &mdesc[0];
|
||||
}
|
||||
|
||||
static int __init prom_memtype_classify(unsigned int type)
|
||||
{
|
||||
switch (type) {
|
||||
case simmem_free:
|
||||
return BOOT_MEM_RAM;
|
||||
case simmem_reserved:
|
||||
default:
|
||||
return BOOT_MEM_RESERVED;
|
||||
}
|
||||
}
|
||||
|
||||
void __init prom_meminit(void)
|
||||
{
|
||||
struct prom_pmemblock *p;
|
||||
|
||||
p = prom_getmdesc();
|
||||
|
||||
while (p->size) {
|
||||
long type;
|
||||
unsigned long base, size;
|
||||
|
||||
type = prom_memtype_classify(p->type);
|
||||
base = p->base;
|
||||
size = p->size;
|
||||
|
||||
add_memory_region(base, size, type);
|
||||
p++;
|
||||
}
|
||||
}
|
||||
|
||||
void __init prom_free_prom_memory(void)
|
||||
{
|
||||
int i;
|
||||
unsigned long addr;
|
||||
|
||||
for (i = 0; i < boot_mem_map.nr_map; i++) {
|
||||
if (boot_mem_map.map[i].type != BOOT_MEM_ROM_DATA)
|
||||
continue;
|
||||
|
||||
addr = boot_mem_map.map[i].addr;
|
||||
free_init_pages("prom memory",
|
||||
addr, addr + boot_mem_map.map[i].size);
|
||||
}
|
||||
}
|
|
@ -1,35 +0,0 @@
|
|||
/*
|
||||
* This file is subject to the terms and conditions of the GNU General Public
|
||||
* License. See the file "COPYING" in the main directory of this archive
|
||||
* for more details.
|
||||
*
|
||||
* Copyright (C) 2007 by Ralf Baechle (ralf@linux-mips.org)
|
||||
*/
|
||||
#include <linux/init.h>
|
||||
#include <linux/if_ether.h>
|
||||
#include <linux/kernel.h>
|
||||
#include <linux/platform_device.h>
|
||||
|
||||
static char mipsnet_string[] = "mipsnet";
|
||||
|
||||
static struct platform_device eth1_device = {
|
||||
.name = mipsnet_string,
|
||||
.id = 0,
|
||||
};
|
||||
|
||||
/*
|
||||
* Create a platform device for the GPI port that receives the
|
||||
* image data from the embedded camera.
|
||||
*/
|
||||
static int __init mipsnet_devinit(void)
|
||||
{
|
||||
int err;
|
||||
|
||||
err = platform_device_register(ð1_device);
|
||||
if (err)
|
||||
printk(KERN_ERR "%s: registration failed\n", mipsnet_string);
|
||||
|
||||
return err;
|
||||
}
|
||||
|
||||
device_initcall(mipsnet_devinit);
|
|
@ -1,99 +0,0 @@
|
|||
/*
|
||||
* Copyright (C) 2005 MIPS Technologies, Inc. All rights reserved.
|
||||
*
|
||||
* This program is free software; you can distribute it and/or modify it
|
||||
* under the terms of the GNU General Public License (Version 2) as
|
||||
* published by the Free Software Foundation.
|
||||
*
|
||||
* This program is distributed in the hope it will be useful, but WITHOUT
|
||||
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
||||
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
|
||||
* for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License along
|
||||
* with this program; if not, write to the Free Software Foundation, Inc.,
|
||||
* 59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
|
||||
*
|
||||
*/
|
||||
|
||||
#include <linux/init.h>
|
||||
#include <linux/string.h>
|
||||
#include <linux/kernel.h>
|
||||
#include <linux/io.h>
|
||||
#include <linux/irq.h>
|
||||
#include <linux/ioport.h>
|
||||
#include <linux/tty.h>
|
||||
#include <linux/serial.h>
|
||||
#include <linux/serial_core.h>
|
||||
#include <linux/serial_8250.h>
|
||||
|
||||
#include <asm/cpu.h>
|
||||
#include <asm/bootinfo.h>
|
||||
#include <asm/mips-boards/generic.h>
|
||||
#include <asm/mips-boards/prom.h>
|
||||
#include <asm/time.h>
|
||||
#include <asm/mips-boards/sim.h>
|
||||
#include <asm/mips-boards/simint.h>
|
||||
#include <asm/smp-ops.h>
|
||||
|
||||
|
||||
static void __init serial_init(void);
|
||||
unsigned int _isbonito;
|
||||
|
||||
const char *get_system_type(void)
|
||||
{
|
||||
return "MIPSsim";
|
||||
}
|
||||
|
||||
void __init plat_mem_setup(void)
|
||||
{
|
||||
set_io_port_base(0xbfd00000);
|
||||
|
||||
serial_init();
|
||||
}
|
||||
|
||||
extern struct plat_smp_ops ssmtc_smp_ops;
|
||||
|
||||
void __init prom_init(void)
|
||||
{
|
||||
set_io_port_base(0xbfd00000);
|
||||
|
||||
prom_meminit();
|
||||
|
||||
if (cpu_has_mipsmt) {
|
||||
if (!register_vsmp_smp_ops())
|
||||
return;
|
||||
|
||||
#ifdef CONFIG_MIPS_MT_SMTC
|
||||
register_smp_ops(&ssmtc_smp_ops);
|
||||
return;
|
||||
#endif
|
||||
}
|
||||
|
||||
register_up_smp_ops();
|
||||
}
|
||||
|
||||
static void __init serial_init(void)
|
||||
{
|
||||
#ifdef CONFIG_SERIAL_8250
|
||||
struct uart_port s;
|
||||
|
||||
memset(&s, 0, sizeof(s));
|
||||
|
||||
s.iobase = 0x3f8;
|
||||
|
||||
/* hardware int 4 - the serial int, is CPU int 6
|
||||
but poll for now */
|
||||
s.irq = 0;
|
||||
s.uartclk = 1843200;
|
||||
s.flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST;
|
||||
s.iotype = UPIO_PORT;
|
||||
s.regshift = 0;
|
||||
s.timeout = 4;
|
||||
|
||||
if (early_serial_setup(&s) != 0) {
|
||||
printk(KERN_ERR "Serial setup failed!\n");
|
||||
}
|
||||
|
||||
#endif
|
||||
}
|
|
@ -1,116 +0,0 @@
|
|||
/*
|
||||
* Copyright (C) 2005 MIPS Technologies, Inc. All rights reserved.
|
||||
*
|
||||
* This program is free software; you can distribute it and/or modify it
|
||||
* under the terms of the GNU General Public License (Version 2) as
|
||||
* published by the Free Software Foundation.
|
||||
*
|
||||
* This program is distributed in the hope it will be useful, but WITHOUT
|
||||
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
||||
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
|
||||
* for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License along
|
||||
* with this program; if not, write to the Free Software Foundation, Inc.,
|
||||
* 59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
|
||||
*
|
||||
*/
|
||||
/*
|
||||
* Simulator Platform-specific hooks for SMTC operation
|
||||
*/
|
||||
#include <linux/kernel.h>
|
||||
#include <linux/sched.h>
|
||||
#include <linux/cpumask.h>
|
||||
#include <linux/interrupt.h>
|
||||
#include <linux/smp.h>
|
||||
|
||||
#include <linux/atomic.h>
|
||||
#include <asm/cpu.h>
|
||||
#include <asm/processor.h>
|
||||
#include <asm/smtc.h>
|
||||
#include <asm/mmu_context.h>
|
||||
#include <asm/smtc_ipi.h>
|
||||
|
||||
/* VPE/SMP Prototype implements platform interfaces directly */
|
||||
|
||||
/*
|
||||
* Cause the specified action to be performed on a targeted "CPU"
|
||||
*/
|
||||
|
||||
static void ssmtc_send_ipi_single(int cpu, unsigned int action)
|
||||
{
|
||||
smtc_send_ipi(cpu, LINUX_SMP_IPI, action);
|
||||
/* "CPU" may be TC of same VPE, VPE of same CPU, or different CPU */
|
||||
}
|
||||
|
||||
static inline void ssmtc_send_ipi_mask(const struct cpumask *mask,
|
||||
unsigned int action)
|
||||
{
|
||||
unsigned int i;
|
||||
|
||||
for_each_cpu(i, mask)
|
||||
ssmtc_send_ipi_single(i, action);
|
||||
}
|
||||
|
||||
/*
|
||||
* Post-config but pre-boot cleanup entry point
|
||||
*/
|
||||
static void __cpuinit ssmtc_init_secondary(void)
|
||||
{
|
||||
smtc_init_secondary();
|
||||
}
|
||||
|
||||
/*
|
||||
* SMP initialization finalization entry point
|
||||
*/
|
||||
static void __cpuinit ssmtc_smp_finish(void)
|
||||
{
|
||||
smtc_smp_finish();
|
||||
}
|
||||
|
||||
/*
|
||||
* Hook for after all CPUs are online
|
||||
*/
|
||||
static void ssmtc_cpus_done(void)
|
||||
{
|
||||
}
|
||||
|
||||
/*
|
||||
* Platform "CPU" startup hook
|
||||
*/
|
||||
static void __cpuinit ssmtc_boot_secondary(int cpu, struct task_struct *idle)
|
||||
{
|
||||
smtc_boot_secondary(cpu, idle);
|
||||
}
|
||||
|
||||
static void __init ssmtc_smp_setup(void)
|
||||
{
|
||||
if (read_c0_config3() & (1 << 2))
|
||||
mipsmt_build_cpu_map(0);
|
||||
}
|
||||
|
||||
/*
|
||||
* Platform SMP pre-initialization
|
||||
*/
|
||||
static void ssmtc_prepare_cpus(unsigned int max_cpus)
|
||||
{
|
||||
/*
|
||||
* As noted above, we can assume a single CPU for now
|
||||
* but it may be multithreaded.
|
||||
*/
|
||||
|
||||
if (read_c0_config3() & (1 << 2)) {
|
||||
mipsmt_prepare_cpus();
|
||||
}
|
||||
}
|
||||
|
||||
struct plat_smp_ops ssmtc_smp_ops = {
|
||||
.send_ipi_single = ssmtc_send_ipi_single,
|
||||
.send_ipi_mask = ssmtc_send_ipi_mask,
|
||||
.init_secondary = ssmtc_init_secondary,
|
||||
.smp_finish = ssmtc_smp_finish,
|
||||
.cpus_done = ssmtc_cpus_done,
|
||||
.boot_secondary = ssmtc_boot_secondary,
|
||||
.smp_setup = ssmtc_smp_setup,
|
||||
.prepare_cpus = ssmtc_prepare_cpus,
|
||||
};
|
|
@ -1,117 +0,0 @@
|
|||
#include <linux/types.h>
|
||||
#include <linux/init.h>
|
||||
#include <linux/kernel_stat.h>
|
||||
#include <linux/sched.h>
|
||||
#include <linux/spinlock.h>
|
||||
#include <linux/interrupt.h>
|
||||
#include <linux/mc146818rtc.h>
|
||||
#include <linux/smp.h>
|
||||
#include <linux/timex.h>
|
||||
|
||||
#include <asm/hardirq.h>
|
||||
#include <asm/div64.h>
|
||||
#include <asm/cpu.h>
|
||||
#include <asm/setup.h>
|
||||
#include <asm/time.h>
|
||||
#include <asm/irq.h>
|
||||
#include <asm/mc146818-time.h>
|
||||
#include <asm/msc01_ic.h>
|
||||
|
||||
#include <asm/mips-boards/generic.h>
|
||||
#include <asm/mips-boards/prom.h>
|
||||
#include <asm/mips-boards/simint.h>
|
||||
|
||||
|
||||
unsigned long cpu_khz;
|
||||
|
||||
/*
|
||||
* Estimate CPU frequency. Sets mips_hpt_frequency as a side-effect
|
||||
*/
|
||||
static unsigned int __init estimate_cpu_frequency(void)
|
||||
{
|
||||
unsigned int prid = read_c0_prid() & 0xffff00;
|
||||
unsigned int count;
|
||||
|
||||
#if 1
|
||||
/*
|
||||
* hardwire the board frequency to 12MHz.
|
||||
*/
|
||||
|
||||
if ((prid == (PRID_COMP_MIPS | PRID_IMP_20KC)) ||
|
||||
(prid == (PRID_COMP_MIPS | PRID_IMP_25KF)))
|
||||
count = 12000000;
|
||||
else
|
||||
count = 6000000;
|
||||
#else
|
||||
unsigned int flags;
|
||||
|
||||
local_irq_save(flags);
|
||||
|
||||
/* Start counter exactly on falling edge of update flag */
|
||||
while (CMOS_READ(RTC_REG_A) & RTC_UIP);
|
||||
while (!(CMOS_READ(RTC_REG_A) & RTC_UIP));
|
||||
|
||||
/* Start r4k counter. */
|
||||
write_c0_count(0);
|
||||
|
||||
/* Read counter exactly on falling edge of update flag */
|
||||
while (CMOS_READ(RTC_REG_A) & RTC_UIP);
|
||||
while (!(CMOS_READ(RTC_REG_A) & RTC_UIP));
|
||||
|
||||
count = read_c0_count();
|
||||
|
||||
/* restore interrupts */
|
||||
local_irq_restore(flags);
|
||||
#endif
|
||||
|
||||
mips_hpt_frequency = count;
|
||||
|
||||
if ((prid != (PRID_COMP_MIPS | PRID_IMP_20KC)) &&
|
||||
(prid != (PRID_COMP_MIPS | PRID_IMP_25KF)))
|
||||
count *= 2;
|
||||
|
||||
count += 5000; /* round */
|
||||
count -= count%10000;
|
||||
|
||||
return count;
|
||||
}
|
||||
|
||||
static int mips_cpu_timer_irq;
|
||||
|
||||
static void mips_timer_dispatch(void)
|
||||
{
|
||||
do_IRQ(mips_cpu_timer_irq);
|
||||
}
|
||||
|
||||
|
||||
unsigned __cpuinit get_c0_compare_int(void)
|
||||
{
|
||||
#ifdef MSC01E_INT_BASE
|
||||
if (cpu_has_veic) {
|
||||
set_vi_handler(MSC01E_INT_CPUCTR, mips_timer_dispatch);
|
||||
mips_cpu_timer_irq = MSC01E_INT_BASE + MSC01E_INT_CPUCTR;
|
||||
|
||||
return mips_cpu_timer_irq;
|
||||
}
|
||||
#endif
|
||||
if (cpu_has_vint)
|
||||
set_vi_handler(cp0_compare_irq, mips_timer_dispatch);
|
||||
mips_cpu_timer_irq = MIPS_CPU_IRQ_BASE + cp0_compare_irq;
|
||||
|
||||
return mips_cpu_timer_irq;
|
||||
}
|
||||
|
||||
void __init plat_time_init(void)
|
||||
{
|
||||
unsigned int est_freq;
|
||||
|
||||
/* Set Data mode - binary. */
|
||||
CMOS_WRITE(CMOS_READ(RTC_CONTROL) | RTC_DM_BINARY, RTC_CONTROL);
|
||||
|
||||
est_freq = estimate_cpu_frequency();
|
||||
|
||||
printk(KERN_INFO "CPU frequency %d.%02d MHz\n", est_freq / 1000000,
|
||||
(est_freq % 1000000) * 100 / 1000000);
|
||||
|
||||
cpu_khz = est_freq / 1000;
|
||||
}
|
Loading…
Reference in a new issue