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clk: tegra: Changes for v4.5-rc1
This set of changes adds support for the Tegra210 SoC and contains a couple fixes and cleanups. -----BEGIN PGP SIGNATURE----- Version: GnuPG v2 iQIcBAABCAAGBQJWcq0qAAoJEN0jrNd/PrOhxXIP/Rs/Iw27BVfk/ZYA+9SaYlNz vxqzGqWincnlaArLuhAnUHciAv5kl3HnHEuOyAgFevX/KrnmAb5JMXuw2FaSmzPc hjI5QqeieEHqp0wFSms/+abTiLX5t36bsY91QM8LfsdDOotrYGwEJcqDVEZkvMF2 j3U4RuXEqt/C0r436lPcxf+flvy70K1cQkywsKupcS4YGl0QiQVeY80tHmIIyrkA 2KLkxH5zgs/6xlcGblqzkFmrQntp5XJVgdlg1e2SZ5MOOme9fQCU0F3VueOX+WZH FL4C05eaXCaga398Z/UgJru1X8HWUKzrGBX6XXktxeTjt8ruKD8PEjX7SVPYMRI9 Kzb3NE5qC0LEwe/BAX/4scZ6fZFyk+zfiC566YA3rcM1sg5mm4k8PCH3x2ktxXI1 SZYmIrm+9hXXWfvXlKysaIsmGL0hlsRlu6m6g2OEYTUABDMBLnMsTbeC6Li4Gh0Q kXISNZpMhRaiB1hba3z2J/sVuMQcR33e86IaAX7WFY4ZRTNKfD0oB2zN5lZjPO6o U9ATB5ApPWn3t0JR88jaApPVELVb5q6ufra2zPesnS25CfS+zSXbskgnZe9UkPAs XVUprlmsNm+vZbZJpf3eNtW2IS0c0vCAYkafY3KjWcKVKvgKw5Zu8Kdo1TAJTHbP +xfWr3/iiwN5NNsYZbiH =/f1y -----END PGP SIGNATURE----- Merge tag 'tegra-for-4.5-clk' of git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux into clk-next clk: tegra: Changes for v4.5-rc1 This set of changes adds support for the Tegra210 SoC and contains a couple fixes and cleanups.
This commit is contained in:
Michael Turquette
commit
b360ada3f1
13 changed files with 5439 additions and 930 deletions
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@ -0,0 +1,56 @@
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NVIDIA Tegra210 Clock And Reset Controller
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This binding uses the common clock binding:
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Documentation/devicetree/bindings/clock/clock-bindings.txt
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The CAR (Clock And Reset) Controller on Tegra is the HW module responsible
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for muxing and gating Tegra's clocks, and setting their rates.
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Required properties :
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- compatible : Should be "nvidia,tegra210-car"
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- reg : Should contain CAR registers location and length
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- clocks : Should contain phandle and clock specifiers for two clocks:
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the 32 KHz "32k_in".
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- #clock-cells : Should be 1.
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In clock consumers, this cell represents the clock ID exposed by the
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CAR. The assignments may be found in header file
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<dt-bindings/clock/tegra210-car.h>.
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- #reset-cells : Should be 1.
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In clock consumers, this cell represents the bit number in the CAR's
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array of CLK_RST_CONTROLLER_RST_DEVICES_* registers.
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Example SoC include file:
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/ {
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tegra_car: clock {
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compatible = "nvidia,tegra210-car";
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reg = <0x60006000 0x1000>;
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#clock-cells = <1>;
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#reset-cells = <1>;
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};
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usb@c5004000 {
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clocks = <&tegra_car TEGRA210_CLK_USB2>;
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};
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};
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Example board file:
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/ {
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clocks {
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compatible = "simple-bus";
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#address-cells = <1>;
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#size-cells = <0>;
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clk_32k: clock@1 {
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compatible = "fixed-clock";
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reg = <1>;
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#clock-cells = <0>;
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clock-frequency = <32768>;
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};
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};
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&tegra_car {
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clocks = <&clk_32k>;
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};
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};
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@ -20,3 +20,4 @@ obj-$(CONFIG_ARCH_TEGRA_124_SOC) += clk-tegra124.o
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obj-$(CONFIG_ARCH_TEGRA_124_SOC) += clk-tegra124-dfll-fcpu.o
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obj-$(CONFIG_ARCH_TEGRA_132_SOC) += clk-tegra124.o
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obj-y += cvb.o
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obj-$(CONFIG_ARCH_TEGRA_210_SOC) += clk-tegra210.o
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@ -13,6 +13,7 @@ enum clk_id {
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tegra_clk_amx1,
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tegra_clk_apbdma,
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tegra_clk_apbif,
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tegra_clk_ape,
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tegra_clk_audio0,
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tegra_clk_audio0_2x,
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tegra_clk_audio0_mux,
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@ -38,6 +39,7 @@ enum clk_id {
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tegra_clk_cile,
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tegra_clk_clk_32k,
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tegra_clk_clk72Mhz,
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tegra_clk_clk72Mhz_8,
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tegra_clk_clk_m,
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tegra_clk_clk_m_div2,
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tegra_clk_clk_m_div4,
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@ -51,17 +53,21 @@ enum clk_id {
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tegra_clk_cml1,
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tegra_clk_csi,
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tegra_clk_csite,
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tegra_clk_csite_8,
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tegra_clk_csus,
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tegra_clk_cve,
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tegra_clk_dam0,
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tegra_clk_dam1,
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tegra_clk_dam2,
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tegra_clk_d_audio,
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tegra_clk_dbgapb,
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tegra_clk_dds,
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tegra_clk_dfll_ref,
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tegra_clk_dfll_soc,
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tegra_clk_disp1,
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tegra_clk_disp1_8,
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tegra_clk_disp2,
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tegra_clk_disp2_8,
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tegra_clk_dp2,
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tegra_clk_dpaux,
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tegra_clk_dsialp,
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@ -71,6 +77,7 @@ enum clk_id {
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tegra_clk_dtv,
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tegra_clk_emc,
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tegra_clk_entropy,
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tegra_clk_entropy_8,
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tegra_clk_epp,
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tegra_clk_epp_8,
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tegra_clk_extern1,
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@ -85,12 +92,16 @@ enum clk_id {
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tegra_clk_gr3d_8,
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tegra_clk_hclk,
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tegra_clk_hda,
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tegra_clk_hda_8,
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tegra_clk_hda2codec_2x,
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tegra_clk_hda2codec_2x_8,
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tegra_clk_hda2hdmi,
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tegra_clk_hdmi,
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tegra_clk_hdmi_audio,
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tegra_clk_host1x,
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tegra_clk_host1x_8,
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tegra_clk_host1x_9,
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tegra_clk_hsic_trk,
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tegra_clk_i2c1,
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tegra_clk_i2c2,
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tegra_clk_i2c3,
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@ -110,11 +121,14 @@ enum clk_id {
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tegra_clk_i2s4_sync,
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tegra_clk_isp,
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tegra_clk_isp_8,
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tegra_clk_isp_9,
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tegra_clk_ispb,
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tegra_clk_kbc,
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tegra_clk_kfuse,
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tegra_clk_la,
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tegra_clk_maud,
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tegra_clk_mipi,
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tegra_clk_mipibif,
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tegra_clk_mipi_cal,
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tegra_clk_mpe,
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tegra_clk_mselect,
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@ -124,15 +138,24 @@ enum clk_id {
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tegra_clk_ndspeed,
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tegra_clk_ndspeed_8,
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tegra_clk_nor,
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tegra_clk_nvdec,
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tegra_clk_nvenc,
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tegra_clk_nvjpg,
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tegra_clk_owr,
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tegra_clk_owr_8,
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tegra_clk_pcie,
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tegra_clk_pclk,
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tegra_clk_pll_a,
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tegra_clk_pll_a_out0,
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tegra_clk_pll_a1,
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tegra_clk_pll_c,
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tegra_clk_pll_c2,
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tegra_clk_pll_c3,
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tegra_clk_pll_c4,
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tegra_clk_pll_c4_out0,
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tegra_clk_pll_c4_out1,
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tegra_clk_pll_c4_out2,
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tegra_clk_pll_c4_out3,
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tegra_clk_pll_c_out1,
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tegra_clk_pll_d,
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tegra_clk_pll_d2,
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@ -140,19 +163,29 @@ enum clk_id {
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tegra_clk_pll_d_out0,
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tegra_clk_pll_dp,
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tegra_clk_pll_e_out0,
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tegra_clk_pll_g_ref,
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tegra_clk_pll_m,
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tegra_clk_pll_m_out1,
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tegra_clk_pll_mb,
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tegra_clk_pll_p,
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tegra_clk_pll_p_out1,
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tegra_clk_pll_p_out2,
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tegra_clk_pll_p_out2_int,
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tegra_clk_pll_p_out3,
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tegra_clk_pll_p_out4,
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tegra_clk_pll_p_out4_cpu,
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tegra_clk_pll_p_out5,
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tegra_clk_pll_p_out_hsio,
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tegra_clk_pll_p_out_xusb,
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tegra_clk_pll_p_out_cpu,
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tegra_clk_pll_p_out_adsp,
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tegra_clk_pll_ref,
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tegra_clk_pll_re_out,
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tegra_clk_pll_re_vco,
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tegra_clk_pll_u,
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tegra_clk_pll_u_out,
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tegra_clk_pll_u_out1,
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tegra_clk_pll_u_out2,
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tegra_clk_pll_u_12m,
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tegra_clk_pll_u_480m,
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tegra_clk_pll_u_48m,
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@ -160,53 +193,80 @@ enum clk_id {
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tegra_clk_pll_x,
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tegra_clk_pll_x_out0,
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tegra_clk_pwm,
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tegra_clk_qspi,
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tegra_clk_rtc,
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tegra_clk_sata,
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tegra_clk_sata_8,
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tegra_clk_sata_cold,
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tegra_clk_sata_oob,
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tegra_clk_sata_oob_8,
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tegra_clk_sbc1,
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tegra_clk_sbc1_8,
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tegra_clk_sbc1_9,
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tegra_clk_sbc2,
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tegra_clk_sbc2_8,
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tegra_clk_sbc2_9,
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tegra_clk_sbc3,
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tegra_clk_sbc3_8,
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tegra_clk_sbc3_9,
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tegra_clk_sbc4,
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tegra_clk_sbc4_8,
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tegra_clk_sbc4_9,
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tegra_clk_sbc5,
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tegra_clk_sbc5_8,
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tegra_clk_sbc6,
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tegra_clk_sbc6_8,
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tegra_clk_sclk,
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tegra_clk_sdmmc_legacy,
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tegra_clk_sdmmc1,
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tegra_clk_sdmmc1_8,
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tegra_clk_sdmmc1_9,
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tegra_clk_sdmmc2,
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tegra_clk_sdmmc2_8,
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tegra_clk_sdmmc2_9,
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tegra_clk_sdmmc3,
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tegra_clk_sdmmc3_8,
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tegra_clk_sdmmc3_9,
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tegra_clk_sdmmc4,
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tegra_clk_sdmmc4_8,
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tegra_clk_sdmmc4_9,
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tegra_clk_se,
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tegra_clk_soc_therm,
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tegra_clk_soc_therm_8,
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tegra_clk_sor0,
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tegra_clk_sor0_lvds,
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tegra_clk_sor1,
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tegra_clk_sor1_brick,
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tegra_clk_sor1_src,
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tegra_clk_spdif,
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tegra_clk_spdif_2x,
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tegra_clk_spdif_in,
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tegra_clk_spdif_in_8,
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tegra_clk_spdif_in_sync,
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tegra_clk_spdif_mux,
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tegra_clk_spdif_out,
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tegra_clk_timer,
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tegra_clk_trace,
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tegra_clk_tsec,
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tegra_clk_tsec_8,
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tegra_clk_tsecb,
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tegra_clk_tsensor,
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tegra_clk_tvdac,
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tegra_clk_tvo,
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tegra_clk_uarta,
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tegra_clk_uarta_8,
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tegra_clk_uartb,
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tegra_clk_uartb_8,
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tegra_clk_uartc,
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tegra_clk_uartc_8,
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tegra_clk_uartd,
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tegra_clk_uartd_8,
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tegra_clk_uarte,
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tegra_clk_uarte_8,
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tegra_clk_uartape,
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tegra_clk_usb2,
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tegra_clk_usb2_hsic_trk,
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tegra_clk_usb2_trk,
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tegra_clk_usb3,
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tegra_clk_usbd,
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tegra_clk_vcp,
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@ -216,22 +276,35 @@ enum clk_id {
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tegra_clk_vi,
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tegra_clk_vi_8,
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tegra_clk_vi_9,
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tegra_clk_vi_10,
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tegra_clk_vi_i2c,
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tegra_clk_vic03,
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tegra_clk_vic03_8,
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tegra_clk_vim2_clk,
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tegra_clk_vimclk_sync,
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tegra_clk_vi_sensor,
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tegra_clk_vi_sensor2,
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tegra_clk_vi_sensor_8,
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tegra_clk_vi_sensor_9,
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tegra_clk_vi_sensor2,
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tegra_clk_vi_sensor2_8,
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tegra_clk_xusb_dev,
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tegra_clk_xusb_dev_src,
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tegra_clk_xusb_dev_src_8,
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tegra_clk_xusb_falcon_src,
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tegra_clk_xusb_falcon_src_8,
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tegra_clk_xusb_fs_src,
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tegra_clk_xusb_gate,
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tegra_clk_xusb_host,
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tegra_clk_xusb_host_src,
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tegra_clk_xusb_host_src_8,
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tegra_clk_xusb_hs_src,
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tegra_clk_xusb_hs_src_4,
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tegra_clk_xusb_ss,
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tegra_clk_xusb_ss_src,
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tegra_clk_xusb_ss_src_8,
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tegra_clk_xusb_ss_div2,
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tegra_clk_xusb_ssp_src,
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tegra_clk_sclk_mux,
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tegra_clk_max,
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};
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File diff suppressed because it is too large
Load diff
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@ -124,6 +124,20 @@
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#define CLK_SOURCE_HDMI_AUDIO 0x668
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#define CLK_SOURCE_VIC03 0x678
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#define CLK_SOURCE_CLK72MHZ 0x66c
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#define CLK_SOURCE_DBGAPB 0x718
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#define CLK_SOURCE_NVENC 0x6a0
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#define CLK_SOURCE_NVDEC 0x698
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#define CLK_SOURCE_NVJPG 0x69c
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#define CLK_SOURCE_APE 0x6c0
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#define CLK_SOURCE_SOR1 0x410
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#define CLK_SOURCE_SDMMC_LEGACY 0x694
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#define CLK_SOURCE_QSPI 0x6c4
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#define CLK_SOURCE_VI_I2C 0x6c8
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#define CLK_SOURCE_MIPIBIF 0x660
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#define CLK_SOURCE_UARTAPE 0x710
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#define CLK_SOURCE_TSECB 0x6d8
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#define CLK_SOURCE_MAUD 0x6d4
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#define CLK_SOURCE_USB2_HSIC_TRK 0x6cc
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#define MASK(x) (BIT(x) - 1)
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@ -182,6 +196,13 @@
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TEGRA_DIVIDER_ROUND_UP, _clk_num, 0, _clk_id,\
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_parents##_idx, 0, NULL)
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#define UART8(_name, _parents, _offset,\
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_clk_num, _clk_id) \
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TEGRA_INIT_DATA_TABLE(_name, NULL, NULL, _parents, _offset,\
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29, MASK(3), 0, 0, 16, 1, TEGRA_DIVIDER_UART| \
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TEGRA_DIVIDER_ROUND_UP, _clk_num, 0, _clk_id,\
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_parents##_idx, 0, NULL)
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#define I2C(_name, _parents, _offset,\
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_clk_num, _clk_id) \
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TEGRA_INIT_DATA_TABLE(_name, NULL, NULL, _parents, _offset,\
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@ -221,8 +242,21 @@
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.flags = _flags \
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}
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#define DIV8(_name, _parent_name, _offset, _clk_id, _flags) \
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{ \
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.name = _name, \
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.clk_id = _clk_id, \
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.p.parent_name = _parent_name, \
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.periph = TEGRA_CLK_PERIPH(0, 0, 0, 0, 8, 1, \
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TEGRA_DIVIDER_ROUND_UP, 0, 0, \
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NULL, NULL), \
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.offset = _offset, \
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.flags = _flags, \
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}
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#define PLLP_BASE 0xa0
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#define PLLP_MISC 0xac
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#define PLLP_MISC1 0x680
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#define PLLP_OUTA 0xa4
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#define PLLP_OUTB 0xa8
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#define PLLP_OUTC 0x67c
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|
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@ -234,6 +268,7 @@ static DEFINE_SPINLOCK(PLLP_OUTA_lock);
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static DEFINE_SPINLOCK(PLLP_OUTB_lock);
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static DEFINE_SPINLOCK(PLLP_OUTC_lock);
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static DEFINE_SPINLOCK(sor0_lock);
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static DEFINE_SPINLOCK(sor1_lock);
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#define MUX_I2S_SPDIF(_id) \
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static const char *mux_pllaout0_##_id##_2x_pllp_clkm[] = { "pll_a_out0", \
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|
|
@ -285,6 +320,68 @@ static u32 mux_pllp_clkm_idx[] = {
|
|||
[0] = 0, [1] = 3,
|
||||
};
|
||||
|
||||
static const char *mux_pllp_clkm_2[] = {
|
||||
"pll_p", "clk_m"
|
||||
};
|
||||
static u32 mux_pllp_clkm_2_idx[] = {
|
||||
[0] = 2, [1] = 6,
|
||||
};
|
||||
|
||||
static const char *mux_pllc2_c_c3_pllp_plla1_clkm[] = {
|
||||
"pll_c2", "pll_c", "pll_c3", "pll_p", "pll_a1", "clk_m"
|
||||
};
|
||||
static u32 mux_pllc2_c_c3_pllp_plla1_clkm_idx[] = {
|
||||
[0] = 1, [1] = 2, [2] = 3, [3] = 4, [4] = 6, [5] = 7,
|
||||
};
|
||||
|
||||
static const char *
|
||||
mux_pllc4_out1_pllc_pllc4_out2_pllp_clkm_plla_pllc4_out0[] = {
|
||||
"pll_c4_out1", "pll_c", "pll_c4_out2", "pll_p", "clk_m",
|
||||
"pll_a_out0", "pll_c4_out0"
|
||||
};
|
||||
static u32 mux_pllc4_out1_pllc_pllc4_out2_pllp_clkm_plla_pllc4_out0_idx[] = {
|
||||
[0] = 0, [1] = 2, [2] = 3, [3] = 4, [4] = 5, [5] = 6, [6] = 7,
|
||||
};
|
||||
|
||||
static const char *mux_pllc_pllp_plla[] = {
|
||||
"pll_c", "pll_p", "pll_a_out0"
|
||||
};
|
||||
static u32 mux_pllc_pllp_plla_idx[] = {
|
||||
[0] = 1, [1] = 2, [2] = 3,
|
||||
};
|
||||
|
||||
static const char *mux_clkm_pllc_pllp_plla[] = {
|
||||
"clk_m", "pll_c", "pll_p", "pll_a_out0"
|
||||
};
|
||||
#define mux_clkm_pllc_pllp_plla_idx NULL
|
||||
|
||||
static const char *mux_pllc_pllp_plla1_pllc2_c3_clkm[] = {
|
||||
"pll_c", "pll_p", "pll_a1", "pll_c2", "pll_c3", "clk_m"
|
||||
};
|
||||
static u32 mux_pllc_pllp_plla1_pllc2_c3_clkm_idx[] = {
|
||||
[0] = 1, [1] = 2, [2] = 3, [3] = 4, [4] = 5, [5] = 6,
|
||||
};
|
||||
|
||||
static const char *mux_pllc2_c_c3_pllp_clkm_plla1_pllc4[] = {
|
||||
"pll_c2", "pll_c", "pll_c3", "pll_p", "clk_m", "pll_a1", "pll_c4_out0",
|
||||
};
|
||||
static u32 mux_pllc2_c_c3_pllp_clkm_plla1_pllc4_idx[] = {
|
||||
[0] = 1, [1] = 2, [2] = 3, [3] = 4, [4] = 5, [5] = 6, [6] = 7,
|
||||
};
|
||||
|
||||
static const char *mux_pllc_pllp_plla1_pllc2_c3_clkm_pllc4[] = {
|
||||
"pll_c", "pll_p", "pll_a1", "pll_c2", "pll_c3", "clk_m", "pll_c4_out0",
|
||||
};
|
||||
#define mux_pllc_pllp_plla1_pllc2_c3_clkm_pllc4_idx \
|
||||
mux_pllc2_c_c3_pllp_clkm_plla1_pllc4_idx
|
||||
|
||||
static const char *
|
||||
mux_plla_pllc4_out0_pllc_pllc4_out1_pllp_pllc4_out2_clkm[] = {
|
||||
"pll_a_out0", "pll_c4_out0", "pll_c", "pll_c4_out1", "pll_p",
|
||||
"pll_c4_out2", "clk_m"
|
||||
};
|
||||
#define mux_plla_pllc4_out0_pllc_pllc4_out1_pllp_pllc4_out2_clkm_idx NULL
|
||||
|
||||
static const char *mux_pllm_pllc2_c_c3_pllp_plla[] = {
|
||||
"pll_m", "pll_c2", "pll_c", "pll_c3", "pll_p", "pll_a_out0"
|
||||
};
|
||||
|
|
@ -302,12 +399,93 @@ static const char *mux_pllm_pllc_pllp_plla[] = {
|
|||
#define mux_pllm_pllc_pllp_plla_idx mux_pllp_pllc_pllm_clkm_idx
|
||||
|
||||
static const char *mux_pllp_pllc_clkm[] = {
|
||||
"pll_p", "pll_c", "pll_m"
|
||||
"pll_p", "pll_c", "clk_m"
|
||||
};
|
||||
static u32 mux_pllp_pllc_clkm_idx[] = {
|
||||
[0] = 0, [1] = 1, [2] = 3,
|
||||
};
|
||||
|
||||
static const char *mux_pllp_pllc_clkm_1[] = {
|
||||
"pll_p", "pll_c", "clk_m"
|
||||
};
|
||||
static u32 mux_pllp_pllc_clkm_1_idx[] = {
|
||||
[0] = 0, [1] = 2, [2] = 5,
|
||||
};
|
||||
|
||||
static const char *mux_pllp_pllc_plla_clkm[] = {
|
||||
"pll_p", "pll_c", "pll_a_out0", "clk_m"
|
||||
};
|
||||
static u32 mux_pllp_pllc_plla_clkm_idx[] = {
|
||||
[0] = 0, [1] = 2, [2] = 4, [3] = 6,
|
||||
};
|
||||
|
||||
static const char *mux_pllp_pllc_pllc4_out0_pllc4_out1_clkm_pllc4_out2[] = {
|
||||
"pll_p", "pll_c", "pll_c4_out0", "pll_c4_out1", "clk_m", "pll_c4_out2"
|
||||
};
|
||||
static u32 mux_pllp_pllc_pllc4_out0_pllc4_out1_clkm_pllc4_out2_idx[] = {
|
||||
[0] = 0, [1] = 2, [2] = 3, [3] = 5, [4] = 6, [5] = 7,
|
||||
};
|
||||
|
||||
static const char *
|
||||
mux_pllp_pllc_pllc_out1_pllc4_out2_pllc4_out1_clkm_pllc4_out0[] = {
|
||||
"pll_p", "pll_c_out1", "pll_c", "pll_c4_out2", "pll_c4_out1",
|
||||
"clk_m", "pll_c4_out0"
|
||||
};
|
||||
static u32
|
||||
mux_pllp_pllc_pllc_out1_pllc4_out2_pllc4_out1_clkm_pllc4_out0_idx[] = {
|
||||
[0] = 0, [1] = 1, [2] = 2, [3] = 4, [4] = 5, [5] = 6, [6] = 7,
|
||||
};
|
||||
|
||||
static const char *mux_pllp_pllc4_out2_pllc4_out1_clkm_pllc4_out0[] = {
|
||||
"pll_p", "pll_c4_out2", "pll_c4_out1", "clk_m", "pll_c4_out0"
|
||||
};
|
||||
static u32 mux_pllp_pllc4_out2_pllc4_out1_clkm_pllc4_out0_idx[] = {
|
||||
[0] = 0, [1] = 3, [2] = 4, [3] = 6, [4] = 7,
|
||||
};
|
||||
|
||||
static const char *mux_pllp_clkm_pllc4_out2_out1_out0_lj[] = {
|
||||
"pll_p",
|
||||
"pll_c4_out2", "pll_c4_out0", /* LJ input */
|
||||
"pll_c4_out2", "pll_c4_out1",
|
||||
"pll_c4_out1", /* LJ input */
|
||||
"clk_m", "pll_c4_out0"
|
||||
};
|
||||
#define mux_pllp_clkm_pllc4_out2_out1_out0_lj_idx NULL
|
||||
|
||||
static const char *mux_pllp_pllc2_c_c3_clkm[] = {
|
||||
"pll_p", "pll_c2", "pll_c", "pll_c3", "clk_m"
|
||||
};
|
||||
static u32 mux_pllp_pllc2_c_c3_clkm_idx[] = {
|
||||
[0] = 0, [1] = 1, [2] = 2, [3] = 3, [4] = 6,
|
||||
};
|
||||
|
||||
static const char *mux_pllp_clkm_clk32_plle[] = {
|
||||
"pll_p", "clk_m", "clk_32k", "pll_e"
|
||||
};
|
||||
static u32 mux_pllp_clkm_clk32_plle_idx[] = {
|
||||
[0] = 0, [1] = 2, [2] = 4, [3] = 6,
|
||||
};
|
||||
|
||||
static const char *mux_pllp_pllp_out3_clkm_clk32k_plla[] = {
|
||||
"pll_p", "pll_p_out3", "clk_m", "clk_32k", "pll_a_out0"
|
||||
};
|
||||
#define mux_pllp_pllp_out3_clkm_clk32k_plla_idx NULL
|
||||
|
||||
static const char *mux_pllp_out3_clkm_pllp_pllc4[] = {
|
||||
"pll_p_out3", "clk_m", "pll_p", "pll_c4_out0", "pll_c4_out1",
|
||||
"pll_c4_out2"
|
||||
};
|
||||
static u32 mux_pllp_out3_clkm_pllp_pllc4_idx[] = {
|
||||
[0] = 0, [1] = 3, [2] = 4, [3] = 5, [4] = 6, [5] = 7,
|
||||
};
|
||||
|
||||
static const char *mux_clkm_pllp_pllre[] = {
|
||||
"clk_m", "pll_p_out_xusb", "pll_re_out"
|
||||
};
|
||||
static u32 mux_clkm_pllp_pllre_idx[] = {
|
||||
[0] = 0, [1] = 1, [2] = 5,
|
||||
};
|
||||
|
||||
static const char *mux_pllp_pllc_clkm_clk32[] = {
|
||||
"pll_p", "pll_c", "clk_m", "clk_32k"
|
||||
};
|
||||
|
|
@ -332,6 +510,11 @@ static u32 mux_clkm_48M_pllp_480M_idx[] = {
|
|||
[0] = 0, [1] = 2, [2] = 4, [3] = 6,
|
||||
};
|
||||
|
||||
static const char *mux_clkm_pllre_clk32_480M[] = {
|
||||
"clk_m", "pll_re_out", "clk_32k", "pll_u_480M"
|
||||
};
|
||||
#define mux_clkm_pllre_clk32_480M_idx NULL
|
||||
|
||||
static const char *mux_clkm_pllre_clk32_480M_pllc_ref[] = {
|
||||
"clk_m", "pll_re_out", "clk_32k", "pll_u_480M", "pll_c", "pll_ref"
|
||||
};
|
||||
|
|
@ -339,10 +522,27 @@ static u32 mux_clkm_pllre_clk32_480M_pllc_ref_idx[] = {
|
|||
[0] = 0, [1] = 1, [2] = 3, [3] = 3, [4] = 4, [5] = 7,
|
||||
};
|
||||
|
||||
static const char *mux_ss_60M[] = {
|
||||
static const char *mux_pllp_out3_pllp_pllc_clkm[] = {
|
||||
"pll_p_out3", "pll_p", "pll_c", "clk_m"
|
||||
};
|
||||
static u32 mux_pllp_out3_pllp_pllc_clkm_idx[] = {
|
||||
[0] = 0, [1] = 1, [2] = 2, [3] = 6,
|
||||
};
|
||||
|
||||
static const char *mux_ss_div2_60M[] = {
|
||||
"xusb_ss_div2", "pll_u_60M"
|
||||
};
|
||||
#define mux_ss_60M_idx NULL
|
||||
#define mux_ss_div2_60M_idx NULL
|
||||
|
||||
static const char *mux_ss_div2_60M_ss[] = {
|
||||
"xusb_ss_div2", "pll_u_60M", "xusb_ss_src"
|
||||
};
|
||||
#define mux_ss_div2_60M_ss_idx NULL
|
||||
|
||||
static const char *mux_ss_clkm[] = {
|
||||
"xusb_ss_src", "clk_m"
|
||||
};
|
||||
#define mux_ss_clkm_idx NULL
|
||||
|
||||
static const char *mux_d_audio_clk[] = {
|
||||
"pll_a_out0", "pll_p", "clk_m", "spdif_in_sync", "i2s0_sync",
|
||||
|
|
@ -386,6 +586,32 @@ static u32 mux_pllm_pllc2_c_c3_pllp_plla_pllc4_idx[] = {
|
|||
[0] = 0, [1] = 1, [2] = 2, [3] = 3, [4] = 4, [5] = 6, [6] = 7,
|
||||
};
|
||||
|
||||
/* SOR1 mux'es */
|
||||
static const char *mux_pllp_plld_plld2_clkm[] = {
|
||||
"pll_p", "pll_d_out0", "pll_d2_out0", "clk_m"
|
||||
};
|
||||
static u32 mux_pllp_plld_plld2_clkm_idx[] = {
|
||||
[0] = 0, [1] = 2, [2] = 5, [3] = 6
|
||||
};
|
||||
|
||||
static const char *mux_plldp_sor1_src[] = {
|
||||
"pll_dp", "clk_sor1_src"
|
||||
};
|
||||
#define mux_plldp_sor1_src_idx NULL
|
||||
|
||||
static const char *mux_clkm_sor1_brick_sor1_src[] = {
|
||||
"clk_m", "sor1_brick", "sor1_src", "sor1_brick"
|
||||
};
|
||||
#define mux_clkm_sor1_brick_sor1_src_idx NULL
|
||||
|
||||
static const char *mux_pllp_pllre_clkm[] = {
|
||||
"pll_p", "pll_re_out1", "clk_m"
|
||||
};
|
||||
|
||||
static u32 mux_pllp_pllre_clkm_idx[] = {
|
||||
[0] = 0, [1] = 2, [2] = 3,
|
||||
};
|
||||
|
||||
static const char *mux_clkm_plldp_sor0lvds[] = {
|
||||
"clk_m", "pll_dp", "sor0_lvds",
|
||||
};
|
||||
|
|
@ -401,6 +627,7 @@ static struct tegra_periph_init_data periph_clks[] = {
|
|||
I2C("i2c3", mux_pllp_clkm, CLK_SOURCE_I2C3, 67, tegra_clk_i2c3),
|
||||
I2C("i2c4", mux_pllp_clkm, CLK_SOURCE_I2C4, 103, tegra_clk_i2c4),
|
||||
I2C("i2c5", mux_pllp_clkm, CLK_SOURCE_I2C5, 47, tegra_clk_i2c5),
|
||||
I2C("i2c6", mux_pllp_clkm, CLK_SOURCE_I2C6, 166, tegra_clk_i2c6),
|
||||
INT("vde", mux_pllp_pllc_pllm_clkm, CLK_SOURCE_VDE, 61, 0, tegra_clk_vde),
|
||||
INT("vi", mux_pllm_pllc_pllp_plla, CLK_SOURCE_VI, 20, 0, tegra_clk_vi),
|
||||
INT("epp", mux_pllm_pllc_pllp_plla, CLK_SOURCE_EPP, 19, 0, tegra_clk_epp),
|
||||
|
|
@ -411,14 +638,19 @@ static struct tegra_periph_init_data periph_clks[] = {
|
|||
INT8("vde", mux_pllp_pllc2_c_c3_pllm_clkm, CLK_SOURCE_VDE, 61, 0, tegra_clk_vde_8),
|
||||
INT8("vi", mux_pllm_pllc2_c_c3_pllp_plla, CLK_SOURCE_VI, 20, 0, tegra_clk_vi_8),
|
||||
INT8("vi", mux_pllm_pllc2_c_c3_pllp_plla_pllc4, CLK_SOURCE_VI, 20, 0, tegra_clk_vi_9),
|
||||
INT8("vi", mux_pllc2_c_c3_pllp_clkm_plla1_pllc4, CLK_SOURCE_VI, 20, 0, tegra_clk_vi_10),
|
||||
INT8("epp", mux_pllm_pllc2_c_c3_pllp_plla, CLK_SOURCE_EPP, 19, 0, tegra_clk_epp_8),
|
||||
INT8("msenc", mux_pllm_pllc2_c_c3_pllp_plla, CLK_SOURCE_MSENC, 91, TEGRA_PERIPH_WAR_1005168, tegra_clk_msenc),
|
||||
INT8("tsec", mux_pllp_pllc2_c_c3_pllm_clkm, CLK_SOURCE_TSEC, 83, 0, tegra_clk_tsec),
|
||||
INT("tsec", mux_pllp_pllc_clkm, CLK_SOURCE_TSEC, 83, 0, tegra_clk_tsec_8),
|
||||
INT8("host1x", mux_pllm_pllc2_c_c3_pllp_plla, CLK_SOURCE_HOST1X, 28, 0, tegra_clk_host1x_8),
|
||||
INT8("host1x", mux_pllc4_out1_pllc_pllc4_out2_pllp_clkm_plla_pllc4_out0, CLK_SOURCE_HOST1X, 28, 0, tegra_clk_host1x_9),
|
||||
INT8("se", mux_pllp_pllc2_c_c3_pllm_clkm, CLK_SOURCE_SE, 127, TEGRA_PERIPH_ON_APB, tegra_clk_se),
|
||||
INT8("se", mux_pllp_pllc2_c_c3_clkm, CLK_SOURCE_SE, 127, TEGRA_PERIPH_ON_APB, tegra_clk_se),
|
||||
INT8("2d", mux_pllm_pllc2_c_c3_pllp_plla, CLK_SOURCE_2D, 21, 0, tegra_clk_gr2d_8),
|
||||
INT8("3d", mux_pllm_pllc2_c_c3_pllp_plla, CLK_SOURCE_3D, 24, 0, tegra_clk_gr3d_8),
|
||||
INT8("vic03", mux_pllm_pllc_pllp_plla_pllc2_c3_clkm, CLK_SOURCE_VIC03, 178, 0, tegra_clk_vic03),
|
||||
INT8("vic03", mux_pllc_pllp_plla1_pllc2_c3_clkm, CLK_SOURCE_VIC03, 178, 0, tegra_clk_vic03_8),
|
||||
INT_FLAGS("mselect", mux_pllp_clkm, CLK_SOURCE_MSELECT, 99, 0, tegra_clk_mselect, CLK_IGNORE_UNUSED),
|
||||
MUX("i2s0", mux_pllaout0_audio0_2x_pllp_clkm, CLK_SOURCE_I2S0, 30, TEGRA_PERIPH_ON_APB, tegra_clk_i2s0),
|
||||
MUX("i2s1", mux_pllaout0_audio1_2x_pllp_clkm, CLK_SOURCE_I2S1, 11, TEGRA_PERIPH_ON_APB, tegra_clk_i2s1),
|
||||
|
|
@ -427,22 +659,31 @@ static struct tegra_periph_init_data periph_clks[] = {
|
|||
MUX("i2s4", mux_pllaout0_audio4_2x_pllp_clkm, CLK_SOURCE_I2S4, 102, TEGRA_PERIPH_ON_APB, tegra_clk_i2s4),
|
||||
MUX("spdif_out", mux_pllaout0_audio_2x_pllp_clkm, CLK_SOURCE_SPDIF_OUT, 10, TEGRA_PERIPH_ON_APB, tegra_clk_spdif_out),
|
||||
MUX("spdif_in", mux_pllp_pllc_pllm, CLK_SOURCE_SPDIF_IN, 10, TEGRA_PERIPH_ON_APB, tegra_clk_spdif_in),
|
||||
MUX8("spdif_in", mux_pllp_pllc_clkm_1, CLK_SOURCE_SPDIF_IN, 10, TEGRA_PERIPH_ON_APB, tegra_clk_spdif_in_8),
|
||||
MUX("pwm", mux_pllp_pllc_clk32_clkm, CLK_SOURCE_PWM, 17, TEGRA_PERIPH_ON_APB, tegra_clk_pwm),
|
||||
MUX("adx", mux_plla_pllc_pllp_clkm, CLK_SOURCE_ADX, 154, TEGRA_PERIPH_ON_APB, tegra_clk_adx),
|
||||
MUX("amx", mux_plla_pllc_pllp_clkm, CLK_SOURCE_AMX, 153, TEGRA_PERIPH_ON_APB, tegra_clk_amx),
|
||||
MUX("hda", mux_pllp_pllc_pllm_clkm, CLK_SOURCE_HDA, 125, TEGRA_PERIPH_ON_APB, tegra_clk_hda),
|
||||
MUX("hda", mux_pllp_pllc_clkm, CLK_SOURCE_HDA, 125, TEGRA_PERIPH_ON_APB, tegra_clk_hda_8),
|
||||
MUX("hda2codec_2x", mux_pllp_pllc_pllm_clkm, CLK_SOURCE_HDA2CODEC_2X, 111, TEGRA_PERIPH_ON_APB, tegra_clk_hda2codec_2x),
|
||||
MUX8("hda2codec_2x", mux_pllp_pllc_plla_clkm, CLK_SOURCE_HDA2CODEC_2X, 111, TEGRA_PERIPH_ON_APB, tegra_clk_hda2codec_2x_8),
|
||||
MUX("vfir", mux_pllp_pllc_pllm_clkm, CLK_SOURCE_VFIR, 7, TEGRA_PERIPH_ON_APB, tegra_clk_vfir),
|
||||
MUX("sdmmc1", mux_pllp_pllc_pllm_clkm, CLK_SOURCE_SDMMC1, 14, TEGRA_PERIPH_ON_APB, tegra_clk_sdmmc1),
|
||||
MUX("sdmmc2", mux_pllp_pllc_pllm_clkm, CLK_SOURCE_SDMMC2, 9, TEGRA_PERIPH_ON_APB, tegra_clk_sdmmc2),
|
||||
MUX("sdmmc3", mux_pllp_pllc_pllm_clkm, CLK_SOURCE_SDMMC3, 69, TEGRA_PERIPH_ON_APB, tegra_clk_sdmmc3),
|
||||
MUX("sdmmc4", mux_pllp_pllc_pllm_clkm, CLK_SOURCE_SDMMC4, 15, TEGRA_PERIPH_ON_APB, tegra_clk_sdmmc4),
|
||||
MUX8("sdmmc1", mux_pllp_pllc4_out2_pllc4_out1_clkm_pllc4_out0, CLK_SOURCE_SDMMC1, 14, TEGRA_PERIPH_ON_APB, tegra_clk_sdmmc1_9),
|
||||
MUX8("sdmmc2", mux_pllp_clkm_pllc4_out2_out1_out0_lj, CLK_SOURCE_SDMMC2, 9, TEGRA_PERIPH_ON_APB, tegra_clk_sdmmc2_9),
|
||||
MUX8("sdmmc3", mux_pllp_pllc4_out2_pllc4_out1_clkm_pllc4_out0, CLK_SOURCE_SDMMC3, 69, TEGRA_PERIPH_ON_APB, tegra_clk_sdmmc3_9),
|
||||
MUX8("sdmmc4", mux_pllp_clkm_pllc4_out2_out1_out0_lj, CLK_SOURCE_SDMMC4, 15, TEGRA_PERIPH_ON_APB, tegra_clk_sdmmc4_9),
|
||||
MUX("la", mux_pllp_pllc_pllm_clkm, CLK_SOURCE_LA, 76, TEGRA_PERIPH_ON_APB, tegra_clk_la),
|
||||
MUX("trace", mux_pllp_pllc_pllm_clkm, CLK_SOURCE_TRACE, 77, TEGRA_PERIPH_ON_APB, tegra_clk_trace),
|
||||
MUX("owr", mux_pllp_pllc_pllm_clkm, CLK_SOURCE_OWR, 71, TEGRA_PERIPH_ON_APB, tegra_clk_owr),
|
||||
MUX("owr", mux_pllp_pllc_clkm, CLK_SOURCE_OWR, 71, TEGRA_PERIPH_ON_APB, tegra_clk_owr_8),
|
||||
MUX("nor", mux_pllp_pllc_pllm_clkm, CLK_SOURCE_NOR, 42, 0, tegra_clk_nor),
|
||||
MUX("mipi", mux_pllp_pllc_pllm_clkm, CLK_SOURCE_MIPI, 50, TEGRA_PERIPH_ON_APB, tegra_clk_mipi),
|
||||
MUX("vi_sensor", mux_pllm_pllc_pllp_plla, CLK_SOURCE_VI_SENSOR, 20, TEGRA_PERIPH_NO_RESET, tegra_clk_vi_sensor),
|
||||
MUX("vi_sensor", mux_pllc_pllp_plla, CLK_SOURCE_VI_SENSOR, 20, TEGRA_PERIPH_NO_RESET, tegra_clk_vi_sensor_9),
|
||||
MUX("cilab", mux_pllp_pllc_clkm, CLK_SOURCE_CILAB, 144, 0, tegra_clk_cilab),
|
||||
MUX("cilcd", mux_pllp_pllc_clkm, CLK_SOURCE_CILCD, 145, 0, tegra_clk_cilcd),
|
||||
MUX("cile", mux_pllp_pllc_clkm, CLK_SOURCE_CILE, 146, 0, tegra_clk_cile),
|
||||
|
|
@ -465,10 +706,13 @@ static struct tegra_periph_init_data periph_clks[] = {
|
|||
MUX("ndflash", mux_pllp_pllc_pllm_clkm, CLK_SOURCE_NDFLASH, 13, TEGRA_PERIPH_ON_APB, tegra_clk_ndflash),
|
||||
MUX("ndspeed", mux_pllp_pllc_pllm_clkm, CLK_SOURCE_NDSPEED, 80, TEGRA_PERIPH_ON_APB, tegra_clk_ndspeed),
|
||||
MUX("sata_oob", mux_pllp_pllc_pllm_clkm, CLK_SOURCE_SATA_OOB, 123, TEGRA_PERIPH_ON_APB, tegra_clk_sata_oob),
|
||||
MUX("sata_oob", mux_pllp_pllc_clkm, CLK_SOURCE_SATA_OOB, 123, TEGRA_PERIPH_ON_APB, tegra_clk_sata_oob_8),
|
||||
MUX("sata", mux_pllp_pllc_pllm_clkm, CLK_SOURCE_SATA, 124, TEGRA_PERIPH_ON_APB, tegra_clk_sata),
|
||||
MUX("sata", mux_pllp_pllc_clkm, CLK_SOURCE_SATA, 124, TEGRA_PERIPH_ON_APB, tegra_clk_sata_8),
|
||||
MUX("adx1", mux_plla_pllc_pllp_clkm, CLK_SOURCE_ADX1, 180, TEGRA_PERIPH_ON_APB, tegra_clk_adx1),
|
||||
MUX("amx1", mux_plla_pllc_pllp_clkm, CLK_SOURCE_AMX1, 185, TEGRA_PERIPH_ON_APB, tegra_clk_amx1),
|
||||
MUX("vi_sensor2", mux_pllm_pllc2_c_c3_pllp_plla, CLK_SOURCE_VI_SENSOR2, 165, TEGRA_PERIPH_NO_RESET, tegra_clk_vi_sensor2),
|
||||
MUX("vi_sensor2", mux_pllc_pllp_plla, CLK_SOURCE_VI_SENSOR2, 165, TEGRA_PERIPH_NO_RESET, tegra_clk_vi_sensor2_8),
|
||||
MUX8("sdmmc1", mux_pllp_pllc2_c_c3_pllm_clkm, CLK_SOURCE_SDMMC1, 14, TEGRA_PERIPH_ON_APB, tegra_clk_sdmmc1_8),
|
||||
MUX8("sdmmc2", mux_pllp_pllc2_c_c3_pllm_clkm, CLK_SOURCE_SDMMC2, 9, TEGRA_PERIPH_ON_APB, tegra_clk_sdmmc2_8),
|
||||
MUX8("sdmmc3", mux_pllp_pllc2_c_c3_pllm_clkm, CLK_SOURCE_SDMMC3, 69, TEGRA_PERIPH_ON_APB, tegra_clk_sdmmc3_8),
|
||||
|
|
@ -479,6 +723,10 @@ static struct tegra_periph_init_data periph_clks[] = {
|
|||
MUX8("sbc4", mux_pllp_pllc2_c_c3_pllm_clkm, CLK_SOURCE_SBC4, 68, TEGRA_PERIPH_ON_APB, tegra_clk_sbc4_8),
|
||||
MUX8("sbc5", mux_pllp_pllc2_c_c3_pllm_clkm, CLK_SOURCE_SBC5, 104, TEGRA_PERIPH_ON_APB, tegra_clk_sbc5_8),
|
||||
MUX8("sbc6", mux_pllp_pllc2_c_c3_pllm_clkm, CLK_SOURCE_SBC6, 105, TEGRA_PERIPH_ON_APB, tegra_clk_sbc6_8),
|
||||
MUX("sbc1", mux_pllp_pllc_clkm, CLK_SOURCE_SBC1, 41, TEGRA_PERIPH_ON_APB, tegra_clk_sbc1_9),
|
||||
MUX("sbc2", mux_pllp_pllc_clkm, CLK_SOURCE_SBC2, 44, TEGRA_PERIPH_ON_APB, tegra_clk_sbc2_9),
|
||||
MUX("sbc3", mux_pllp_pllc_clkm, CLK_SOURCE_SBC3, 46, TEGRA_PERIPH_ON_APB, tegra_clk_sbc3_9),
|
||||
MUX("sbc4", mux_pllp_pllc_clkm, CLK_SOURCE_SBC4, 68, TEGRA_PERIPH_ON_APB, tegra_clk_sbc4_9),
|
||||
MUX8("ndflash", mux_pllp_pllc2_c_c3_pllm_clkm, CLK_SOURCE_NDFLASH, 13, TEGRA_PERIPH_ON_APB, tegra_clk_ndflash_8),
|
||||
MUX8("ndspeed", mux_pllp_pllc2_c_c3_pllm_clkm, CLK_SOURCE_NDSPEED, 80, TEGRA_PERIPH_ON_APB, tegra_clk_ndspeed_8),
|
||||
MUX8("hdmi", mux_pllp_pllm_plld_plla_pllc_plld2_clkm, CLK_SOURCE_HDMI, 51, 0, tegra_clk_hdmi),
|
||||
|
|
@ -486,27 +734,59 @@ static struct tegra_periph_init_data periph_clks[] = {
|
|||
MUX8("extern2", mux_plla_clk32_pllp_clkm_plle, CLK_SOURCE_EXTERN2, 121, 0, tegra_clk_extern2),
|
||||
MUX8("extern3", mux_plla_clk32_pllp_clkm_plle, CLK_SOURCE_EXTERN3, 122, 0, tegra_clk_extern3),
|
||||
MUX8("soc_therm", mux_pllm_pllc_pllp_plla, CLK_SOURCE_SOC_THERM, 78, TEGRA_PERIPH_ON_APB, tegra_clk_soc_therm),
|
||||
MUX8("soc_therm", mux_clkm_pllc_pllp_plla, CLK_SOURCE_SOC_THERM, 78, TEGRA_PERIPH_ON_APB, tegra_clk_soc_therm_8),
|
||||
MUX8("vi_sensor", mux_pllm_pllc2_c_c3_pllp_plla, CLK_SOURCE_VI_SENSOR, 164, TEGRA_PERIPH_NO_RESET, tegra_clk_vi_sensor_8),
|
||||
MUX8("isp", mux_pllm_pllc_pllp_plla_clkm_pllc4, CLK_SOURCE_ISP, 23, TEGRA_PERIPH_ON_APB, tegra_clk_isp_8),
|
||||
MUX8("isp", mux_pllc_pllp_plla1_pllc2_c3_clkm_pllc4, CLK_SOURCE_ISP, 23, TEGRA_PERIPH_ON_APB, tegra_clk_isp_9),
|
||||
MUX8("entropy", mux_pllp_clkm1, CLK_SOURCE_ENTROPY, 149, 0, tegra_clk_entropy),
|
||||
MUX8("entropy", mux_pllp_clkm_clk32_plle, CLK_SOURCE_ENTROPY, 149, 0, tegra_clk_entropy_8),
|
||||
MUX8("hdmi_audio", mux_pllp3_pllc_clkm, CLK_SOURCE_HDMI_AUDIO, 176, TEGRA_PERIPH_NO_RESET, tegra_clk_hdmi_audio),
|
||||
MUX8("clk72mhz", mux_pllp3_pllc_clkm, CLK_SOURCE_CLK72MHZ, 177, TEGRA_PERIPH_NO_RESET, tegra_clk_clk72Mhz),
|
||||
MUX8("clk72mhz", mux_pllp_out3_pllp_pllc_clkm, CLK_SOURCE_CLK72MHZ, 177, TEGRA_PERIPH_NO_RESET, tegra_clk_clk72Mhz_8),
|
||||
MUX8_NOGATE_LOCK("sor0_lvds", mux_pllp_pllm_plld_plla_pllc_plld2_clkm, CLK_SOURCE_SOR0, tegra_clk_sor0_lvds, &sor0_lock),
|
||||
MUX_FLAGS("csite", mux_pllp_pllc_pllm_clkm, CLK_SOURCE_CSITE, 73, TEGRA_PERIPH_ON_APB, tegra_clk_csite, CLK_IGNORE_UNUSED),
|
||||
MUX_FLAGS("csite", mux_pllp_pllre_clkm, CLK_SOURCE_CSITE, 73, TEGRA_PERIPH_ON_APB, tegra_clk_csite_8, CLK_IGNORE_UNUSED),
|
||||
NODIV("disp1", mux_pllp_pllm_plld_plla_pllc_plld2_clkm, CLK_SOURCE_DISP1, 29, 7, 27, 0, tegra_clk_disp1, NULL),
|
||||
NODIV("disp1", mux_pllp_plld_plld2_clkm, CLK_SOURCE_DISP1, 29, 7, 27, 0, tegra_clk_disp1_8, NULL),
|
||||
NODIV("disp2", mux_pllp_pllm_plld_plla_pllc_plld2_clkm, CLK_SOURCE_DISP2, 29, 7, 26, 0, tegra_clk_disp2, NULL),
|
||||
NODIV("disp2", mux_pllp_plld_plld2_clkm, CLK_SOURCE_DISP2, 29, 7, 26, 0, tegra_clk_disp2_8, NULL),
|
||||
NODIV("sor0", mux_clkm_plldp_sor0lvds, CLK_SOURCE_SOR0, 14, 3, 182, 0, tegra_clk_sor0, &sor0_lock),
|
||||
UART("uarta", mux_pllp_pllc_pllm_clkm, CLK_SOURCE_UARTA, 6, tegra_clk_uarta),
|
||||
UART("uartb", mux_pllp_pllc_pllm_clkm, CLK_SOURCE_UARTB, 7, tegra_clk_uartb),
|
||||
UART("uartc", mux_pllp_pllc_pllm_clkm, CLK_SOURCE_UARTC, 55, tegra_clk_uartc),
|
||||
UART("uartd", mux_pllp_pllc_pllm_clkm, CLK_SOURCE_UARTD, 65, tegra_clk_uartd),
|
||||
UART("uarte", mux_pllp_pllc_pllm_clkm, CLK_SOURCE_UARTE, 66, tegra_clk_uarte),
|
||||
UART8("uarta", mux_pllp_pllc_pllc4_out0_pllc4_out1_clkm_pllc4_out2, CLK_SOURCE_UARTA, 6, tegra_clk_uarta_8),
|
||||
UART8("uartb", mux_pllp_pllc_pllc4_out0_pllc4_out1_clkm_pllc4_out2, CLK_SOURCE_UARTB, 7, tegra_clk_uartb_8),
|
||||
UART8("uartc", mux_pllp_pllc_pllc4_out0_pllc4_out1_clkm_pllc4_out2, CLK_SOURCE_UARTC, 55, tegra_clk_uartc_8),
|
||||
UART8("uartd", mux_pllp_pllc_pllc4_out0_pllc4_out1_clkm_pllc4_out2, CLK_SOURCE_UARTD, 65, tegra_clk_uartd_8),
|
||||
XUSB("xusb_host_src", mux_clkm_pllp_pllc_pllre, CLK_SOURCE_XUSB_HOST_SRC, 143, TEGRA_PERIPH_ON_APB | TEGRA_PERIPH_NO_RESET, tegra_clk_xusb_host_src),
|
||||
XUSB("xusb_host_src", mux_clkm_pllp_pllre, CLK_SOURCE_XUSB_HOST_SRC, 143, TEGRA_PERIPH_ON_APB | TEGRA_PERIPH_NO_RESET, tegra_clk_xusb_host_src_8),
|
||||
XUSB("xusb_falcon_src", mux_clkm_pllp_pllc_pllre, CLK_SOURCE_XUSB_FALCON_SRC, 143, TEGRA_PERIPH_NO_RESET, tegra_clk_xusb_falcon_src),
|
||||
XUSB("xusb_falcon_src", mux_clkm_pllp_pllre, CLK_SOURCE_XUSB_FALCON_SRC, 143, TEGRA_PERIPH_NO_RESET, tegra_clk_xusb_falcon_src_8),
|
||||
XUSB("xusb_fs_src", mux_clkm_48M_pllp_480M, CLK_SOURCE_XUSB_FS_SRC, 143, TEGRA_PERIPH_NO_RESET, tegra_clk_xusb_fs_src),
|
||||
XUSB("xusb_ss_src", mux_clkm_pllre_clk32_480M_pllc_ref, CLK_SOURCE_XUSB_SS_SRC, 143, TEGRA_PERIPH_NO_RESET, tegra_clk_xusb_ss_src),
|
||||
NODIV("xusb_hs_src", mux_ss_60M, CLK_SOURCE_XUSB_SS_SRC, 25, MASK(1), 143, TEGRA_PERIPH_NO_RESET, tegra_clk_xusb_hs_src, NULL),
|
||||
XUSB("xusb_ss_src", mux_clkm_pllre_clk32_480M, CLK_SOURCE_XUSB_SS_SRC, 143, TEGRA_PERIPH_NO_RESET, tegra_clk_xusb_ss_src_8),
|
||||
NODIV("xusb_hs_src", mux_ss_div2_60M, CLK_SOURCE_XUSB_SS_SRC, 25, MASK(1), 143, TEGRA_PERIPH_NO_RESET, tegra_clk_xusb_hs_src, NULL),
|
||||
NODIV("xusb_hs_src", mux_ss_div2_60M_ss, CLK_SOURCE_XUSB_SS_SRC, 25, MASK(2), 143, TEGRA_PERIPH_NO_RESET, tegra_clk_xusb_hs_src_4, NULL),
|
||||
NODIV("xusb_ssp_src", mux_ss_clkm, CLK_SOURCE_XUSB_SS_SRC, 24, MASK(1), 143, TEGRA_PERIPH_NO_RESET, tegra_clk_xusb_ssp_src, NULL),
|
||||
XUSB("xusb_dev_src", mux_clkm_pllp_pllc_pllre, CLK_SOURCE_XUSB_DEV_SRC, 95, TEGRA_PERIPH_ON_APB | TEGRA_PERIPH_NO_RESET, tegra_clk_xusb_dev_src),
|
||||
XUSB("xusb_dev_src", mux_clkm_pllp_pllre, CLK_SOURCE_XUSB_DEV_SRC, 95, TEGRA_PERIPH_ON_APB | TEGRA_PERIPH_NO_RESET, tegra_clk_xusb_dev_src_8),
|
||||
MUX8("dbgapb", mux_pllp_clkm_2, CLK_SOURCE_DBGAPB, 185, TEGRA_PERIPH_NO_RESET, tegra_clk_dbgapb),
|
||||
MUX8("msenc", mux_pllc2_c_c3_pllp_plla1_clkm, CLK_SOURCE_NVENC, 219, 0, tegra_clk_nvenc),
|
||||
MUX8("nvdec", mux_pllc2_c_c3_pllp_plla1_clkm, CLK_SOURCE_NVDEC, 194, 0, tegra_clk_nvdec),
|
||||
MUX8("nvjpg", mux_pllc2_c_c3_pllp_plla1_clkm, CLK_SOURCE_NVJPG, 195, 0, tegra_clk_nvjpg),
|
||||
MUX8("ape", mux_plla_pllc4_out0_pllc_pllc4_out1_pllp_pllc4_out2_clkm, CLK_SOURCE_APE, 198, TEGRA_PERIPH_ON_APB, tegra_clk_ape),
|
||||
MUX8_NOGATE_LOCK("sor1_src", mux_pllp_plld_plld2_clkm, CLK_SOURCE_SOR1, tegra_clk_sor1_src, &sor1_lock),
|
||||
NODIV("sor1_brick", mux_plldp_sor1_src, CLK_SOURCE_SOR1, 14, MASK(1), 183, 0, tegra_clk_sor1_brick, &sor1_lock),
|
||||
NODIV("sor1", mux_clkm_sor1_brick_sor1_src, CLK_SOURCE_SOR1, 15, MASK(1), 183, 0, tegra_clk_sor1, &sor1_lock),
|
||||
MUX8("sdmmc_legacy", mux_pllp_out3_clkm_pllp_pllc4, CLK_SOURCE_SDMMC_LEGACY, 193, TEGRA_PERIPH_ON_APB | TEGRA_PERIPH_NO_RESET, tegra_clk_sdmmc_legacy),
|
||||
MUX8("qspi", mux_pllp_pllc_pllc_out1_pllc4_out2_pllc4_out1_clkm_pllc4_out0, CLK_SOURCE_QSPI, 211, TEGRA_PERIPH_ON_APB, tegra_clk_qspi),
|
||||
MUX("vii2c", mux_pllp_pllc_clkm, CLK_SOURCE_VI_I2C, 208, TEGRA_PERIPH_ON_APB, tegra_clk_vi_i2c),
|
||||
MUX("mipibif", mux_pllp_clkm, CLK_SOURCE_MIPIBIF, 173, TEGRA_PERIPH_ON_APB, tegra_clk_mipibif),
|
||||
MUX("uartape", mux_pllp_pllc_clkm, CLK_SOURCE_UARTAPE, 212, TEGRA_PERIPH_ON_APB | TEGRA_PERIPH_NO_RESET, tegra_clk_uartape),
|
||||
MUX8("tsecb", mux_pllp_pllc2_c_c3_clkm, CLK_SOURCE_TSECB, 206, 0, tegra_clk_tsecb),
|
||||
MUX8("maud", mux_pllp_pllp_out3_clkm_clk32k_plla, CLK_SOURCE_MAUD, 202, TEGRA_PERIPH_ON_APB | TEGRA_PERIPH_NO_RESET, tegra_clk_maud),
|
||||
};
|
||||
|
||||
static struct tegra_periph_init_data gate_clks[] = {
|
||||
|
|
@ -543,6 +823,16 @@ static struct tegra_periph_init_data gate_clks[] = {
|
|||
GATE("pcie", "clk_m", 70, 0, tegra_clk_pcie, 0),
|
||||
GATE("dpaux", "clk_m", 181, 0, tegra_clk_dpaux, 0),
|
||||
GATE("gpu", "pll_ref", 184, 0, tegra_clk_gpu, 0),
|
||||
GATE("pllg_ref", "pll_ref", 189, 0, tegra_clk_pll_g_ref, 0),
|
||||
GATE("hsic_trk", "usb2_hsic_trk", 209, TEGRA_PERIPH_NO_RESET, tegra_clk_hsic_trk, 0),
|
||||
GATE("usb2_trk", "usb2_hsic_trk", 210, TEGRA_PERIPH_NO_RESET, tegra_clk_usb2_trk, 0),
|
||||
GATE("xusb_gate", "osc", 143, 0, tegra_clk_xusb_gate, 0),
|
||||
GATE("pll_p_out_cpu", "pll_p", 223, 0, tegra_clk_pll_p_out_cpu, 0),
|
||||
GATE("pll_p_out_adsp", "pll_p", 187, 0, tegra_clk_pll_p_out_adsp, 0),
|
||||
};
|
||||
|
||||
static struct tegra_periph_init_data div_clks[] = {
|
||||
DIV8("usb2_hsic_trk", "osc", CLK_SOURCE_USB2_HSIC_TRK, tegra_clk_usb2_hsic_trk, 0),
|
||||
};
|
||||
|
||||
struct pll_out_data {
|
||||
|
|
@ -633,6 +923,33 @@ static void __init gate_clk_init(void __iomem *clk_base,
|
|||
}
|
||||
}
|
||||
|
||||
static void __init div_clk_init(void __iomem *clk_base,
|
||||
struct tegra_clk *tegra_clks)
|
||||
{
|
||||
int i;
|
||||
struct clk *clk;
|
||||
struct clk **dt_clk;
|
||||
|
||||
for (i = 0; i < ARRAY_SIZE(div_clks); i++) {
|
||||
struct tegra_periph_init_data *data;
|
||||
|
||||
data = div_clks + i;
|
||||
|
||||
dt_clk = tegra_lookup_dt_id(data->clk_id, tegra_clks);
|
||||
if (!dt_clk)
|
||||
continue;
|
||||
|
||||
clk = tegra_clk_register_divider(data->name,
|
||||
data->p.parent_name, clk_base + data->offset,
|
||||
data->flags, data->periph.divider.flags,
|
||||
data->periph.divider.shift,
|
||||
data->periph.divider.width,
|
||||
data->periph.divider.frac_width,
|
||||
data->periph.divider.lock);
|
||||
*dt_clk = clk;
|
||||
}
|
||||
}
|
||||
|
||||
static void __init init_pllp(void __iomem *clk_base, void __iomem *pmc_base,
|
||||
struct tegra_clk *tegra_clks,
|
||||
struct tegra_clk_pll_params *pll_params)
|
||||
|
|
@ -669,6 +986,51 @@ static void __init init_pllp(void __iomem *clk_base, void __iomem *pmc_base,
|
|||
data->lock);
|
||||
*dt_clk = clk;
|
||||
}
|
||||
|
||||
dt_clk = tegra_lookup_dt_id(tegra_clk_pll_p_out_cpu,
|
||||
tegra_clks);
|
||||
if (dt_clk) {
|
||||
/*
|
||||
* Tegra210 has control on enabling/disabling PLLP branches to
|
||||
* CPU, register a gate clock "pll_p_out_cpu" for this gating
|
||||
* function and parent "pll_p_out4" to it, so when we are
|
||||
* re-parenting CPU off from "pll_p_out4" the PLLP branching to
|
||||
* CPU can be disabled automatically.
|
||||
*/
|
||||
clk = tegra_clk_register_divider("pll_p_out4_div",
|
||||
"pll_p_out_cpu", clk_base + PLLP_OUTB, 0, 0, 24,
|
||||
8, 1, &PLLP_OUTB_lock);
|
||||
|
||||
dt_clk = tegra_lookup_dt_id(tegra_clk_pll_p_out4_cpu, tegra_clks);
|
||||
if (dt_clk) {
|
||||
clk = tegra_clk_register_pll_out("pll_p_out4",
|
||||
"pll_p_out4_div", clk_base + PLLP_OUTB,
|
||||
17, 16, CLK_IGNORE_UNUSED |
|
||||
CLK_SET_RATE_PARENT, 0,
|
||||
&PLLP_OUTB_lock);
|
||||
*dt_clk = clk;
|
||||
}
|
||||
}
|
||||
|
||||
dt_clk = tegra_lookup_dt_id(tegra_clk_pll_p_out_hsio, tegra_clks);
|
||||
if (dt_clk) {
|
||||
/* PLLP_OUT_HSIO */
|
||||
clk = clk_register_gate(NULL, "pll_p_out_hsio", "pll_p",
|
||||
CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
|
||||
clk_base + PLLP_MISC1, 29, 0, NULL);
|
||||
*dt_clk = clk;
|
||||
}
|
||||
|
||||
dt_clk = tegra_lookup_dt_id(tegra_clk_pll_p_out_xusb, tegra_clks);
|
||||
if (dt_clk) {
|
||||
/* PLLP_OUT_XUSB */
|
||||
clk = clk_register_gate(NULL, "pll_p_out_xusb",
|
||||
"pll_p_out_hsio", CLK_SET_RATE_PARENT |
|
||||
CLK_IGNORE_UNUSED, clk_base + PLLP_MISC1, 28, 0,
|
||||
NULL);
|
||||
clk_register_clkdev(clk, "pll_p_out_xusb", NULL);
|
||||
*dt_clk = clk;
|
||||
}
|
||||
}
|
||||
|
||||
void __init tegra_periph_clk_init(void __iomem *clk_base,
|
||||
|
|
@ -678,4 +1040,5 @@ void __init tegra_periph_clk_init(void __iomem *clk_base,
|
|||
init_pllp(clk_base, pmc_base, tegra_clks, pll_params);
|
||||
periph_clk_init(clk_base, tegra_clks);
|
||||
gate_clk_init(clk_base, tegra_clks);
|
||||
div_clk_init(clk_base, tegra_clks);
|
||||
}
|
||||
|
|
|
|||
|
|
@ -34,9 +34,25 @@
|
|||
#define CCLKLP_BURST_POLICY 0x370
|
||||
#define SCLK_BURST_POLICY 0x028
|
||||
#define SYSTEM_CLK_RATE 0x030
|
||||
#define SCLK_DIVIDER 0x2c
|
||||
|
||||
static DEFINE_SPINLOCK(sysrate_lock);
|
||||
|
||||
enum tegra_super_gen {
|
||||
gen4 = 4,
|
||||
gen5,
|
||||
};
|
||||
|
||||
struct tegra_super_gen_info {
|
||||
enum tegra_super_gen gen;
|
||||
const char **sclk_parents;
|
||||
const char **cclk_g_parents;
|
||||
const char **cclk_lp_parents;
|
||||
int num_sclk_parents;
|
||||
int num_cclk_g_parents;
|
||||
int num_cclk_lp_parents;
|
||||
};
|
||||
|
||||
static const char *sclk_parents[] = { "clk_m", "pll_c_out1", "pll_p_out4",
|
||||
"pll_p", "pll_p_out2", "unused",
|
||||
"clk_32k", "pll_m_out1" };
|
||||
|
|
@ -51,21 +67,81 @@ static const char *cclk_lp_parents[] = { "clk_m", "pll_c", "clk_32k", "pll_m",
|
|||
"pll_p", "pll_p_out4", "unused",
|
||||
"unused", "pll_x", "pll_x_out0" };
|
||||
|
||||
const struct tegra_super_gen_info tegra_super_gen_info_gen4 = {
|
||||
.gen = gen4,
|
||||
.sclk_parents = sclk_parents,
|
||||
.cclk_g_parents = cclk_g_parents,
|
||||
.cclk_lp_parents = cclk_lp_parents,
|
||||
.num_sclk_parents = ARRAY_SIZE(sclk_parents),
|
||||
.num_cclk_g_parents = ARRAY_SIZE(cclk_g_parents),
|
||||
.num_cclk_lp_parents = ARRAY_SIZE(cclk_lp_parents),
|
||||
};
|
||||
|
||||
static const char *sclk_parents_gen5[] = { "clk_m", "pll_c_out1", "pll_c4_out3",
|
||||
"pll_p", "pll_p_out2", "pll_c4_out1",
|
||||
"clk_32k", "pll_c4_out2" };
|
||||
|
||||
static const char *cclk_g_parents_gen5[] = { "clk_m", "unused", "clk_32k", "unused",
|
||||
"pll_p", "pll_p_out4", "unused",
|
||||
"unused", "pll_x", "unused", "unused",
|
||||
"unused", "unused", "unused", "unused",
|
||||
"dfllCPU_out" };
|
||||
|
||||
static const char *cclk_lp_parents_gen5[] = { "clk_m", "unused", "clk_32k", "unused",
|
||||
"pll_p", "pll_p_out4", "unused",
|
||||
"unused", "pll_x", "unused", "unused",
|
||||
"unused", "unused", "unused", "unused",
|
||||
"dfllCPU_out" };
|
||||
|
||||
const struct tegra_super_gen_info tegra_super_gen_info_gen5 = {
|
||||
.gen = gen5,
|
||||
.sclk_parents = sclk_parents_gen5,
|
||||
.cclk_g_parents = cclk_g_parents_gen5,
|
||||
.cclk_lp_parents = cclk_lp_parents_gen5,
|
||||
.num_sclk_parents = ARRAY_SIZE(sclk_parents_gen5),
|
||||
.num_cclk_g_parents = ARRAY_SIZE(cclk_g_parents_gen5),
|
||||
.num_cclk_lp_parents = ARRAY_SIZE(cclk_lp_parents_gen5),
|
||||
};
|
||||
|
||||
static void __init tegra_sclk_init(void __iomem *clk_base,
|
||||
struct tegra_clk *tegra_clks)
|
||||
struct tegra_clk *tegra_clks,
|
||||
const struct tegra_super_gen_info *gen_info)
|
||||
{
|
||||
struct clk *clk;
|
||||
struct clk **dt_clk;
|
||||
|
||||
/* SCLK */
|
||||
dt_clk = tegra_lookup_dt_id(tegra_clk_sclk, tegra_clks);
|
||||
/* SCLK_MUX */
|
||||
dt_clk = tegra_lookup_dt_id(tegra_clk_sclk_mux, tegra_clks);
|
||||
if (dt_clk) {
|
||||
clk = tegra_clk_register_super_mux("sclk", sclk_parents,
|
||||
ARRAY_SIZE(sclk_parents),
|
||||
clk = tegra_clk_register_super_mux("sclk_mux",
|
||||
gen_info->sclk_parents,
|
||||
gen_info->num_sclk_parents,
|
||||
CLK_SET_RATE_PARENT,
|
||||
clk_base + SCLK_BURST_POLICY,
|
||||
0, 4, 0, 0, NULL);
|
||||
*dt_clk = clk;
|
||||
|
||||
|
||||
/* SCLK */
|
||||
dt_clk = tegra_lookup_dt_id(tegra_clk_sclk, tegra_clks);
|
||||
if (dt_clk) {
|
||||
clk = clk_register_divider(NULL, "sclk", "sclk_mux", 0,
|
||||
clk_base + SCLK_DIVIDER, 0, 8,
|
||||
0, &sysrate_lock);
|
||||
*dt_clk = clk;
|
||||
}
|
||||
} else {
|
||||
/* SCLK */
|
||||
dt_clk = tegra_lookup_dt_id(tegra_clk_sclk, tegra_clks);
|
||||
if (dt_clk) {
|
||||
clk = tegra_clk_register_super_mux("sclk",
|
||||
gen_info->sclk_parents,
|
||||
gen_info->num_sclk_parents,
|
||||
CLK_SET_RATE_PARENT,
|
||||
clk_base + SCLK_BURST_POLICY,
|
||||
0, 4, 0, 0, NULL);
|
||||
*dt_clk = clk;
|
||||
}
|
||||
}
|
||||
|
||||
/* HCLK */
|
||||
|
|
@ -95,10 +171,11 @@ static void __init tegra_sclk_init(void __iomem *clk_base,
|
|||
*dt_clk = clk;
|
||||
}
|
||||
|
||||
void __init tegra_super_clk_gen4_init(void __iomem *clk_base,
|
||||
void __init tegra_super_clk_init(void __iomem *clk_base,
|
||||
void __iomem *pmc_base,
|
||||
struct tegra_clk *tegra_clks,
|
||||
struct tegra_clk_pll_params *params)
|
||||
struct tegra_clk_pll_params *params,
|
||||
const struct tegra_super_gen_info *gen_info)
|
||||
{
|
||||
struct clk *clk;
|
||||
struct clk **dt_clk;
|
||||
|
|
@ -106,28 +183,50 @@ void __init tegra_super_clk_gen4_init(void __iomem *clk_base,
|
|||
/* CCLKG */
|
||||
dt_clk = tegra_lookup_dt_id(tegra_clk_cclk_g, tegra_clks);
|
||||
if (dt_clk) {
|
||||
clk = tegra_clk_register_super_mux("cclk_g", cclk_g_parents,
|
||||
ARRAY_SIZE(cclk_g_parents),
|
||||
if (gen_info->gen == gen5) {
|
||||
clk = tegra_clk_register_super_mux("cclk_g",
|
||||
gen_info->cclk_g_parents,
|
||||
gen_info->num_cclk_g_parents,
|
||||
CLK_SET_RATE_PARENT,
|
||||
clk_base + CCLKG_BURST_POLICY,
|
||||
0, 4, 8, 0, NULL);
|
||||
} else {
|
||||
clk = tegra_clk_register_super_mux("cclk_g",
|
||||
gen_info->cclk_g_parents,
|
||||
gen_info->num_cclk_g_parents,
|
||||
CLK_SET_RATE_PARENT,
|
||||
clk_base + CCLKG_BURST_POLICY,
|
||||
0, 4, 0, 0, NULL);
|
||||
}
|
||||
*dt_clk = clk;
|
||||
}
|
||||
|
||||
/* CCLKLP */
|
||||
dt_clk = tegra_lookup_dt_id(tegra_clk_cclk_lp, tegra_clks);
|
||||
if (dt_clk) {
|
||||
clk = tegra_clk_register_super_mux("cclk_lp", cclk_lp_parents,
|
||||
ARRAY_SIZE(cclk_lp_parents),
|
||||
if (gen_info->gen == gen5) {
|
||||
clk = tegra_clk_register_super_mux("cclk_lp",
|
||||
gen_info->cclk_lp_parents,
|
||||
gen_info->num_cclk_lp_parents,
|
||||
CLK_SET_RATE_PARENT,
|
||||
clk_base + CCLKLP_BURST_POLICY,
|
||||
0, 4, 8, 0, NULL);
|
||||
} else {
|
||||
clk = tegra_clk_register_super_mux("cclk_lp",
|
||||
gen_info->cclk_lp_parents,
|
||||
gen_info->num_cclk_lp_parents,
|
||||
CLK_SET_RATE_PARENT,
|
||||
clk_base + CCLKLP_BURST_POLICY,
|
||||
TEGRA_DIVIDER_2, 4, 8, 9, NULL);
|
||||
}
|
||||
*dt_clk = clk;
|
||||
}
|
||||
|
||||
tegra_sclk_init(clk_base, tegra_clks);
|
||||
tegra_sclk_init(clk_base, tegra_clks, gen_info);
|
||||
|
||||
#if defined(CONFIG_ARCH_TEGRA_114_SOC) || defined(CONFIG_ARCH_TEGRA_124_SOC)
|
||||
#if defined(CONFIG_ARCH_TEGRA_114_SOC) || \
|
||||
defined(CONFIG_ARCH_TEGRA_124_SOC) || \
|
||||
defined(CONFIG_ARCH_TEGRA_210_SOC)
|
||||
/* PLLX */
|
||||
dt_clk = tegra_lookup_dt_id(tegra_clk_pll_x, tegra_clks);
|
||||
if (!dt_clk)
|
||||
|
|
@ -148,3 +247,20 @@ void __init tegra_super_clk_gen4_init(void __iomem *clk_base,
|
|||
#endif
|
||||
}
|
||||
|
||||
void __init tegra_super_clk_gen4_init(void __iomem *clk_base,
|
||||
void __iomem *pmc_base,
|
||||
struct tegra_clk *tegra_clks,
|
||||
struct tegra_clk_pll_params *params)
|
||||
{
|
||||
tegra_super_clk_init(clk_base, pmc_base, tegra_clks, params,
|
||||
&tegra_super_gen_info_gen4);
|
||||
}
|
||||
|
||||
void __init tegra_super_clk_gen5_init(void __iomem *clk_base,
|
||||
void __iomem *pmc_base,
|
||||
struct tegra_clk *tegra_clks,
|
||||
struct tegra_clk_pll_params *params)
|
||||
{
|
||||
tegra_super_clk_init(clk_base, pmc_base, tegra_clks, params,
|
||||
&tegra_super_gen_info_gen5);
|
||||
}
|
||||
|
|
|
|||
|
|
@ -182,40 +182,40 @@ static struct div_nmp pllxc_nmp = {
|
|||
.divp_width = 4,
|
||||
};
|
||||
|
||||
static struct pdiv_map pllxc_p[] = {
|
||||
{ .pdiv = 1, .hw_val = 0 },
|
||||
{ .pdiv = 2, .hw_val = 1 },
|
||||
{ .pdiv = 3, .hw_val = 2 },
|
||||
{ .pdiv = 4, .hw_val = 3 },
|
||||
{ .pdiv = 5, .hw_val = 4 },
|
||||
{ .pdiv = 6, .hw_val = 5 },
|
||||
{ .pdiv = 8, .hw_val = 6 },
|
||||
{ .pdiv = 10, .hw_val = 7 },
|
||||
{ .pdiv = 12, .hw_val = 8 },
|
||||
{ .pdiv = 16, .hw_val = 9 },
|
||||
static const struct pdiv_map pllxc_p[] = {
|
||||
{ .pdiv = 1, .hw_val = 0 },
|
||||
{ .pdiv = 2, .hw_val = 1 },
|
||||
{ .pdiv = 3, .hw_val = 2 },
|
||||
{ .pdiv = 4, .hw_val = 3 },
|
||||
{ .pdiv = 5, .hw_val = 4 },
|
||||
{ .pdiv = 6, .hw_val = 5 },
|
||||
{ .pdiv = 8, .hw_val = 6 },
|
||||
{ .pdiv = 10, .hw_val = 7 },
|
||||
{ .pdiv = 12, .hw_val = 8 },
|
||||
{ .pdiv = 16, .hw_val = 9 },
|
||||
{ .pdiv = 12, .hw_val = 10 },
|
||||
{ .pdiv = 16, .hw_val = 11 },
|
||||
{ .pdiv = 20, .hw_val = 12 },
|
||||
{ .pdiv = 24, .hw_val = 13 },
|
||||
{ .pdiv = 32, .hw_val = 14 },
|
||||
{ .pdiv = 0, .hw_val = 0 },
|
||||
{ .pdiv = 0, .hw_val = 0 },
|
||||
};
|
||||
|
||||
static struct tegra_clk_pll_freq_table pll_c_freq_table[] = {
|
||||
{ 12000000, 624000000, 104, 0, 2},
|
||||
{ 12000000, 600000000, 100, 0, 2},
|
||||
{ 13000000, 600000000, 92, 0, 2}, /* actual: 598.0 MHz */
|
||||
{ 16800000, 600000000, 71, 0, 2}, /* actual: 596.4 MHz */
|
||||
{ 19200000, 600000000, 62, 0, 2}, /* actual: 595.2 MHz */
|
||||
{ 26000000, 600000000, 92, 1, 2}, /* actual: 598.0 MHz */
|
||||
{ 0, 0, 0, 0, 0, 0 },
|
||||
{ 12000000, 624000000, 104, 1, 2, 0 },
|
||||
{ 12000000, 600000000, 100, 1, 2, 0 },
|
||||
{ 13000000, 600000000, 92, 1, 2, 0 }, /* actual: 598.0 MHz */
|
||||
{ 16800000, 600000000, 71, 1, 2, 0 }, /* actual: 596.4 MHz */
|
||||
{ 19200000, 600000000, 62, 1, 2, 0 }, /* actual: 595.2 MHz */
|
||||
{ 26000000, 600000000, 92, 2, 2, 0 }, /* actual: 598.0 MHz */
|
||||
{ 0, 0, 0, 0, 0, 0 },
|
||||
};
|
||||
|
||||
static struct tegra_clk_pll_params pll_c_params = {
|
||||
.input_min = 12000000,
|
||||
.input_max = 800000000,
|
||||
.cf_min = 12000000,
|
||||
.cf_max = 19200000, /* s/w policy, h/w capability 50 MHz */
|
||||
.cf_max = 19200000, /* s/w policy, h/w capability 50 MHz */
|
||||
.vco_min = 600000000,
|
||||
.vco_max = 1400000000,
|
||||
.base_reg = PLLC_BASE,
|
||||
|
|
@ -232,7 +232,7 @@ static struct tegra_clk_pll_params pll_c_params = {
|
|||
.pdiv_tohw = pllxc_p,
|
||||
.div_nmp = &pllxc_nmp,
|
||||
.freq_table = pll_c_freq_table,
|
||||
.flags = TEGRA_PLL_USE_LOCK,
|
||||
.flags = TEGRA_PLL_USE_LOCK | TEGRA_PLL_HAS_LOCK_ENABLE,
|
||||
};
|
||||
|
||||
static struct div_nmp pllcx_nmp = {
|
||||
|
|
@ -244,22 +244,22 @@ static struct div_nmp pllcx_nmp = {
|
|||
.divp_width = 3,
|
||||
};
|
||||
|
||||
static struct pdiv_map pllc_p[] = {
|
||||
{ .pdiv = 1, .hw_val = 0 },
|
||||
{ .pdiv = 2, .hw_val = 1 },
|
||||
{ .pdiv = 4, .hw_val = 3 },
|
||||
{ .pdiv = 8, .hw_val = 5 },
|
||||
static const struct pdiv_map pllc_p[] = {
|
||||
{ .pdiv = 1, .hw_val = 0 },
|
||||
{ .pdiv = 2, .hw_val = 1 },
|
||||
{ .pdiv = 4, .hw_val = 3 },
|
||||
{ .pdiv = 8, .hw_val = 5 },
|
||||
{ .pdiv = 16, .hw_val = 7 },
|
||||
{ .pdiv = 0, .hw_val = 0 },
|
||||
{ .pdiv = 0, .hw_val = 0 },
|
||||
};
|
||||
|
||||
static struct tegra_clk_pll_freq_table pll_cx_freq_table[] = {
|
||||
{12000000, 600000000, 100, 0, 2},
|
||||
{13000000, 600000000, 92, 0, 2}, /* actual: 598.0 MHz */
|
||||
{16800000, 600000000, 71, 0, 2}, /* actual: 596.4 MHz */
|
||||
{19200000, 600000000, 62, 0, 2}, /* actual: 595.2 MHz */
|
||||
{26000000, 600000000, 92, 1, 2}, /* actual: 598.0 MHz */
|
||||
{0, 0, 0, 0, 0, 0},
|
||||
{ 12000000, 600000000, 100, 1, 2, 0 },
|
||||
{ 13000000, 600000000, 92, 1, 2, 0 }, /* actual: 598.0 MHz */
|
||||
{ 16800000, 600000000, 71, 1, 2, 0 }, /* actual: 596.4 MHz */
|
||||
{ 19200000, 600000000, 62, 1, 2, 0 }, /* actual: 595.2 MHz */
|
||||
{ 26000000, 600000000, 92, 2, 2, 0 }, /* actual: 598.0 MHz */
|
||||
{ 0, 0, 0, 0, 0, 0 },
|
||||
};
|
||||
|
||||
static struct tegra_clk_pll_params pll_c2_params = {
|
||||
|
|
@ -318,26 +318,26 @@ static struct div_nmp pllm_nmp = {
|
|||
.override_divp_shift = 27,
|
||||
};
|
||||
|
||||
static struct pdiv_map pllm_p[] = {
|
||||
static const struct pdiv_map pllm_p[] = {
|
||||
{ .pdiv = 1, .hw_val = 0 },
|
||||
{ .pdiv = 2, .hw_val = 1 },
|
||||
{ .pdiv = 0, .hw_val = 0 },
|
||||
};
|
||||
|
||||
static struct tegra_clk_pll_freq_table pll_m_freq_table[] = {
|
||||
{12000000, 800000000, 66, 0, 1}, /* actual: 792.0 MHz */
|
||||
{13000000, 800000000, 61, 0, 1}, /* actual: 793.0 MHz */
|
||||
{16800000, 800000000, 47, 0, 1}, /* actual: 789.6 MHz */
|
||||
{19200000, 800000000, 41, 0, 1}, /* actual: 787.2 MHz */
|
||||
{26000000, 800000000, 61, 1, 1}, /* actual: 793.0 MHz */
|
||||
{0, 0, 0, 0, 0, 0},
|
||||
{ 12000000, 800000000, 66, 1, 1, 0 }, /* actual: 792.0 MHz */
|
||||
{ 13000000, 800000000, 61, 1, 1, 0 }, /* actual: 793.0 MHz */
|
||||
{ 16800000, 800000000, 47, 1, 1, 0 }, /* actual: 789.6 MHz */
|
||||
{ 19200000, 800000000, 41, 1, 1, 0 }, /* actual: 787.2 MHz */
|
||||
{ 26000000, 800000000, 61, 2, 1, 0 }, /* actual: 793.0 MHz */
|
||||
{ 0, 0, 0, 0, 0, 0 },
|
||||
};
|
||||
|
||||
static struct tegra_clk_pll_params pll_m_params = {
|
||||
.input_min = 12000000,
|
||||
.input_max = 500000000,
|
||||
.cf_min = 12000000,
|
||||
.cf_max = 19200000, /* s/w policy, h/w capability 50 MHz */
|
||||
.cf_max = 19200000, /* s/w policy, h/w capability 50 MHz */
|
||||
.vco_min = 400000000,
|
||||
.vco_max = 1066000000,
|
||||
.base_reg = PLLM_BASE,
|
||||
|
|
@ -351,7 +351,8 @@ static struct tegra_clk_pll_params pll_m_params = {
|
|||
.pmc_divnm_reg = PMC_PLLM_WB0_OVERRIDE,
|
||||
.pmc_divp_reg = PMC_PLLM_WB0_OVERRIDE_2,
|
||||
.freq_table = pll_m_freq_table,
|
||||
.flags = TEGRA_PLL_USE_LOCK,
|
||||
.flags = TEGRA_PLL_USE_LOCK | TEGRA_PLL_HAS_LOCK_ENABLE |
|
||||
TEGRA_PLL_FIXED,
|
||||
};
|
||||
|
||||
static struct div_nmp pllp_nmp = {
|
||||
|
|
@ -364,12 +365,12 @@ static struct div_nmp pllp_nmp = {
|
|||
};
|
||||
|
||||
static struct tegra_clk_pll_freq_table pll_p_freq_table[] = {
|
||||
{12000000, 216000000, 432, 12, 1, 8},
|
||||
{13000000, 216000000, 432, 13, 1, 8},
|
||||
{16800000, 216000000, 360, 14, 1, 8},
|
||||
{19200000, 216000000, 360, 16, 1, 8},
|
||||
{26000000, 216000000, 432, 26, 1, 8},
|
||||
{0, 0, 0, 0, 0, 0},
|
||||
{ 12000000, 216000000, 432, 12, 2, 8 },
|
||||
{ 13000000, 216000000, 432, 13, 2, 8 },
|
||||
{ 16800000, 216000000, 360, 14, 2, 8 },
|
||||
{ 19200000, 216000000, 360, 16, 2, 8 },
|
||||
{ 26000000, 216000000, 432, 26, 2, 8 },
|
||||
{ 0, 0, 0, 0, 0, 0 },
|
||||
};
|
||||
|
||||
static struct tegra_clk_pll_params pll_p_params = {
|
||||
|
|
@ -386,19 +387,19 @@ static struct tegra_clk_pll_params pll_p_params = {
|
|||
.lock_delay = 300,
|
||||
.div_nmp = &pllp_nmp,
|
||||
.freq_table = pll_p_freq_table,
|
||||
.flags = TEGRA_PLL_FIXED | TEGRA_PLL_USE_LOCK,
|
||||
.flags = TEGRA_PLL_FIXED | TEGRA_PLL_USE_LOCK |
|
||||
TEGRA_PLL_HAS_LOCK_ENABLE,
|
||||
.fixed_rate = 408000000,
|
||||
};
|
||||
|
||||
static struct tegra_clk_pll_freq_table pll_a_freq_table[] = {
|
||||
{9600000, 282240000, 147, 5, 0, 4},
|
||||
{9600000, 368640000, 192, 5, 0, 4},
|
||||
{9600000, 240000000, 200, 8, 0, 8},
|
||||
|
||||
{28800000, 282240000, 245, 25, 0, 8},
|
||||
{28800000, 368640000, 320, 25, 0, 8},
|
||||
{28800000, 240000000, 200, 24, 0, 8},
|
||||
{0, 0, 0, 0, 0, 0},
|
||||
{ 9600000, 282240000, 147, 5, 1, 4 },
|
||||
{ 9600000, 368640000, 192, 5, 1, 4 },
|
||||
{ 9600000, 240000000, 200, 8, 1, 8 },
|
||||
{ 28800000, 282240000, 245, 25, 1, 8 },
|
||||
{ 28800000, 368640000, 320, 25, 1, 8 },
|
||||
{ 28800000, 240000000, 200, 24, 1, 8 },
|
||||
{ 0, 0, 0, 0, 0, 0 },
|
||||
};
|
||||
|
||||
|
||||
|
|
@ -416,28 +417,26 @@ static struct tegra_clk_pll_params pll_a_params = {
|
|||
.lock_delay = 300,
|
||||
.div_nmp = &pllp_nmp,
|
||||
.freq_table = pll_a_freq_table,
|
||||
.flags = TEGRA_PLL_HAS_CPCON | TEGRA_PLL_USE_LOCK,
|
||||
.flags = TEGRA_PLL_HAS_CPCON | TEGRA_PLL_USE_LOCK |
|
||||
TEGRA_PLL_HAS_LOCK_ENABLE,
|
||||
};
|
||||
|
||||
static struct tegra_clk_pll_freq_table pll_d_freq_table[] = {
|
||||
{12000000, 216000000, 864, 12, 2, 12},
|
||||
{13000000, 216000000, 864, 13, 2, 12},
|
||||
{16800000, 216000000, 720, 14, 2, 12},
|
||||
{19200000, 216000000, 720, 16, 2, 12},
|
||||
{26000000, 216000000, 864, 26, 2, 12},
|
||||
|
||||
{12000000, 594000000, 594, 12, 0, 12},
|
||||
{13000000, 594000000, 594, 13, 0, 12},
|
||||
{16800000, 594000000, 495, 14, 0, 12},
|
||||
{19200000, 594000000, 495, 16, 0, 12},
|
||||
{26000000, 594000000, 594, 26, 0, 12},
|
||||
|
||||
{12000000, 1000000000, 1000, 12, 0, 12},
|
||||
{13000000, 1000000000, 1000, 13, 0, 12},
|
||||
{19200000, 1000000000, 625, 12, 0, 12},
|
||||
{26000000, 1000000000, 1000, 26, 0, 12},
|
||||
|
||||
{0, 0, 0, 0, 0, 0},
|
||||
{ 12000000, 216000000, 864, 12, 4, 12 },
|
||||
{ 13000000, 216000000, 864, 13, 4, 12 },
|
||||
{ 16800000, 216000000, 720, 14, 4, 12 },
|
||||
{ 19200000, 216000000, 720, 16, 4, 12 },
|
||||
{ 26000000, 216000000, 864, 26, 4, 12 },
|
||||
{ 12000000, 594000000, 594, 12, 1, 12 },
|
||||
{ 13000000, 594000000, 594, 13, 1, 12 },
|
||||
{ 16800000, 594000000, 495, 14, 1, 12 },
|
||||
{ 19200000, 594000000, 495, 16, 1, 12 },
|
||||
{ 26000000, 594000000, 594, 26, 1, 12 },
|
||||
{ 12000000, 1000000000, 1000, 12, 1, 12 },
|
||||
{ 13000000, 1000000000, 1000, 13, 1, 12 },
|
||||
{ 19200000, 1000000000, 625, 12, 1, 12 },
|
||||
{ 26000000, 1000000000, 1000, 26, 1, 12 },
|
||||
{ 0, 0, 0, 0, 0, 0 },
|
||||
};
|
||||
|
||||
static struct tegra_clk_pll_params pll_d_params = {
|
||||
|
|
@ -455,7 +454,7 @@ static struct tegra_clk_pll_params pll_d_params = {
|
|||
.div_nmp = &pllp_nmp,
|
||||
.freq_table = pll_d_freq_table,
|
||||
.flags = TEGRA_PLL_HAS_CPCON | TEGRA_PLL_SET_LFCON |
|
||||
TEGRA_PLL_USE_LOCK,
|
||||
TEGRA_PLL_USE_LOCK | TEGRA_PLL_HAS_LOCK_ENABLE,
|
||||
};
|
||||
|
||||
static struct tegra_clk_pll_params pll_d2_params = {
|
||||
|
|
@ -473,10 +472,10 @@ static struct tegra_clk_pll_params pll_d2_params = {
|
|||
.div_nmp = &pllp_nmp,
|
||||
.freq_table = pll_d_freq_table,
|
||||
.flags = TEGRA_PLL_HAS_CPCON | TEGRA_PLL_SET_LFCON |
|
||||
TEGRA_PLL_USE_LOCK,
|
||||
TEGRA_PLL_USE_LOCK | TEGRA_PLL_HAS_LOCK_ENABLE,
|
||||
};
|
||||
|
||||
static struct pdiv_map pllu_p[] = {
|
||||
static const struct pdiv_map pllu_p[] = {
|
||||
{ .pdiv = 1, .hw_val = 1 },
|
||||
{ .pdiv = 2, .hw_val = 0 },
|
||||
{ .pdiv = 0, .hw_val = 0 },
|
||||
|
|
@ -492,12 +491,12 @@ static struct div_nmp pllu_nmp = {
|
|||
};
|
||||
|
||||
static struct tegra_clk_pll_freq_table pll_u_freq_table[] = {
|
||||
{12000000, 480000000, 960, 12, 0, 12},
|
||||
{13000000, 480000000, 960, 13, 0, 12},
|
||||
{16800000, 480000000, 400, 7, 0, 5},
|
||||
{19200000, 480000000, 200, 4, 0, 3},
|
||||
{26000000, 480000000, 960, 26, 0, 12},
|
||||
{0, 0, 0, 0, 0, 0},
|
||||
{ 12000000, 480000000, 960, 12, 2, 12 },
|
||||
{ 13000000, 480000000, 960, 13, 2, 12 },
|
||||
{ 16800000, 480000000, 400, 7, 2, 5 },
|
||||
{ 19200000, 480000000, 200, 4, 2, 3 },
|
||||
{ 26000000, 480000000, 960, 26, 2, 12 },
|
||||
{ 0, 0, 0, 0, 0, 0 },
|
||||
};
|
||||
|
||||
static struct tegra_clk_pll_params pll_u_params = {
|
||||
|
|
@ -516,25 +515,24 @@ static struct tegra_clk_pll_params pll_u_params = {
|
|||
.div_nmp = &pllu_nmp,
|
||||
.freq_table = pll_u_freq_table,
|
||||
.flags = TEGRA_PLLU | TEGRA_PLL_HAS_CPCON | TEGRA_PLL_SET_LFCON |
|
||||
TEGRA_PLL_USE_LOCK,
|
||||
TEGRA_PLL_USE_LOCK | TEGRA_PLL_HAS_LOCK_ENABLE,
|
||||
};
|
||||
|
||||
static struct tegra_clk_pll_freq_table pll_x_freq_table[] = {
|
||||
/* 1 GHz */
|
||||
{12000000, 1000000000, 83, 0, 1}, /* actual: 996.0 MHz */
|
||||
{13000000, 1000000000, 76, 0, 1}, /* actual: 988.0 MHz */
|
||||
{16800000, 1000000000, 59, 0, 1}, /* actual: 991.2 MHz */
|
||||
{19200000, 1000000000, 52, 0, 1}, /* actual: 998.4 MHz */
|
||||
{26000000, 1000000000, 76, 1, 1}, /* actual: 988.0 MHz */
|
||||
|
||||
{0, 0, 0, 0, 0, 0},
|
||||
{ 12000000, 1000000000, 83, 1, 1, 0 }, /* actual: 996.0 MHz */
|
||||
{ 13000000, 1000000000, 76, 1, 1, 0 }, /* actual: 988.0 MHz */
|
||||
{ 16800000, 1000000000, 59, 1, 1, 0 }, /* actual: 991.2 MHz */
|
||||
{ 19200000, 1000000000, 52, 1, 1, 0 }, /* actual: 998.4 MHz */
|
||||
{ 26000000, 1000000000, 76, 2, 1, 0 }, /* actual: 988.0 MHz */
|
||||
{ 0, 0, 0, 0, 0, 0 },
|
||||
};
|
||||
|
||||
static struct tegra_clk_pll_params pll_x_params = {
|
||||
.input_min = 12000000,
|
||||
.input_max = 800000000,
|
||||
.cf_min = 12000000,
|
||||
.cf_max = 19200000, /* s/w policy, h/w capability 50 MHz */
|
||||
.cf_max = 19200000, /* s/w policy, h/w capability 50 MHz */
|
||||
.vco_min = 700000000,
|
||||
.vco_max = 2400000000U,
|
||||
.base_reg = PLLX_BASE,
|
||||
|
|
@ -551,15 +549,34 @@ static struct tegra_clk_pll_params pll_x_params = {
|
|||
.pdiv_tohw = pllxc_p,
|
||||
.div_nmp = &pllxc_nmp,
|
||||
.freq_table = pll_x_freq_table,
|
||||
.flags = TEGRA_PLL_USE_LOCK,
|
||||
.flags = TEGRA_PLL_USE_LOCK | TEGRA_PLL_HAS_LOCK_ENABLE,
|
||||
};
|
||||
|
||||
static struct tegra_clk_pll_freq_table pll_e_freq_table[] = {
|
||||
/* PLLE special case: use cpcon field to store cml divider value */
|
||||
{336000000, 100000000, 100, 21, 16, 11},
|
||||
{312000000, 100000000, 200, 26, 24, 13},
|
||||
{12000000, 100000000, 200, 1, 24, 13},
|
||||
{0, 0, 0, 0, 0, 0},
|
||||
{ 336000000, 100000000, 100, 21, 16, 11 },
|
||||
{ 312000000, 100000000, 200, 26, 24, 13 },
|
||||
{ 12000000, 100000000, 200, 1, 24, 13 },
|
||||
{ 0, 0, 0, 0, 0, 0 },
|
||||
};
|
||||
|
||||
static const struct pdiv_map plle_p[] = {
|
||||
{ .pdiv = 1, .hw_val = 0 },
|
||||
{ .pdiv = 2, .hw_val = 1 },
|
||||
{ .pdiv = 3, .hw_val = 2 },
|
||||
{ .pdiv = 4, .hw_val = 3 },
|
||||
{ .pdiv = 5, .hw_val = 4 },
|
||||
{ .pdiv = 6, .hw_val = 5 },
|
||||
{ .pdiv = 8, .hw_val = 6 },
|
||||
{ .pdiv = 10, .hw_val = 7 },
|
||||
{ .pdiv = 12, .hw_val = 8 },
|
||||
{ .pdiv = 16, .hw_val = 9 },
|
||||
{ .pdiv = 12, .hw_val = 10 },
|
||||
{ .pdiv = 16, .hw_val = 11 },
|
||||
{ .pdiv = 20, .hw_val = 12 },
|
||||
{ .pdiv = 24, .hw_val = 13 },
|
||||
{ .pdiv = 32, .hw_val = 14 },
|
||||
{ .pdiv = 0, .hw_val = 0 }
|
||||
};
|
||||
|
||||
static struct div_nmp plle_nmp = {
|
||||
|
|
@ -584,9 +601,10 @@ static struct tegra_clk_pll_params pll_e_params = {
|
|||
.lock_mask = PLLE_MISC_LOCK,
|
||||
.lock_enable_bit_idx = PLLE_MISC_LOCK_ENABLE,
|
||||
.lock_delay = 300,
|
||||
.pdiv_tohw = plle_p,
|
||||
.div_nmp = &plle_nmp,
|
||||
.freq_table = pll_e_freq_table,
|
||||
.flags = TEGRA_PLL_FIXED,
|
||||
.flags = TEGRA_PLL_FIXED | TEGRA_PLL_HAS_LOCK_ENABLE,
|
||||
.fixed_rate = 100000000,
|
||||
};
|
||||
|
||||
|
|
@ -614,18 +632,19 @@ static struct tegra_clk_pll_params pll_re_vco_params = {
|
|||
.iddq_reg = PLLRE_MISC,
|
||||
.iddq_bit_idx = PLLRE_IDDQ_BIT,
|
||||
.div_nmp = &pllre_nmp,
|
||||
.flags = TEGRA_PLL_USE_LOCK,
|
||||
.flags = TEGRA_PLL_USE_LOCK | TEGRA_PLL_HAS_LOCK_ENABLE |
|
||||
TEGRA_PLL_LOCK_MISC,
|
||||
};
|
||||
|
||||
/* possible OSC frequencies in Hz */
|
||||
static unsigned long tegra114_input_freq[] = {
|
||||
[0] = 13000000,
|
||||
[1] = 16800000,
|
||||
[4] = 19200000,
|
||||
[5] = 38400000,
|
||||
[8] = 12000000,
|
||||
[9] = 48000000,
|
||||
[12] = 260000000,
|
||||
[ 0] = 13000000,
|
||||
[ 1] = 16800000,
|
||||
[ 4] = 19200000,
|
||||
[ 5] = 38400000,
|
||||
[ 8] = 12000000,
|
||||
[ 9] = 48000000,
|
||||
[12] = 26000000,
|
||||
};
|
||||
|
||||
#define MASK(x) (BIT(x) - 1)
|
||||
|
|
@ -644,21 +663,27 @@ struct utmi_clk_param {
|
|||
};
|
||||
|
||||
static const struct utmi_clk_param utmi_parameters[] = {
|
||||
{.osc_frequency = 13000000, .enable_delay_count = 0x02,
|
||||
.stable_count = 0x33, .active_delay_count = 0x05,
|
||||
.xtal_freq_count = 0x7F},
|
||||
{.osc_frequency = 19200000, .enable_delay_count = 0x03,
|
||||
.stable_count = 0x4B, .active_delay_count = 0x06,
|
||||
.xtal_freq_count = 0xBB},
|
||||
{.osc_frequency = 12000000, .enable_delay_count = 0x02,
|
||||
.stable_count = 0x2F, .active_delay_count = 0x04,
|
||||
.xtal_freq_count = 0x76},
|
||||
{.osc_frequency = 26000000, .enable_delay_count = 0x04,
|
||||
.stable_count = 0x66, .active_delay_count = 0x09,
|
||||
.xtal_freq_count = 0xFE},
|
||||
{.osc_frequency = 16800000, .enable_delay_count = 0x03,
|
||||
.stable_count = 0x41, .active_delay_count = 0x0A,
|
||||
.xtal_freq_count = 0xA4},
|
||||
{
|
||||
.osc_frequency = 13000000, .enable_delay_count = 0x02,
|
||||
.stable_count = 0x33, .active_delay_count = 0x05,
|
||||
.xtal_freq_count = 0x7f
|
||||
}, {
|
||||
.osc_frequency = 19200000, .enable_delay_count = 0x03,
|
||||
.stable_count = 0x4b, .active_delay_count = 0x06,
|
||||
.xtal_freq_count = 0xbb
|
||||
}, {
|
||||
.osc_frequency = 12000000, .enable_delay_count = 0x02,
|
||||
.stable_count = 0x2f, .active_delay_count = 0x04,
|
||||
.xtal_freq_count = 0x76
|
||||
}, {
|
||||
.osc_frequency = 26000000, .enable_delay_count = 0x04,
|
||||
.stable_count = 0x66, .active_delay_count = 0x09,
|
||||
.xtal_freq_count = 0xfe
|
||||
}, {
|
||||
.osc_frequency = 16800000, .enable_delay_count = 0x03,
|
||||
.stable_count = 0x41, .active_delay_count = 0x0a,
|
||||
.xtal_freq_count = 0xa4
|
||||
},
|
||||
};
|
||||
|
||||
/* peripheral mux definitions */
|
||||
|
|
@ -965,8 +990,8 @@ static void __init tegra114_fixed_clk_init(void __iomem *clk_base)
|
|||
|
||||
static __init void tegra114_utmi_param_configure(void __iomem *clk_base)
|
||||
{
|
||||
unsigned int i;
|
||||
u32 reg;
|
||||
int i;
|
||||
|
||||
for (i = 0; i < ARRAY_SIZE(utmi_parameters); i++) {
|
||||
if (osc_freq == utmi_parameters[i].osc_frequency)
|
||||
|
|
@ -1173,7 +1198,7 @@ static __init void tegra114_periph_clk_init(void __iomem *clk_base,
|
|||
{
|
||||
struct clk *clk;
|
||||
struct tegra_periph_init_data *data;
|
||||
int i;
|
||||
unsigned int i;
|
||||
|
||||
/* xusb_ss_div2 */
|
||||
clk = clk_register_fixed_factor(NULL, "xusb_ss_div2", "xusb_ss_src", 0,
|
||||
|
|
@ -1278,7 +1303,7 @@ static struct tegra_cpu_car_ops tegra114_cpu_car_ops = {
|
|||
|
||||
static const struct of_device_id pmc_match[] __initconst = {
|
||||
{ .compatible = "nvidia,tegra114-pmc" },
|
||||
{},
|
||||
{ },
|
||||
};
|
||||
|
||||
/*
|
||||
|
|
@ -1286,37 +1311,37 @@ static const struct of_device_id pmc_match[] __initconst = {
|
|||
* breaks
|
||||
*/
|
||||
static struct tegra_clk_init_table init_table[] __initdata = {
|
||||
{TEGRA114_CLK_UARTA, TEGRA114_CLK_PLL_P, 408000000, 0},
|
||||
{TEGRA114_CLK_UARTB, TEGRA114_CLK_PLL_P, 408000000, 0},
|
||||
{TEGRA114_CLK_UARTC, TEGRA114_CLK_PLL_P, 408000000, 0},
|
||||
{TEGRA114_CLK_UARTD, TEGRA114_CLK_PLL_P, 408000000, 0},
|
||||
{TEGRA114_CLK_PLL_A, TEGRA114_CLK_CLK_MAX, 564480000, 1},
|
||||
{TEGRA114_CLK_PLL_A_OUT0, TEGRA114_CLK_CLK_MAX, 11289600, 1},
|
||||
{TEGRA114_CLK_EXTERN1, TEGRA114_CLK_PLL_A_OUT0, 0, 1},
|
||||
{TEGRA114_CLK_CLK_OUT_1_MUX, TEGRA114_CLK_EXTERN1, 0, 1},
|
||||
{TEGRA114_CLK_CLK_OUT_1, TEGRA114_CLK_CLK_MAX, 0, 1},
|
||||
{TEGRA114_CLK_I2S0, TEGRA114_CLK_PLL_A_OUT0, 11289600, 0},
|
||||
{TEGRA114_CLK_I2S1, TEGRA114_CLK_PLL_A_OUT0, 11289600, 0},
|
||||
{TEGRA114_CLK_I2S2, TEGRA114_CLK_PLL_A_OUT0, 11289600, 0},
|
||||
{TEGRA114_CLK_I2S3, TEGRA114_CLK_PLL_A_OUT0, 11289600, 0},
|
||||
{TEGRA114_CLK_I2S4, TEGRA114_CLK_PLL_A_OUT0, 11289600, 0},
|
||||
{TEGRA114_CLK_HOST1X, TEGRA114_CLK_PLL_P, 136000000, 0},
|
||||
{TEGRA114_CLK_DFLL_SOC, TEGRA114_CLK_PLL_P, 51000000, 1},
|
||||
{TEGRA114_CLK_DFLL_REF, TEGRA114_CLK_PLL_P, 51000000, 1},
|
||||
{TEGRA114_CLK_DISP1, TEGRA114_CLK_PLL_P, 0, 0},
|
||||
{TEGRA114_CLK_DISP2, TEGRA114_CLK_PLL_P, 0, 0},
|
||||
{TEGRA114_CLK_GR2D, TEGRA114_CLK_PLL_C2, 300000000, 0},
|
||||
{TEGRA114_CLK_GR3D, TEGRA114_CLK_PLL_C2, 300000000, 0},
|
||||
{TEGRA114_CLK_DSIALP, TEGRA114_CLK_PLL_P, 68000000, 0},
|
||||
{TEGRA114_CLK_DSIBLP, TEGRA114_CLK_PLL_P, 68000000, 0},
|
||||
{TEGRA114_CLK_PLL_RE_VCO, TEGRA114_CLK_CLK_MAX, 612000000, 0},
|
||||
{TEGRA114_CLK_XUSB_SS_SRC, TEGRA114_CLK_PLL_RE_OUT, 122400000, 0},
|
||||
{TEGRA114_CLK_XUSB_FS_SRC, TEGRA114_CLK_PLL_U_48M, 48000000, 0},
|
||||
{TEGRA114_CLK_XUSB_HS_SRC, TEGRA114_CLK_XUSB_SS_DIV2, 61200000, 0},
|
||||
{TEGRA114_CLK_XUSB_FALCON_SRC, TEGRA114_CLK_PLL_P, 204000000, 0},
|
||||
{TEGRA114_CLK_XUSB_HOST_SRC, TEGRA114_CLK_PLL_P, 102000000, 0},
|
||||
/* This MUST be the last entry. */
|
||||
{TEGRA114_CLK_CLK_MAX, TEGRA114_CLK_CLK_MAX, 0, 0},
|
||||
{ TEGRA114_CLK_UARTA, TEGRA114_CLK_PLL_P, 408000000, 0 },
|
||||
{ TEGRA114_CLK_UARTB, TEGRA114_CLK_PLL_P, 408000000, 0 },
|
||||
{ TEGRA114_CLK_UARTC, TEGRA114_CLK_PLL_P, 408000000, 0 },
|
||||
{ TEGRA114_CLK_UARTD, TEGRA114_CLK_PLL_P, 408000000, 0 },
|
||||
{ TEGRA114_CLK_PLL_A, TEGRA114_CLK_CLK_MAX, 564480000, 1 },
|
||||
{ TEGRA114_CLK_PLL_A_OUT0, TEGRA114_CLK_CLK_MAX, 11289600, 1 },
|
||||
{ TEGRA114_CLK_EXTERN1, TEGRA114_CLK_PLL_A_OUT0, 0, 1 },
|
||||
{ TEGRA114_CLK_CLK_OUT_1_MUX, TEGRA114_CLK_EXTERN1, 0, 1 },
|
||||
{ TEGRA114_CLK_CLK_OUT_1, TEGRA114_CLK_CLK_MAX, 0, 1 },
|
||||
{ TEGRA114_CLK_I2S0, TEGRA114_CLK_PLL_A_OUT0, 11289600, 0 },
|
||||
{ TEGRA114_CLK_I2S1, TEGRA114_CLK_PLL_A_OUT0, 11289600, 0 },
|
||||
{ TEGRA114_CLK_I2S2, TEGRA114_CLK_PLL_A_OUT0, 11289600, 0 },
|
||||
{ TEGRA114_CLK_I2S3, TEGRA114_CLK_PLL_A_OUT0, 11289600, 0 },
|
||||
{ TEGRA114_CLK_I2S4, TEGRA114_CLK_PLL_A_OUT0, 11289600, 0 },
|
||||
{ TEGRA114_CLK_HOST1X, TEGRA114_CLK_PLL_P, 136000000, 0 },
|
||||
{ TEGRA114_CLK_DFLL_SOC, TEGRA114_CLK_PLL_P, 51000000, 1 },
|
||||
{ TEGRA114_CLK_DFLL_REF, TEGRA114_CLK_PLL_P, 51000000, 1 },
|
||||
{ TEGRA114_CLK_DISP1, TEGRA114_CLK_PLL_P, 0, 0 },
|
||||
{ TEGRA114_CLK_DISP2, TEGRA114_CLK_PLL_P, 0, 0 },
|
||||
{ TEGRA114_CLK_GR2D, TEGRA114_CLK_PLL_C2, 300000000, 0 },
|
||||
{ TEGRA114_CLK_GR3D, TEGRA114_CLK_PLL_C2, 300000000, 0 },
|
||||
{ TEGRA114_CLK_DSIALP, TEGRA114_CLK_PLL_P, 68000000, 0 },
|
||||
{ TEGRA114_CLK_DSIBLP, TEGRA114_CLK_PLL_P, 68000000, 0 },
|
||||
{ TEGRA114_CLK_PLL_RE_VCO, TEGRA114_CLK_CLK_MAX, 612000000, 0 },
|
||||
{ TEGRA114_CLK_XUSB_SS_SRC, TEGRA114_CLK_PLL_RE_OUT, 122400000, 0 },
|
||||
{ TEGRA114_CLK_XUSB_FS_SRC, TEGRA114_CLK_PLL_U_48M, 48000000, 0 },
|
||||
{ TEGRA114_CLK_XUSB_HS_SRC, TEGRA114_CLK_XUSB_SS_DIV2, 61200000, 0 },
|
||||
{ TEGRA114_CLK_XUSB_FALCON_SRC, TEGRA114_CLK_PLL_P, 204000000, 0 },
|
||||
{ TEGRA114_CLK_XUSB_HOST_SRC, TEGRA114_CLK_PLL_P, 102000000, 0 },
|
||||
/* must be the last entry */
|
||||
{ TEGRA114_CLK_CLK_MAX, TEGRA114_CLK_CLK_MAX, 0, 0 },
|
||||
};
|
||||
|
||||
static void __init tegra114_clock_apply_init_table(void)
|
||||
|
|
|
|||
|
|
@ -150,13 +150,13 @@ static DEFINE_SPINLOCK(emc_lock);
|
|||
|
||||
/* possible OSC frequencies in Hz */
|
||||
static unsigned long tegra124_input_freq[] = {
|
||||
[0] = 13000000,
|
||||
[1] = 16800000,
|
||||
[4] = 19200000,
|
||||
[5] = 38400000,
|
||||
[8] = 12000000,
|
||||
[9] = 48000000,
|
||||
[12] = 260000000,
|
||||
[ 0] = 13000000,
|
||||
[ 1] = 16800000,
|
||||
[ 4] = 19200000,
|
||||
[ 5] = 38400000,
|
||||
[ 8] = 12000000,
|
||||
[ 9] = 48000000,
|
||||
[12] = 26000000,
|
||||
};
|
||||
|
||||
static struct div_nmp pllxc_nmp = {
|
||||
|
|
@ -168,33 +168,33 @@ static struct div_nmp pllxc_nmp = {
|
|||
.divp_width = 4,
|
||||
};
|
||||
|
||||
static struct pdiv_map pllxc_p[] = {
|
||||
{ .pdiv = 1, .hw_val = 0 },
|
||||
{ .pdiv = 2, .hw_val = 1 },
|
||||
{ .pdiv = 3, .hw_val = 2 },
|
||||
{ .pdiv = 4, .hw_val = 3 },
|
||||
{ .pdiv = 5, .hw_val = 4 },
|
||||
{ .pdiv = 6, .hw_val = 5 },
|
||||
{ .pdiv = 8, .hw_val = 6 },
|
||||
{ .pdiv = 10, .hw_val = 7 },
|
||||
{ .pdiv = 12, .hw_val = 8 },
|
||||
{ .pdiv = 16, .hw_val = 9 },
|
||||
static const struct pdiv_map pllxc_p[] = {
|
||||
{ .pdiv = 1, .hw_val = 0 },
|
||||
{ .pdiv = 2, .hw_val = 1 },
|
||||
{ .pdiv = 3, .hw_val = 2 },
|
||||
{ .pdiv = 4, .hw_val = 3 },
|
||||
{ .pdiv = 5, .hw_val = 4 },
|
||||
{ .pdiv = 6, .hw_val = 5 },
|
||||
{ .pdiv = 8, .hw_val = 6 },
|
||||
{ .pdiv = 10, .hw_val = 7 },
|
||||
{ .pdiv = 12, .hw_val = 8 },
|
||||
{ .pdiv = 16, .hw_val = 9 },
|
||||
{ .pdiv = 12, .hw_val = 10 },
|
||||
{ .pdiv = 16, .hw_val = 11 },
|
||||
{ .pdiv = 20, .hw_val = 12 },
|
||||
{ .pdiv = 24, .hw_val = 13 },
|
||||
{ .pdiv = 32, .hw_val = 14 },
|
||||
{ .pdiv = 0, .hw_val = 0 },
|
||||
{ .pdiv = 0, .hw_val = 0 },
|
||||
};
|
||||
|
||||
static struct tegra_clk_pll_freq_table pll_x_freq_table[] = {
|
||||
/* 1 GHz */
|
||||
{12000000, 1000000000, 83, 0, 1}, /* actual: 996.0 MHz */
|
||||
{13000000, 1000000000, 76, 0, 1}, /* actual: 988.0 MHz */
|
||||
{16800000, 1000000000, 59, 0, 1}, /* actual: 991.2 MHz */
|
||||
{19200000, 1000000000, 52, 0, 1}, /* actual: 998.4 MHz */
|
||||
{26000000, 1000000000, 76, 1, 1}, /* actual: 988.0 MHz */
|
||||
{0, 0, 0, 0, 0, 0},
|
||||
{ 12000000, 1000000000, 83, 1, 1, 0 }, /* actual: 996.0 MHz */
|
||||
{ 13000000, 1000000000, 76, 1, 1, 0 }, /* actual: 988.0 MHz */
|
||||
{ 16800000, 1000000000, 59, 1, 1, 0 }, /* actual: 991.2 MHz */
|
||||
{ 19200000, 1000000000, 52, 1, 1, 0 }, /* actual: 998.4 MHz */
|
||||
{ 26000000, 1000000000, 76, 2, 1, 0 }, /* actual: 988.0 MHz */
|
||||
{ 0, 0, 0, 0, 0, 0 },
|
||||
};
|
||||
|
||||
static struct tegra_clk_pll_params pll_x_params = {
|
||||
|
|
@ -218,24 +218,24 @@ static struct tegra_clk_pll_params pll_x_params = {
|
|||
.pdiv_tohw = pllxc_p,
|
||||
.div_nmp = &pllxc_nmp,
|
||||
.freq_table = pll_x_freq_table,
|
||||
.flags = TEGRA_PLL_USE_LOCK,
|
||||
.flags = TEGRA_PLL_USE_LOCK | TEGRA_PLL_HAS_LOCK_ENABLE,
|
||||
};
|
||||
|
||||
static struct tegra_clk_pll_freq_table pll_c_freq_table[] = {
|
||||
{ 12000000, 624000000, 104, 1, 2},
|
||||
{ 12000000, 600000000, 100, 1, 2},
|
||||
{ 13000000, 600000000, 92, 1, 2}, /* actual: 598.0 MHz */
|
||||
{ 16800000, 600000000, 71, 1, 2}, /* actual: 596.4 MHz */
|
||||
{ 19200000, 600000000, 62, 1, 2}, /* actual: 595.2 MHz */
|
||||
{ 26000000, 600000000, 92, 2, 2}, /* actual: 598.0 MHz */
|
||||
{ 0, 0, 0, 0, 0, 0 },
|
||||
{ 12000000, 624000000, 104, 1, 2, 0 },
|
||||
{ 12000000, 600000000, 100, 1, 2, 0 },
|
||||
{ 13000000, 600000000, 92, 1, 2, 0 }, /* actual: 598.0 MHz */
|
||||
{ 16800000, 600000000, 71, 1, 2, 0 }, /* actual: 596.4 MHz */
|
||||
{ 19200000, 600000000, 62, 1, 2, 0 }, /* actual: 595.2 MHz */
|
||||
{ 26000000, 600000000, 92, 2, 2, 0 }, /* actual: 598.0 MHz */
|
||||
{ 0, 0, 0, 0, 0, 0 },
|
||||
};
|
||||
|
||||
static struct tegra_clk_pll_params pll_c_params = {
|
||||
.input_min = 12000000,
|
||||
.input_max = 800000000,
|
||||
.cf_min = 12000000,
|
||||
.cf_max = 19200000, /* s/w policy, h/w capability 50 MHz */
|
||||
.cf_max = 19200000, /* s/w policy, h/w capability 50 MHz */
|
||||
.vco_min = 600000000,
|
||||
.vco_max = 1400000000,
|
||||
.base_reg = PLLC_BASE,
|
||||
|
|
@ -252,7 +252,7 @@ static struct tegra_clk_pll_params pll_c_params = {
|
|||
.pdiv_tohw = pllxc_p,
|
||||
.div_nmp = &pllxc_nmp,
|
||||
.freq_table = pll_c_freq_table,
|
||||
.flags = TEGRA_PLL_USE_LOCK,
|
||||
.flags = TEGRA_PLL_USE_LOCK | TEGRA_PLL_HAS_LOCK_ENABLE,
|
||||
};
|
||||
|
||||
static struct div_nmp pllcx_nmp = {
|
||||
|
|
@ -264,25 +264,25 @@ static struct div_nmp pllcx_nmp = {
|
|||
.divp_width = 3,
|
||||
};
|
||||
|
||||
static struct pdiv_map pllc_p[] = {
|
||||
{ .pdiv = 1, .hw_val = 0 },
|
||||
{ .pdiv = 2, .hw_val = 1 },
|
||||
{ .pdiv = 3, .hw_val = 2 },
|
||||
{ .pdiv = 4, .hw_val = 3 },
|
||||
{ .pdiv = 6, .hw_val = 4 },
|
||||
{ .pdiv = 8, .hw_val = 5 },
|
||||
static const struct pdiv_map pllc_p[] = {
|
||||
{ .pdiv = 1, .hw_val = 0 },
|
||||
{ .pdiv = 2, .hw_val = 1 },
|
||||
{ .pdiv = 3, .hw_val = 2 },
|
||||
{ .pdiv = 4, .hw_val = 3 },
|
||||
{ .pdiv = 6, .hw_val = 4 },
|
||||
{ .pdiv = 8, .hw_val = 5 },
|
||||
{ .pdiv = 12, .hw_val = 6 },
|
||||
{ .pdiv = 16, .hw_val = 7 },
|
||||
{ .pdiv = 0, .hw_val = 0 },
|
||||
{ .pdiv = 0, .hw_val = 0 },
|
||||
};
|
||||
|
||||
static struct tegra_clk_pll_freq_table pll_cx_freq_table[] = {
|
||||
{12000000, 600000000, 100, 1, 2},
|
||||
{13000000, 600000000, 92, 1, 2}, /* actual: 598.0 MHz */
|
||||
{16800000, 600000000, 71, 1, 2}, /* actual: 596.4 MHz */
|
||||
{19200000, 600000000, 62, 1, 2}, /* actual: 595.2 MHz */
|
||||
{26000000, 600000000, 92, 2, 2}, /* actual: 598.0 MHz */
|
||||
{0, 0, 0, 0, 0, 0},
|
||||
{ 12000000, 600000000, 100, 1, 2, 0 },
|
||||
{ 13000000, 600000000, 92, 1, 2, 0 }, /* actual: 598.0 MHz */
|
||||
{ 16800000, 600000000, 71, 1, 2, 0 }, /* actual: 596.4 MHz */
|
||||
{ 19200000, 600000000, 62, 1, 2, 0 }, /* actual: 595.2 MHz */
|
||||
{ 26000000, 600000000, 92, 2, 2, 0 }, /* actual: 598.0 MHz */
|
||||
{ 0, 0, 0, 0, 0, 0 },
|
||||
};
|
||||
|
||||
static struct tegra_clk_pll_params pll_c2_params = {
|
||||
|
|
@ -338,32 +338,32 @@ static struct div_nmp pllss_nmp = {
|
|||
.divp_width = 4,
|
||||
};
|
||||
|
||||
static struct pdiv_map pll12g_ssd_esd_p[] = {
|
||||
{ .pdiv = 1, .hw_val = 0 },
|
||||
{ .pdiv = 2, .hw_val = 1 },
|
||||
{ .pdiv = 3, .hw_val = 2 },
|
||||
{ .pdiv = 4, .hw_val = 3 },
|
||||
{ .pdiv = 5, .hw_val = 4 },
|
||||
{ .pdiv = 6, .hw_val = 5 },
|
||||
{ .pdiv = 8, .hw_val = 6 },
|
||||
{ .pdiv = 10, .hw_val = 7 },
|
||||
{ .pdiv = 12, .hw_val = 8 },
|
||||
{ .pdiv = 16, .hw_val = 9 },
|
||||
static const struct pdiv_map pll12g_ssd_esd_p[] = {
|
||||
{ .pdiv = 1, .hw_val = 0 },
|
||||
{ .pdiv = 2, .hw_val = 1 },
|
||||
{ .pdiv = 3, .hw_val = 2 },
|
||||
{ .pdiv = 4, .hw_val = 3 },
|
||||
{ .pdiv = 5, .hw_val = 4 },
|
||||
{ .pdiv = 6, .hw_val = 5 },
|
||||
{ .pdiv = 8, .hw_val = 6 },
|
||||
{ .pdiv = 10, .hw_val = 7 },
|
||||
{ .pdiv = 12, .hw_val = 8 },
|
||||
{ .pdiv = 16, .hw_val = 9 },
|
||||
{ .pdiv = 12, .hw_val = 10 },
|
||||
{ .pdiv = 16, .hw_val = 11 },
|
||||
{ .pdiv = 20, .hw_val = 12 },
|
||||
{ .pdiv = 24, .hw_val = 13 },
|
||||
{ .pdiv = 32, .hw_val = 14 },
|
||||
{ .pdiv = 0, .hw_val = 0 },
|
||||
{ .pdiv = 0, .hw_val = 0 },
|
||||
};
|
||||
|
||||
static struct tegra_clk_pll_freq_table pll_c4_freq_table[] = {
|
||||
{ 12000000, 600000000, 100, 1, 1},
|
||||
{ 13000000, 600000000, 92, 1, 1}, /* actual: 598.0 MHz */
|
||||
{ 16800000, 600000000, 71, 1, 1}, /* actual: 596.4 MHz */
|
||||
{ 19200000, 600000000, 62, 1, 1}, /* actual: 595.2 MHz */
|
||||
{ 26000000, 600000000, 92, 2, 1}, /* actual: 598.0 MHz */
|
||||
{ 0, 0, 0, 0, 0, 0 },
|
||||
{ 12000000, 600000000, 100, 1, 2, 0 },
|
||||
{ 13000000, 600000000, 92, 1, 2, 0 }, /* actual: 598.0 MHz */
|
||||
{ 16800000, 600000000, 71, 1, 2, 0 }, /* actual: 596.4 MHz */
|
||||
{ 19200000, 600000000, 62, 1, 2, 0 }, /* actual: 595.2 MHz */
|
||||
{ 26000000, 600000000, 92, 2, 2, 0 }, /* actual: 598.0 MHz */
|
||||
{ 0, 0, 0, 0, 0, 0 },
|
||||
};
|
||||
|
||||
static struct tegra_clk_pll_params pll_c4_params = {
|
||||
|
|
@ -386,21 +386,35 @@ static struct tegra_clk_pll_params pll_c4_params = {
|
|||
.ext_misc_reg[1] = 0x5b0,
|
||||
.ext_misc_reg[2] = 0x5b4,
|
||||
.freq_table = pll_c4_freq_table,
|
||||
.flags = TEGRA_PLL_USE_LOCK | TEGRA_PLL_HAS_LOCK_ENABLE,
|
||||
};
|
||||
|
||||
static struct pdiv_map pllm_p[] = {
|
||||
{ .pdiv = 1, .hw_val = 0 },
|
||||
{ .pdiv = 2, .hw_val = 1 },
|
||||
{ .pdiv = 0, .hw_val = 0 },
|
||||
static const struct pdiv_map pllm_p[] = {
|
||||
{ .pdiv = 1, .hw_val = 0 },
|
||||
{ .pdiv = 2, .hw_val = 1 },
|
||||
{ .pdiv = 3, .hw_val = 2 },
|
||||
{ .pdiv = 4, .hw_val = 3 },
|
||||
{ .pdiv = 5, .hw_val = 4 },
|
||||
{ .pdiv = 6, .hw_val = 5 },
|
||||
{ .pdiv = 8, .hw_val = 6 },
|
||||
{ .pdiv = 10, .hw_val = 7 },
|
||||
{ .pdiv = 12, .hw_val = 8 },
|
||||
{ .pdiv = 16, .hw_val = 9 },
|
||||
{ .pdiv = 12, .hw_val = 10 },
|
||||
{ .pdiv = 16, .hw_val = 11 },
|
||||
{ .pdiv = 20, .hw_val = 12 },
|
||||
{ .pdiv = 24, .hw_val = 13 },
|
||||
{ .pdiv = 32, .hw_val = 14 },
|
||||
{ .pdiv = 0, .hw_val = 0 },
|
||||
};
|
||||
|
||||
static struct tegra_clk_pll_freq_table pll_m_freq_table[] = {
|
||||
{12000000, 800000000, 66, 1, 1}, /* actual: 792.0 MHz */
|
||||
{13000000, 800000000, 61, 1, 1}, /* actual: 793.0 MHz */
|
||||
{16800000, 800000000, 47, 1, 1}, /* actual: 789.6 MHz */
|
||||
{19200000, 800000000, 41, 1, 1}, /* actual: 787.2 MHz */
|
||||
{26000000, 800000000, 61, 2, 1}, /* actual: 793.0 MHz */
|
||||
{0, 0, 0, 0, 0, 0},
|
||||
{ 12000000, 800000000, 66, 1, 1, 0 }, /* actual: 792.0 MHz */
|
||||
{ 13000000, 800000000, 61, 1, 1, 0 }, /* actual: 793.0 MHz */
|
||||
{ 16800000, 800000000, 47, 1, 1, 0 }, /* actual: 789.6 MHz */
|
||||
{ 19200000, 800000000, 41, 1, 1, 0 }, /* actual: 787.2 MHz */
|
||||
{ 26000000, 800000000, 61, 2, 1, 0 }, /* actual: 793.0 MHz */
|
||||
{ 0, 0, 0, 0, 0, 0},
|
||||
};
|
||||
|
||||
static struct div_nmp pllm_nmp = {
|
||||
|
|
@ -427,22 +441,41 @@ static struct tegra_clk_pll_params pll_m_params = {
|
|||
.lock_mask = PLL_BASE_LOCK,
|
||||
.lock_enable_bit_idx = PLL_MISC_LOCK_ENABLE,
|
||||
.lock_delay = 300,
|
||||
.max_p = 2,
|
||||
.max_p = 5,
|
||||
.pdiv_tohw = pllm_p,
|
||||
.div_nmp = &pllm_nmp,
|
||||
.pmc_divnm_reg = PMC_PLLM_WB0_OVERRIDE,
|
||||
.pmc_divp_reg = PMC_PLLM_WB0_OVERRIDE_2,
|
||||
.freq_table = pll_m_freq_table,
|
||||
.flags = TEGRA_PLL_USE_LOCK,
|
||||
.flags = TEGRA_PLL_USE_LOCK | TEGRA_PLL_HAS_LOCK_ENABLE,
|
||||
};
|
||||
|
||||
static struct tegra_clk_pll_freq_table pll_e_freq_table[] = {
|
||||
/* PLLE special case: use cpcon field to store cml divider value */
|
||||
{336000000, 100000000, 100, 21, 16, 11},
|
||||
{312000000, 100000000, 200, 26, 24, 13},
|
||||
{13000000, 100000000, 200, 1, 26, 13},
|
||||
{12000000, 100000000, 200, 1, 24, 13},
|
||||
{0, 0, 0, 0, 0, 0},
|
||||
{ 336000000, 100000000, 100, 21, 16, 11 },
|
||||
{ 312000000, 100000000, 200, 26, 24, 13 },
|
||||
{ 13000000, 100000000, 200, 1, 26, 13 },
|
||||
{ 12000000, 100000000, 200, 1, 24, 13 },
|
||||
{ 0, 0, 0, 0, 0, 0 },
|
||||
};
|
||||
|
||||
static const struct pdiv_map plle_p[] = {
|
||||
{ .pdiv = 1, .hw_val = 0 },
|
||||
{ .pdiv = 2, .hw_val = 1 },
|
||||
{ .pdiv = 3, .hw_val = 2 },
|
||||
{ .pdiv = 4, .hw_val = 3 },
|
||||
{ .pdiv = 5, .hw_val = 4 },
|
||||
{ .pdiv = 6, .hw_val = 5 },
|
||||
{ .pdiv = 8, .hw_val = 6 },
|
||||
{ .pdiv = 10, .hw_val = 7 },
|
||||
{ .pdiv = 12, .hw_val = 8 },
|
||||
{ .pdiv = 16, .hw_val = 9 },
|
||||
{ .pdiv = 12, .hw_val = 10 },
|
||||
{ .pdiv = 16, .hw_val = 11 },
|
||||
{ .pdiv = 20, .hw_val = 12 },
|
||||
{ .pdiv = 24, .hw_val = 13 },
|
||||
{ .pdiv = 32, .hw_val = 14 },
|
||||
{ .pdiv = 1, .hw_val = 0 },
|
||||
};
|
||||
|
||||
static struct div_nmp plle_nmp = {
|
||||
|
|
@ -467,9 +500,10 @@ static struct tegra_clk_pll_params pll_e_params = {
|
|||
.lock_mask = PLLE_MISC_LOCK,
|
||||
.lock_enable_bit_idx = PLLE_MISC_LOCK_ENABLE,
|
||||
.lock_delay = 300,
|
||||
.pdiv_tohw = plle_p,
|
||||
.div_nmp = &plle_nmp,
|
||||
.freq_table = pll_e_freq_table,
|
||||
.flags = TEGRA_PLL_FIXED,
|
||||
.flags = TEGRA_PLL_FIXED | TEGRA_PLL_HAS_LOCK_ENABLE,
|
||||
.fixed_rate = 100000000,
|
||||
};
|
||||
|
||||
|
|
@ -507,7 +541,8 @@ static struct tegra_clk_pll_params pll_re_vco_params = {
|
|||
.iddq_reg = PLLRE_MISC,
|
||||
.iddq_bit_idx = PLLRE_IDDQ_BIT,
|
||||
.div_nmp = &pllre_nmp,
|
||||
.flags = TEGRA_PLL_USE_LOCK,
|
||||
.flags = TEGRA_PLL_USE_LOCK | TEGRA_PLL_HAS_LOCK_ENABLE |
|
||||
TEGRA_PLL_LOCK_MISC,
|
||||
};
|
||||
|
||||
static struct div_nmp pllp_nmp = {
|
||||
|
|
@ -520,12 +555,12 @@ static struct div_nmp pllp_nmp = {
|
|||
};
|
||||
|
||||
static struct tegra_clk_pll_freq_table pll_p_freq_table[] = {
|
||||
{12000000, 408000000, 408, 12, 0, 8},
|
||||
{13000000, 408000000, 408, 13, 0, 8},
|
||||
{16800000, 408000000, 340, 14, 0, 8},
|
||||
{19200000, 408000000, 340, 16, 0, 8},
|
||||
{26000000, 408000000, 408, 26, 0, 8},
|
||||
{0, 0, 0, 0, 0, 0},
|
||||
{ 12000000, 408000000, 408, 12, 1, 8 },
|
||||
{ 13000000, 408000000, 408, 13, 1, 8 },
|
||||
{ 16800000, 408000000, 340, 14, 1, 8 },
|
||||
{ 19200000, 408000000, 340, 16, 1, 8 },
|
||||
{ 26000000, 408000000, 408, 26, 1, 8 },
|
||||
{ 0, 0, 0, 0, 0, 0 },
|
||||
};
|
||||
|
||||
static struct tegra_clk_pll_params pll_p_params = {
|
||||
|
|
@ -543,18 +578,18 @@ static struct tegra_clk_pll_params pll_p_params = {
|
|||
.div_nmp = &pllp_nmp,
|
||||
.freq_table = pll_p_freq_table,
|
||||
.fixed_rate = 408000000,
|
||||
.flags = TEGRA_PLL_FIXED | TEGRA_PLL_USE_LOCK,
|
||||
.flags = TEGRA_PLL_FIXED | TEGRA_PLL_USE_LOCK |
|
||||
TEGRA_PLL_HAS_LOCK_ENABLE,
|
||||
};
|
||||
|
||||
static struct tegra_clk_pll_freq_table pll_a_freq_table[] = {
|
||||
{9600000, 282240000, 147, 5, 0, 4},
|
||||
{9600000, 368640000, 192, 5, 0, 4},
|
||||
{9600000, 240000000, 200, 8, 0, 8},
|
||||
|
||||
{28800000, 282240000, 245, 25, 0, 8},
|
||||
{28800000, 368640000, 320, 25, 0, 8},
|
||||
{28800000, 240000000, 200, 24, 0, 8},
|
||||
{0, 0, 0, 0, 0, 0},
|
||||
{ 9600000, 282240000, 147, 5, 1, 4 },
|
||||
{ 9600000, 368640000, 192, 5, 1, 4 },
|
||||
{ 9600000, 240000000, 200, 8, 1, 8 },
|
||||
{ 28800000, 282240000, 245, 25, 1, 8 },
|
||||
{ 28800000, 368640000, 320, 25, 1, 8 },
|
||||
{ 28800000, 240000000, 200, 24, 1, 8 },
|
||||
{ 0, 0, 0, 0, 0, 0 },
|
||||
};
|
||||
|
||||
static struct tegra_clk_pll_params pll_a_params = {
|
||||
|
|
@ -571,7 +606,8 @@ static struct tegra_clk_pll_params pll_a_params = {
|
|||
.lock_delay = 300,
|
||||
.div_nmp = &pllp_nmp,
|
||||
.freq_table = pll_a_freq_table,
|
||||
.flags = TEGRA_PLL_HAS_CPCON | TEGRA_PLL_USE_LOCK,
|
||||
.flags = TEGRA_PLL_HAS_CPCON | TEGRA_PLL_USE_LOCK |
|
||||
TEGRA_PLL_HAS_LOCK_ENABLE,
|
||||
};
|
||||
|
||||
static struct div_nmp plld_nmp = {
|
||||
|
|
@ -584,24 +620,21 @@ static struct div_nmp plld_nmp = {
|
|||
};
|
||||
|
||||
static struct tegra_clk_pll_freq_table pll_d_freq_table[] = {
|
||||
{12000000, 216000000, 864, 12, 4, 12},
|
||||
{13000000, 216000000, 864, 13, 4, 12},
|
||||
{16800000, 216000000, 720, 14, 4, 12},
|
||||
{19200000, 216000000, 720, 16, 4, 12},
|
||||
{26000000, 216000000, 864, 26, 4, 12},
|
||||
|
||||
{12000000, 594000000, 594, 12, 1, 12},
|
||||
{13000000, 594000000, 594, 13, 1, 12},
|
||||
{16800000, 594000000, 495, 14, 1, 12},
|
||||
{19200000, 594000000, 495, 16, 1, 12},
|
||||
{26000000, 594000000, 594, 26, 1, 12},
|
||||
|
||||
{12000000, 1000000000, 1000, 12, 1, 12},
|
||||
{13000000, 1000000000, 1000, 13, 1, 12},
|
||||
{19200000, 1000000000, 625, 12, 1, 12},
|
||||
{26000000, 1000000000, 1000, 26, 1, 12},
|
||||
|
||||
{0, 0, 0, 0, 0, 0},
|
||||
{ 12000000, 216000000, 864, 12, 4, 12 },
|
||||
{ 13000000, 216000000, 864, 13, 4, 12 },
|
||||
{ 16800000, 216000000, 720, 14, 4, 12 },
|
||||
{ 19200000, 216000000, 720, 16, 4, 12 },
|
||||
{ 26000000, 216000000, 864, 26, 4, 12 },
|
||||
{ 12000000, 594000000, 594, 12, 1, 12 },
|
||||
{ 13000000, 594000000, 594, 13, 1, 12 },
|
||||
{ 16800000, 594000000, 495, 14, 1, 12 },
|
||||
{ 19200000, 594000000, 495, 16, 1, 12 },
|
||||
{ 26000000, 594000000, 594, 26, 1, 12 },
|
||||
{ 12000000, 1000000000, 1000, 12, 1, 12 },
|
||||
{ 13000000, 1000000000, 1000, 13, 1, 12 },
|
||||
{ 19200000, 1000000000, 625, 12, 1, 12 },
|
||||
{ 26000000, 1000000000, 1000, 26, 1, 12 },
|
||||
{ 0, 0, 0, 0, 0, 0 },
|
||||
};
|
||||
|
||||
static struct tegra_clk_pll_params pll_d_params = {
|
||||
|
|
@ -619,16 +652,16 @@ static struct tegra_clk_pll_params pll_d_params = {
|
|||
.div_nmp = &plld_nmp,
|
||||
.freq_table = pll_d_freq_table,
|
||||
.flags = TEGRA_PLL_HAS_CPCON | TEGRA_PLL_SET_LFCON |
|
||||
TEGRA_PLL_USE_LOCK,
|
||||
TEGRA_PLL_USE_LOCK | TEGRA_PLL_HAS_LOCK_ENABLE,
|
||||
};
|
||||
|
||||
static struct tegra_clk_pll_freq_table tegra124_pll_d2_freq_table[] = {
|
||||
{ 12000000, 594000000, 99, 1, 2},
|
||||
{ 13000000, 594000000, 91, 1, 2}, /* actual: 591.5 MHz */
|
||||
{ 16800000, 594000000, 71, 1, 2}, /* actual: 596.4 MHz */
|
||||
{ 19200000, 594000000, 62, 1, 2}, /* actual: 595.2 MHz */
|
||||
{ 26000000, 594000000, 91, 2, 2}, /* actual: 591.5 MHz */
|
||||
{ 0, 0, 0, 0, 0, 0 },
|
||||
{ 12000000, 594000000, 99, 1, 2, 0 },
|
||||
{ 13000000, 594000000, 91, 1, 2, 0 }, /* actual: 591.5 MHz */
|
||||
{ 16800000, 594000000, 71, 1, 2, 0 }, /* actual: 596.4 MHz */
|
||||
{ 19200000, 594000000, 62, 1, 2, 0 }, /* actual: 595.2 MHz */
|
||||
{ 26000000, 594000000, 91, 2, 2, 0 }, /* actual: 591.5 MHz */
|
||||
{ 0, 0, 0, 0, 0, 0 },
|
||||
};
|
||||
|
||||
static struct tegra_clk_pll_params tegra124_pll_d2_params = {
|
||||
|
|
@ -652,15 +685,16 @@ static struct tegra_clk_pll_params tegra124_pll_d2_params = {
|
|||
.ext_misc_reg[2] = 0x578,
|
||||
.max_p = 15,
|
||||
.freq_table = tegra124_pll_d2_freq_table,
|
||||
.flags = TEGRA_PLL_USE_LOCK | TEGRA_PLL_HAS_LOCK_ENABLE,
|
||||
};
|
||||
|
||||
static struct tegra_clk_pll_freq_table pll_dp_freq_table[] = {
|
||||
{ 12000000, 600000000, 100, 1, 1},
|
||||
{ 13000000, 600000000, 92, 1, 1}, /* actual: 598.0 MHz */
|
||||
{ 16800000, 600000000, 71, 1, 1}, /* actual: 596.4 MHz */
|
||||
{ 19200000, 600000000, 62, 1, 1}, /* actual: 595.2 MHz */
|
||||
{ 26000000, 600000000, 92, 2, 1}, /* actual: 598.0 MHz */
|
||||
{ 0, 0, 0, 0, 0, 0 },
|
||||
{ 12000000, 600000000, 100, 1, 2, 0 },
|
||||
{ 13000000, 600000000, 92, 1, 2, 0 }, /* actual: 598.0 MHz */
|
||||
{ 16800000, 600000000, 71, 1, 2, 0 }, /* actual: 596.4 MHz */
|
||||
{ 19200000, 600000000, 62, 1, 2, 0 }, /* actual: 595.2 MHz */
|
||||
{ 26000000, 600000000, 92, 2, 2, 0 }, /* actual: 598.0 MHz */
|
||||
{ 0, 0, 0, 0, 0, 0 },
|
||||
};
|
||||
|
||||
static struct tegra_clk_pll_params pll_dp_params = {
|
||||
|
|
@ -684,9 +718,10 @@ static struct tegra_clk_pll_params pll_dp_params = {
|
|||
.ext_misc_reg[2] = 0x5a0,
|
||||
.max_p = 5,
|
||||
.freq_table = pll_dp_freq_table,
|
||||
.flags = TEGRA_PLL_USE_LOCK | TEGRA_PLL_HAS_LOCK_ENABLE,
|
||||
};
|
||||
|
||||
static struct pdiv_map pllu_p[] = {
|
||||
static const struct pdiv_map pllu_p[] = {
|
||||
{ .pdiv = 1, .hw_val = 1 },
|
||||
{ .pdiv = 2, .hw_val = 0 },
|
||||
{ .pdiv = 0, .hw_val = 0 },
|
||||
|
|
@ -702,12 +737,12 @@ static struct div_nmp pllu_nmp = {
|
|||
};
|
||||
|
||||
static struct tegra_clk_pll_freq_table pll_u_freq_table[] = {
|
||||
{12000000, 480000000, 960, 12, 2, 12},
|
||||
{13000000, 480000000, 960, 13, 2, 12},
|
||||
{16800000, 480000000, 400, 7, 2, 5},
|
||||
{19200000, 480000000, 200, 4, 2, 3},
|
||||
{26000000, 480000000, 960, 26, 2, 12},
|
||||
{0, 0, 0, 0, 0, 0},
|
||||
{ 12000000, 480000000, 960, 12, 2, 12 },
|
||||
{ 13000000, 480000000, 960, 13, 2, 12 },
|
||||
{ 16800000, 480000000, 400, 7, 2, 5 },
|
||||
{ 19200000, 480000000, 200, 4, 2, 3 },
|
||||
{ 26000000, 480000000, 960, 26, 2, 12 },
|
||||
{ 0, 0, 0, 0, 0, 0 },
|
||||
};
|
||||
|
||||
static struct tegra_clk_pll_params pll_u_params = {
|
||||
|
|
@ -726,7 +761,7 @@ static struct tegra_clk_pll_params pll_u_params = {
|
|||
.div_nmp = &pllu_nmp,
|
||||
.freq_table = pll_u_freq_table,
|
||||
.flags = TEGRA_PLLU | TEGRA_PLL_HAS_CPCON | TEGRA_PLL_SET_LFCON |
|
||||
TEGRA_PLL_USE_LOCK,
|
||||
TEGRA_PLL_USE_LOCK | TEGRA_PLL_HAS_LOCK_ENABLE,
|
||||
};
|
||||
|
||||
struct utmi_clk_param {
|
||||
|
|
@ -743,21 +778,27 @@ struct utmi_clk_param {
|
|||
};
|
||||
|
||||
static const struct utmi_clk_param utmi_parameters[] = {
|
||||
{.osc_frequency = 13000000, .enable_delay_count = 0x02,
|
||||
.stable_count = 0x33, .active_delay_count = 0x05,
|
||||
.xtal_freq_count = 0x7F},
|
||||
{.osc_frequency = 19200000, .enable_delay_count = 0x03,
|
||||
.stable_count = 0x4B, .active_delay_count = 0x06,
|
||||
.xtal_freq_count = 0xBB},
|
||||
{.osc_frequency = 12000000, .enable_delay_count = 0x02,
|
||||
.stable_count = 0x2F, .active_delay_count = 0x04,
|
||||
.xtal_freq_count = 0x76},
|
||||
{.osc_frequency = 26000000, .enable_delay_count = 0x04,
|
||||
.stable_count = 0x66, .active_delay_count = 0x09,
|
||||
.xtal_freq_count = 0xFE},
|
||||
{.osc_frequency = 16800000, .enable_delay_count = 0x03,
|
||||
.stable_count = 0x41, .active_delay_count = 0x0A,
|
||||
.xtal_freq_count = 0xA4},
|
||||
{
|
||||
.osc_frequency = 13000000, .enable_delay_count = 0x02,
|
||||
.stable_count = 0x33, .active_delay_count = 0x05,
|
||||
.xtal_freq_count = 0x7f
|
||||
}, {
|
||||
.osc_frequency = 19200000, .enable_delay_count = 0x03,
|
||||
.stable_count = 0x4b, .active_delay_count = 0x06,
|
||||
.xtal_freq_count = 0xbb
|
||||
}, {
|
||||
.osc_frequency = 12000000, .enable_delay_count = 0x02,
|
||||
.stable_count = 0x2f, .active_delay_count = 0x04,
|
||||
.xtal_freq_count = 0x76
|
||||
}, {
|
||||
.osc_frequency = 26000000, .enable_delay_count = 0x04,
|
||||
.stable_count = 0x66, .active_delay_count = 0x09,
|
||||
.xtal_freq_count = 0xfe
|
||||
}, {
|
||||
.osc_frequency = 16800000, .enable_delay_count = 0x03,
|
||||
.stable_count = 0x41, .active_delay_count = 0x0a,
|
||||
.xtal_freq_count = 0xa4
|
||||
},
|
||||
};
|
||||
|
||||
static struct tegra_clk tegra124_clks[tegra_clk_max] __initdata = {
|
||||
|
|
@ -1024,8 +1065,8 @@ static struct clk **clks;
|
|||
|
||||
static void tegra124_utmi_param_configure(void __iomem *clk_base)
|
||||
{
|
||||
unsigned int i;
|
||||
u32 reg;
|
||||
int i;
|
||||
|
||||
for (i = 0; i < ARRAY_SIZE(utmi_parameters); i++) {
|
||||
if (osc_freq == utmi_parameters[i].osc_frequency)
|
||||
|
|
@ -1356,65 +1397,65 @@ static struct tegra_cpu_car_ops tegra124_cpu_car_ops = {
|
|||
|
||||
static const struct of_device_id pmc_match[] __initconst = {
|
||||
{ .compatible = "nvidia,tegra124-pmc" },
|
||||
{},
|
||||
{ },
|
||||
};
|
||||
|
||||
static struct tegra_clk_init_table common_init_table[] __initdata = {
|
||||
{TEGRA124_CLK_UARTA, TEGRA124_CLK_PLL_P, 408000000, 0},
|
||||
{TEGRA124_CLK_UARTB, TEGRA124_CLK_PLL_P, 408000000, 0},
|
||||
{TEGRA124_CLK_UARTC, TEGRA124_CLK_PLL_P, 408000000, 0},
|
||||
{TEGRA124_CLK_UARTD, TEGRA124_CLK_PLL_P, 408000000, 0},
|
||||
{TEGRA124_CLK_PLL_A, TEGRA124_CLK_CLK_MAX, 564480000, 1},
|
||||
{TEGRA124_CLK_PLL_A_OUT0, TEGRA124_CLK_CLK_MAX, 11289600, 1},
|
||||
{TEGRA124_CLK_EXTERN1, TEGRA124_CLK_PLL_A_OUT0, 0, 1},
|
||||
{TEGRA124_CLK_CLK_OUT_1_MUX, TEGRA124_CLK_EXTERN1, 0, 1},
|
||||
{TEGRA124_CLK_CLK_OUT_1, TEGRA124_CLK_CLK_MAX, 0, 1},
|
||||
{TEGRA124_CLK_I2S0, TEGRA124_CLK_PLL_A_OUT0, 11289600, 0},
|
||||
{TEGRA124_CLK_I2S1, TEGRA124_CLK_PLL_A_OUT0, 11289600, 0},
|
||||
{TEGRA124_CLK_I2S2, TEGRA124_CLK_PLL_A_OUT0, 11289600, 0},
|
||||
{TEGRA124_CLK_I2S3, TEGRA124_CLK_PLL_A_OUT0, 11289600, 0},
|
||||
{TEGRA124_CLK_I2S4, TEGRA124_CLK_PLL_A_OUT0, 11289600, 0},
|
||||
{TEGRA124_CLK_VDE, TEGRA124_CLK_PLL_P, 0, 0},
|
||||
{TEGRA124_CLK_HOST1X, TEGRA124_CLK_PLL_P, 136000000, 1},
|
||||
{TEGRA124_CLK_DSIALP, TEGRA124_CLK_PLL_P, 68000000, 0},
|
||||
{TEGRA124_CLK_DSIBLP, TEGRA124_CLK_PLL_P, 68000000, 0},
|
||||
{TEGRA124_CLK_SCLK, TEGRA124_CLK_PLL_P_OUT2, 102000000, 1},
|
||||
{TEGRA124_CLK_DFLL_SOC, TEGRA124_CLK_PLL_P, 51000000, 1},
|
||||
{TEGRA124_CLK_DFLL_REF, TEGRA124_CLK_PLL_P, 51000000, 1},
|
||||
{TEGRA124_CLK_PLL_C, TEGRA124_CLK_CLK_MAX, 768000000, 0},
|
||||
{TEGRA124_CLK_PLL_C_OUT1, TEGRA124_CLK_CLK_MAX, 100000000, 0},
|
||||
{TEGRA124_CLK_SBC4, TEGRA124_CLK_PLL_P, 12000000, 1},
|
||||
{TEGRA124_CLK_TSEC, TEGRA124_CLK_PLL_C3, 0, 0},
|
||||
{TEGRA124_CLK_MSENC, TEGRA124_CLK_PLL_C3, 0, 0},
|
||||
{TEGRA124_CLK_PLL_RE_VCO, TEGRA124_CLK_CLK_MAX, 672000000, 0},
|
||||
{TEGRA124_CLK_XUSB_SS_SRC, TEGRA124_CLK_PLL_U_480M, 120000000, 0},
|
||||
{TEGRA124_CLK_XUSB_FS_SRC, TEGRA124_CLK_PLL_U_48M, 48000000, 0},
|
||||
{TEGRA124_CLK_XUSB_HS_SRC, TEGRA124_CLK_PLL_U_60M, 60000000, 0},
|
||||
{TEGRA124_CLK_XUSB_FALCON_SRC, TEGRA124_CLK_PLL_RE_OUT, 224000000, 0},
|
||||
{TEGRA124_CLK_XUSB_HOST_SRC, TEGRA124_CLK_PLL_RE_OUT, 112000000, 0},
|
||||
{TEGRA124_CLK_SATA, TEGRA124_CLK_PLL_P, 104000000, 0},
|
||||
{TEGRA124_CLK_SATA_OOB, TEGRA124_CLK_PLL_P, 204000000, 0},
|
||||
{TEGRA124_CLK_MSELECT, TEGRA124_CLK_CLK_MAX, 0, 1},
|
||||
{TEGRA124_CLK_CSITE, TEGRA124_CLK_CLK_MAX, 0, 1},
|
||||
{TEGRA124_CLK_TSENSOR, TEGRA124_CLK_CLK_M, 400000, 0},
|
||||
/* This MUST be the last entry. */
|
||||
{TEGRA124_CLK_CLK_MAX, TEGRA124_CLK_CLK_MAX, 0, 0},
|
||||
{ TEGRA124_CLK_UARTA, TEGRA124_CLK_PLL_P, 408000000, 0 },
|
||||
{ TEGRA124_CLK_UARTB, TEGRA124_CLK_PLL_P, 408000000, 0 },
|
||||
{ TEGRA124_CLK_UARTC, TEGRA124_CLK_PLL_P, 408000000, 0 },
|
||||
{ TEGRA124_CLK_UARTD, TEGRA124_CLK_PLL_P, 408000000, 0 },
|
||||
{ TEGRA124_CLK_PLL_A, TEGRA124_CLK_CLK_MAX, 564480000, 1 },
|
||||
{ TEGRA124_CLK_PLL_A_OUT0, TEGRA124_CLK_CLK_MAX, 11289600, 1 },
|
||||
{ TEGRA124_CLK_EXTERN1, TEGRA124_CLK_PLL_A_OUT0, 0, 1 },
|
||||
{ TEGRA124_CLK_CLK_OUT_1_MUX, TEGRA124_CLK_EXTERN1, 0, 1 },
|
||||
{ TEGRA124_CLK_CLK_OUT_1, TEGRA124_CLK_CLK_MAX, 0, 1 },
|
||||
{ TEGRA124_CLK_I2S0, TEGRA124_CLK_PLL_A_OUT0, 11289600, 0 },
|
||||
{ TEGRA124_CLK_I2S1, TEGRA124_CLK_PLL_A_OUT0, 11289600, 0 },
|
||||
{ TEGRA124_CLK_I2S2, TEGRA124_CLK_PLL_A_OUT0, 11289600, 0 },
|
||||
{ TEGRA124_CLK_I2S3, TEGRA124_CLK_PLL_A_OUT0, 11289600, 0 },
|
||||
{ TEGRA124_CLK_I2S4, TEGRA124_CLK_PLL_A_OUT0, 11289600, 0 },
|
||||
{ TEGRA124_CLK_VDE, TEGRA124_CLK_PLL_P, 0, 0 },
|
||||
{ TEGRA124_CLK_HOST1X, TEGRA124_CLK_PLL_P, 136000000, 1 },
|
||||
{ TEGRA124_CLK_DSIALP, TEGRA124_CLK_PLL_P, 68000000, 0 },
|
||||
{ TEGRA124_CLK_DSIBLP, TEGRA124_CLK_PLL_P, 68000000, 0 },
|
||||
{ TEGRA124_CLK_SCLK, TEGRA124_CLK_PLL_P_OUT2, 102000000, 1 },
|
||||
{ TEGRA124_CLK_DFLL_SOC, TEGRA124_CLK_PLL_P, 51000000, 1 },
|
||||
{ TEGRA124_CLK_DFLL_REF, TEGRA124_CLK_PLL_P, 51000000, 1 },
|
||||
{ TEGRA124_CLK_PLL_C, TEGRA124_CLK_CLK_MAX, 768000000, 0 },
|
||||
{ TEGRA124_CLK_PLL_C_OUT1, TEGRA124_CLK_CLK_MAX, 100000000, 0 },
|
||||
{ TEGRA124_CLK_SBC4, TEGRA124_CLK_PLL_P, 12000000, 1 },
|
||||
{ TEGRA124_CLK_TSEC, TEGRA124_CLK_PLL_C3, 0, 0 },
|
||||
{ TEGRA124_CLK_MSENC, TEGRA124_CLK_PLL_C3, 0, 0 },
|
||||
{ TEGRA124_CLK_PLL_RE_VCO, TEGRA124_CLK_CLK_MAX, 672000000, 0 },
|
||||
{ TEGRA124_CLK_XUSB_SS_SRC, TEGRA124_CLK_PLL_U_480M, 120000000, 0 },
|
||||
{ TEGRA124_CLK_XUSB_FS_SRC, TEGRA124_CLK_PLL_U_48M, 48000000, 0 },
|
||||
{ TEGRA124_CLK_XUSB_HS_SRC, TEGRA124_CLK_PLL_U_60M, 60000000, 0 },
|
||||
{ TEGRA124_CLK_XUSB_FALCON_SRC, TEGRA124_CLK_PLL_RE_OUT, 224000000, 0 },
|
||||
{ TEGRA124_CLK_XUSB_HOST_SRC, TEGRA124_CLK_PLL_RE_OUT, 112000000, 0 },
|
||||
{ TEGRA124_CLK_SATA, TEGRA124_CLK_PLL_P, 104000000, 0 },
|
||||
{ TEGRA124_CLK_SATA_OOB, TEGRA124_CLK_PLL_P, 204000000, 0 },
|
||||
{ TEGRA124_CLK_MSELECT, TEGRA124_CLK_CLK_MAX, 0, 1 },
|
||||
{ TEGRA124_CLK_CSITE, TEGRA124_CLK_CLK_MAX, 0, 1 },
|
||||
{ TEGRA124_CLK_TSENSOR, TEGRA124_CLK_CLK_M, 400000, 0 },
|
||||
/* must be the last entry */
|
||||
{ TEGRA124_CLK_CLK_MAX, TEGRA124_CLK_CLK_MAX, 0, 0 },
|
||||
};
|
||||
|
||||
static struct tegra_clk_init_table tegra124_init_table[] __initdata = {
|
||||
{TEGRA124_CLK_SOC_THERM, TEGRA124_CLK_PLL_P, 51000000, 0},
|
||||
{TEGRA124_CLK_CCLK_G, TEGRA124_CLK_CLK_MAX, 0, 1},
|
||||
{TEGRA124_CLK_HDA, TEGRA124_CLK_PLL_P, 102000000, 0},
|
||||
{TEGRA124_CLK_HDA2CODEC_2X, TEGRA124_CLK_PLL_P, 48000000, 0},
|
||||
/* This MUST be the last entry. */
|
||||
{TEGRA124_CLK_CLK_MAX, TEGRA124_CLK_CLK_MAX, 0, 0},
|
||||
{ TEGRA124_CLK_SOC_THERM, TEGRA124_CLK_PLL_P, 51000000, 0 },
|
||||
{ TEGRA124_CLK_CCLK_G, TEGRA124_CLK_CLK_MAX, 0, 1 },
|
||||
{ TEGRA124_CLK_HDA, TEGRA124_CLK_PLL_P, 102000000, 0 },
|
||||
{ TEGRA124_CLK_HDA2CODEC_2X, TEGRA124_CLK_PLL_P, 48000000, 0 },
|
||||
/* must be the last entry */
|
||||
{ TEGRA124_CLK_CLK_MAX, TEGRA124_CLK_CLK_MAX, 0, 0 },
|
||||
};
|
||||
|
||||
/* Tegra132 requires the SOC_THERM clock to remain active */
|
||||
static struct tegra_clk_init_table tegra132_init_table[] __initdata = {
|
||||
{TEGRA124_CLK_SOC_THERM, TEGRA124_CLK_PLL_P, 51000000, 1},
|
||||
/* This MUST be the last entry. */
|
||||
{TEGRA124_CLK_CLK_MAX, TEGRA124_CLK_CLK_MAX, 0, 0},
|
||||
{ TEGRA124_CLK_SOC_THERM, TEGRA124_CLK_PLL_P, 51000000, 1 },
|
||||
/* must be the last entry */
|
||||
{ TEGRA124_CLK_CLK_MAX, TEGRA124_CLK_CLK_MAX, 0, 0 },
|
||||
};
|
||||
|
||||
static struct tegra_audio_clk_info tegra124_audio_plls[] = {
|
||||
|
|
|
|||
|
|
@ -166,126 +166,120 @@ static DEFINE_SPINLOCK(emc_lock);
|
|||
static struct clk **clks;
|
||||
|
||||
static struct tegra_clk_pll_freq_table pll_c_freq_table[] = {
|
||||
{ 12000000, 600000000, 600, 12, 0, 8 },
|
||||
{ 13000000, 600000000, 600, 13, 0, 8 },
|
||||
{ 19200000, 600000000, 500, 16, 0, 6 },
|
||||
{ 26000000, 600000000, 600, 26, 0, 8 },
|
||||
{ 0, 0, 0, 0, 0, 0 },
|
||||
{ 12000000, 600000000, 600, 12, 1, 8 },
|
||||
{ 13000000, 600000000, 600, 13, 1, 8 },
|
||||
{ 19200000, 600000000, 500, 16, 1, 6 },
|
||||
{ 26000000, 600000000, 600, 26, 1, 8 },
|
||||
{ 0, 0, 0, 0, 0, 0 },
|
||||
};
|
||||
|
||||
static struct tegra_clk_pll_freq_table pll_m_freq_table[] = {
|
||||
{ 12000000, 666000000, 666, 12, 0, 8},
|
||||
{ 13000000, 666000000, 666, 13, 0, 8},
|
||||
{ 19200000, 666000000, 555, 16, 0, 8},
|
||||
{ 26000000, 666000000, 666, 26, 0, 8},
|
||||
{ 12000000, 600000000, 600, 12, 0, 8},
|
||||
{ 13000000, 600000000, 600, 13, 0, 8},
|
||||
{ 19200000, 600000000, 375, 12, 0, 6},
|
||||
{ 26000000, 600000000, 600, 26, 0, 8},
|
||||
{ 0, 0, 0, 0, 0, 0 },
|
||||
{ 12000000, 666000000, 666, 12, 1, 8 },
|
||||
{ 13000000, 666000000, 666, 13, 1, 8 },
|
||||
{ 19200000, 666000000, 555, 16, 1, 8 },
|
||||
{ 26000000, 666000000, 666, 26, 1, 8 },
|
||||
{ 12000000, 600000000, 600, 12, 1, 8 },
|
||||
{ 13000000, 600000000, 600, 13, 1, 8 },
|
||||
{ 19200000, 600000000, 375, 12, 1, 6 },
|
||||
{ 26000000, 600000000, 600, 26, 1, 8 },
|
||||
{ 0, 0, 0, 0, 0, 0 },
|
||||
};
|
||||
|
||||
static struct tegra_clk_pll_freq_table pll_p_freq_table[] = {
|
||||
{ 12000000, 216000000, 432, 12, 1, 8},
|
||||
{ 13000000, 216000000, 432, 13, 1, 8},
|
||||
{ 19200000, 216000000, 90, 4, 1, 1},
|
||||
{ 26000000, 216000000, 432, 26, 1, 8},
|
||||
{ 12000000, 432000000, 432, 12, 0, 8},
|
||||
{ 13000000, 432000000, 432, 13, 0, 8},
|
||||
{ 19200000, 432000000, 90, 4, 0, 1},
|
||||
{ 26000000, 432000000, 432, 26, 0, 8},
|
||||
{ 0, 0, 0, 0, 0, 0 },
|
||||
{ 12000000, 216000000, 432, 12, 2, 8 },
|
||||
{ 13000000, 216000000, 432, 13, 2, 8 },
|
||||
{ 19200000, 216000000, 90, 4, 2, 1 },
|
||||
{ 26000000, 216000000, 432, 26, 2, 8 },
|
||||
{ 12000000, 432000000, 432, 12, 1, 8 },
|
||||
{ 13000000, 432000000, 432, 13, 1, 8 },
|
||||
{ 19200000, 432000000, 90, 4, 1, 1 },
|
||||
{ 26000000, 432000000, 432, 26, 1, 8 },
|
||||
{ 0, 0, 0, 0, 0, 0 },
|
||||
};
|
||||
|
||||
static struct tegra_clk_pll_freq_table pll_a_freq_table[] = {
|
||||
{ 28800000, 56448000, 49, 25, 0, 1},
|
||||
{ 28800000, 73728000, 64, 25, 0, 1},
|
||||
{ 28800000, 24000000, 5, 6, 0, 1},
|
||||
{ 0, 0, 0, 0, 0, 0 },
|
||||
{ 28800000, 56448000, 49, 25, 1, 1 },
|
||||
{ 28800000, 73728000, 64, 25, 1, 1 },
|
||||
{ 28800000, 24000000, 5, 6, 1, 1 },
|
||||
{ 0, 0, 0, 0, 0, 0 },
|
||||
};
|
||||
|
||||
static struct tegra_clk_pll_freq_table pll_d_freq_table[] = {
|
||||
{ 12000000, 216000000, 216, 12, 0, 4},
|
||||
{ 13000000, 216000000, 216, 13, 0, 4},
|
||||
{ 19200000, 216000000, 135, 12, 0, 3},
|
||||
{ 26000000, 216000000, 216, 26, 0, 4},
|
||||
|
||||
{ 12000000, 594000000, 594, 12, 0, 8},
|
||||
{ 13000000, 594000000, 594, 13, 0, 8},
|
||||
{ 19200000, 594000000, 495, 16, 0, 8},
|
||||
{ 26000000, 594000000, 594, 26, 0, 8},
|
||||
|
||||
{ 12000000, 1000000000, 1000, 12, 0, 12},
|
||||
{ 13000000, 1000000000, 1000, 13, 0, 12},
|
||||
{ 19200000, 1000000000, 625, 12, 0, 8},
|
||||
{ 26000000, 1000000000, 1000, 26, 0, 12},
|
||||
|
||||
{ 0, 0, 0, 0, 0, 0 },
|
||||
{ 12000000, 216000000, 216, 12, 1, 4 },
|
||||
{ 13000000, 216000000, 216, 13, 1, 4 },
|
||||
{ 19200000, 216000000, 135, 12, 1, 3 },
|
||||
{ 26000000, 216000000, 216, 26, 1, 4 },
|
||||
{ 12000000, 594000000, 594, 12, 1, 8 },
|
||||
{ 13000000, 594000000, 594, 13, 1, 8 },
|
||||
{ 19200000, 594000000, 495, 16, 1, 8 },
|
||||
{ 26000000, 594000000, 594, 26, 1, 8 },
|
||||
{ 12000000, 1000000000, 1000, 12, 1, 12 },
|
||||
{ 13000000, 1000000000, 1000, 13, 1, 12 },
|
||||
{ 19200000, 1000000000, 625, 12, 1, 8 },
|
||||
{ 26000000, 1000000000, 1000, 26, 1, 12 },
|
||||
{ 0, 0, 0, 0, 0, 0 },
|
||||
};
|
||||
|
||||
static struct tegra_clk_pll_freq_table pll_u_freq_table[] = {
|
||||
{ 12000000, 480000000, 960, 12, 0, 0},
|
||||
{ 13000000, 480000000, 960, 13, 0, 0},
|
||||
{ 19200000, 480000000, 200, 4, 0, 0},
|
||||
{ 26000000, 480000000, 960, 26, 0, 0},
|
||||
{ 0, 0, 0, 0, 0, 0 },
|
||||
{ 12000000, 480000000, 960, 12, 1, 0 },
|
||||
{ 13000000, 480000000, 960, 13, 1, 0 },
|
||||
{ 19200000, 480000000, 200, 4, 1, 0 },
|
||||
{ 26000000, 480000000, 960, 26, 1, 0 },
|
||||
{ 0, 0, 0, 0, 0, 0 },
|
||||
};
|
||||
|
||||
static struct tegra_clk_pll_freq_table pll_x_freq_table[] = {
|
||||
/* 1 GHz */
|
||||
{ 12000000, 1000000000, 1000, 12, 0, 12},
|
||||
{ 13000000, 1000000000, 1000, 13, 0, 12},
|
||||
{ 19200000, 1000000000, 625, 12, 0, 8},
|
||||
{ 26000000, 1000000000, 1000, 26, 0, 12},
|
||||
|
||||
{ 12000000, 1000000000, 1000, 12, 1, 12 },
|
||||
{ 13000000, 1000000000, 1000, 13, 1, 12 },
|
||||
{ 19200000, 1000000000, 625, 12, 1, 8 },
|
||||
{ 26000000, 1000000000, 1000, 26, 1, 12 },
|
||||
/* 912 MHz */
|
||||
{ 12000000, 912000000, 912, 12, 0, 12},
|
||||
{ 13000000, 912000000, 912, 13, 0, 12},
|
||||
{ 19200000, 912000000, 760, 16, 0, 8},
|
||||
{ 26000000, 912000000, 912, 26, 0, 12},
|
||||
|
||||
{ 12000000, 912000000, 912, 12, 1, 12 },
|
||||
{ 13000000, 912000000, 912, 13, 1, 12 },
|
||||
{ 19200000, 912000000, 760, 16, 1, 8 },
|
||||
{ 26000000, 912000000, 912, 26, 1, 12 },
|
||||
/* 816 MHz */
|
||||
{ 12000000, 816000000, 816, 12, 0, 12},
|
||||
{ 13000000, 816000000, 816, 13, 0, 12},
|
||||
{ 19200000, 816000000, 680, 16, 0, 8},
|
||||
{ 26000000, 816000000, 816, 26, 0, 12},
|
||||
|
||||
{ 12000000, 816000000, 816, 12, 1, 12 },
|
||||
{ 13000000, 816000000, 816, 13, 1, 12 },
|
||||
{ 19200000, 816000000, 680, 16, 1, 8 },
|
||||
{ 26000000, 816000000, 816, 26, 1, 12 },
|
||||
/* 760 MHz */
|
||||
{ 12000000, 760000000, 760, 12, 0, 12},
|
||||
{ 13000000, 760000000, 760, 13, 0, 12},
|
||||
{ 19200000, 760000000, 950, 24, 0, 8},
|
||||
{ 26000000, 760000000, 760, 26, 0, 12},
|
||||
|
||||
{ 12000000, 760000000, 760, 12, 1, 12 },
|
||||
{ 13000000, 760000000, 760, 13, 1, 12 },
|
||||
{ 19200000, 760000000, 950, 24, 1, 8 },
|
||||
{ 26000000, 760000000, 760, 26, 1, 12 },
|
||||
/* 750 MHz */
|
||||
{ 12000000, 750000000, 750, 12, 0, 12},
|
||||
{ 13000000, 750000000, 750, 13, 0, 12},
|
||||
{ 19200000, 750000000, 625, 16, 0, 8},
|
||||
{ 26000000, 750000000, 750, 26, 0, 12},
|
||||
|
||||
{ 12000000, 750000000, 750, 12, 1, 12 },
|
||||
{ 13000000, 750000000, 750, 13, 1, 12 },
|
||||
{ 19200000, 750000000, 625, 16, 1, 8 },
|
||||
{ 26000000, 750000000, 750, 26, 1, 12 },
|
||||
/* 608 MHz */
|
||||
{ 12000000, 608000000, 608, 12, 0, 12},
|
||||
{ 13000000, 608000000, 608, 13, 0, 12},
|
||||
{ 19200000, 608000000, 380, 12, 0, 8},
|
||||
{ 26000000, 608000000, 608, 26, 0, 12},
|
||||
|
||||
{ 12000000, 608000000, 608, 12, 1, 12 },
|
||||
{ 13000000, 608000000, 608, 13, 1, 12 },
|
||||
{ 19200000, 608000000, 380, 12, 1, 8 },
|
||||
{ 26000000, 608000000, 608, 26, 1, 12 },
|
||||
/* 456 MHz */
|
||||
{ 12000000, 456000000, 456, 12, 0, 12},
|
||||
{ 13000000, 456000000, 456, 13, 0, 12},
|
||||
{ 19200000, 456000000, 380, 16, 0, 8},
|
||||
{ 26000000, 456000000, 456, 26, 0, 12},
|
||||
|
||||
{ 12000000, 456000000, 456, 12, 1, 12 },
|
||||
{ 13000000, 456000000, 456, 13, 1, 12 },
|
||||
{ 19200000, 456000000, 380, 16, 1, 8 },
|
||||
{ 26000000, 456000000, 456, 26, 1, 12 },
|
||||
/* 312 MHz */
|
||||
{ 12000000, 312000000, 312, 12, 0, 12},
|
||||
{ 13000000, 312000000, 312, 13, 0, 12},
|
||||
{ 19200000, 312000000, 260, 16, 0, 8},
|
||||
{ 26000000, 312000000, 312, 26, 0, 12},
|
||||
{ 12000000, 312000000, 312, 12, 1, 12 },
|
||||
{ 13000000, 312000000, 312, 13, 1, 12 },
|
||||
{ 19200000, 312000000, 260, 16, 1, 8 },
|
||||
{ 26000000, 312000000, 312, 26, 1, 12 },
|
||||
{ 0, 0, 0, 0, 0, 0 },
|
||||
};
|
||||
|
||||
{ 0, 0, 0, 0, 0, 0 },
|
||||
static const struct pdiv_map plle_p[] = {
|
||||
{ .pdiv = 1, .hw_val = 1 },
|
||||
{ .pdiv = 0, .hw_val = 0 },
|
||||
};
|
||||
|
||||
static struct tegra_clk_pll_freq_table pll_e_freq_table[] = {
|
||||
{ 12000000, 100000000, 200, 24, 0, 0 },
|
||||
{ 0, 0, 0, 0, 0, 0 },
|
||||
{ 12000000, 100000000, 200, 24, 1, 0 },
|
||||
{ 0, 0, 0, 0, 0, 0 },
|
||||
};
|
||||
|
||||
/* PLL parameters */
|
||||
|
|
@ -302,7 +296,7 @@ static struct tegra_clk_pll_params pll_c_params = {
|
|||
.lock_enable_bit_idx = PLL_MISC_LOCK_ENABLE,
|
||||
.lock_delay = 300,
|
||||
.freq_table = pll_c_freq_table,
|
||||
.flags = TEGRA_PLL_HAS_CPCON,
|
||||
.flags = TEGRA_PLL_HAS_CPCON | TEGRA_PLL_HAS_LOCK_ENABLE,
|
||||
};
|
||||
|
||||
static struct tegra_clk_pll_params pll_m_params = {
|
||||
|
|
@ -318,7 +312,7 @@ static struct tegra_clk_pll_params pll_m_params = {
|
|||
.lock_enable_bit_idx = PLL_MISC_LOCK_ENABLE,
|
||||
.lock_delay = 300,
|
||||
.freq_table = pll_m_freq_table,
|
||||
.flags = TEGRA_PLL_HAS_CPCON,
|
||||
.flags = TEGRA_PLL_HAS_CPCON | TEGRA_PLL_HAS_LOCK_ENABLE,
|
||||
};
|
||||
|
||||
static struct tegra_clk_pll_params pll_p_params = {
|
||||
|
|
@ -334,7 +328,8 @@ static struct tegra_clk_pll_params pll_p_params = {
|
|||
.lock_enable_bit_idx = PLL_MISC_LOCK_ENABLE,
|
||||
.lock_delay = 300,
|
||||
.freq_table = pll_p_freq_table,
|
||||
.flags = TEGRA_PLL_FIXED | TEGRA_PLL_HAS_CPCON,
|
||||
.flags = TEGRA_PLL_FIXED | TEGRA_PLL_HAS_CPCON |
|
||||
TEGRA_PLL_HAS_LOCK_ENABLE,
|
||||
.fixed_rate = 216000000,
|
||||
};
|
||||
|
||||
|
|
@ -351,7 +346,7 @@ static struct tegra_clk_pll_params pll_a_params = {
|
|||
.lock_enable_bit_idx = PLL_MISC_LOCK_ENABLE,
|
||||
.lock_delay = 300,
|
||||
.freq_table = pll_a_freq_table,
|
||||
.flags = TEGRA_PLL_HAS_CPCON,
|
||||
.flags = TEGRA_PLL_HAS_CPCON | TEGRA_PLL_HAS_LOCK_ENABLE,
|
||||
};
|
||||
|
||||
static struct tegra_clk_pll_params pll_d_params = {
|
||||
|
|
@ -367,10 +362,10 @@ static struct tegra_clk_pll_params pll_d_params = {
|
|||
.lock_enable_bit_idx = PLLDU_MISC_LOCK_ENABLE,
|
||||
.lock_delay = 1000,
|
||||
.freq_table = pll_d_freq_table,
|
||||
.flags = TEGRA_PLL_HAS_CPCON,
|
||||
.flags = TEGRA_PLL_HAS_CPCON | TEGRA_PLL_HAS_LOCK_ENABLE,
|
||||
};
|
||||
|
||||
static struct pdiv_map pllu_p[] = {
|
||||
static const struct pdiv_map pllu_p[] = {
|
||||
{ .pdiv = 1, .hw_val = 1 },
|
||||
{ .pdiv = 2, .hw_val = 0 },
|
||||
{ .pdiv = 0, .hw_val = 0 },
|
||||
|
|
@ -390,7 +385,7 @@ static struct tegra_clk_pll_params pll_u_params = {
|
|||
.lock_delay = 1000,
|
||||
.pdiv_tohw = pllu_p,
|
||||
.freq_table = pll_u_freq_table,
|
||||
.flags = TEGRA_PLLU | TEGRA_PLL_HAS_CPCON,
|
||||
.flags = TEGRA_PLLU | TEGRA_PLL_HAS_CPCON | TEGRA_PLL_HAS_LOCK_ENABLE,
|
||||
};
|
||||
|
||||
static struct tegra_clk_pll_params pll_x_params = {
|
||||
|
|
@ -406,7 +401,7 @@ static struct tegra_clk_pll_params pll_x_params = {
|
|||
.lock_enable_bit_idx = PLL_MISC_LOCK_ENABLE,
|
||||
.lock_delay = 300,
|
||||
.freq_table = pll_x_freq_table,
|
||||
.flags = TEGRA_PLL_HAS_CPCON,
|
||||
.flags = TEGRA_PLL_HAS_CPCON | TEGRA_PLL_HAS_LOCK_ENABLE,
|
||||
};
|
||||
|
||||
static struct tegra_clk_pll_params pll_e_params = {
|
||||
|
|
@ -421,8 +416,10 @@ static struct tegra_clk_pll_params pll_e_params = {
|
|||
.lock_mask = PLLE_MISC_LOCK,
|
||||
.lock_enable_bit_idx = PLLE_MISC_LOCK_ENABLE,
|
||||
.lock_delay = 0,
|
||||
.pdiv_tohw = plle_p,
|
||||
.freq_table = pll_e_freq_table,
|
||||
.flags = TEGRA_PLL_FIXED,
|
||||
.flags = TEGRA_PLL_FIXED | TEGRA_PLL_LOCK_MISC |
|
||||
TEGRA_PLL_HAS_LOCK_ENABLE,
|
||||
.fixed_rate = 100000000,
|
||||
};
|
||||
|
||||
|
|
@ -733,9 +730,9 @@ static void tegra20_super_clk_init(void)
|
|||
clks[TEGRA20_CLK_TWD] = clk;
|
||||
}
|
||||
|
||||
static const char *audio_parents[] = {"spdif_in", "i2s1", "i2s2", "unused",
|
||||
"pll_a_out0", "unused", "unused",
|
||||
"unused"};
|
||||
static const char *audio_parents[] = { "spdif_in", "i2s1", "i2s2", "unused",
|
||||
"pll_a_out0", "unused", "unused",
|
||||
"unused" };
|
||||
|
||||
static void __init tegra20_audio_clk_init(void)
|
||||
{
|
||||
|
|
@ -759,19 +756,18 @@ static void __init tegra20_audio_clk_init(void)
|
|||
CLK_SET_RATE_PARENT, 89,
|
||||
periph_clk_enb_refcnt);
|
||||
clks[TEGRA20_CLK_AUDIO_2X] = clk;
|
||||
|
||||
}
|
||||
|
||||
static const char *i2s1_parents[] = {"pll_a_out0", "audio_2x", "pll_p",
|
||||
"clk_m"};
|
||||
static const char *i2s2_parents[] = {"pll_a_out0", "audio_2x", "pll_p",
|
||||
"clk_m"};
|
||||
static const char *pwm_parents[] = {"pll_p", "pll_c", "audio", "clk_m",
|
||||
"clk_32k"};
|
||||
static const char *mux_pllpcm_clkm[] = {"pll_p", "pll_c", "pll_m", "clk_m"};
|
||||
static const char *mux_pllpdc_clkm[] = {"pll_p", "pll_d_out0", "pll_c",
|
||||
"clk_m"};
|
||||
static const char *mux_pllmcp_clkm[] = {"pll_m", "pll_c", "pll_p", "clk_m"};
|
||||
static const char *i2s1_parents[] = { "pll_a_out0", "audio_2x", "pll_p",
|
||||
"clk_m" };
|
||||
static const char *i2s2_parents[] = { "pll_a_out0", "audio_2x", "pll_p",
|
||||
"clk_m" };
|
||||
static const char *pwm_parents[] = { "pll_p", "pll_c", "audio", "clk_m",
|
||||
"clk_32k" };
|
||||
static const char *mux_pllpcm_clkm[] = { "pll_p", "pll_c", "pll_m", "clk_m" };
|
||||
static const char *mux_pllpdc_clkm[] = { "pll_p", "pll_d_out0", "pll_c",
|
||||
"clk_m" };
|
||||
static const char *mux_pllmcp_clkm[] = { "pll_m", "pll_c", "pll_p", "clk_m" };
|
||||
|
||||
static struct tegra_periph_init_data tegra_periph_clk_list[] = {
|
||||
TEGRA_INIT_DATA_MUX("i2s1", i2s1_parents, CLK_SOURCE_I2S1, 11, TEGRA_PERIPH_ON_APB, TEGRA20_CLK_I2S1),
|
||||
|
|
@ -802,7 +798,7 @@ static void __init tegra20_periph_clk_init(void)
|
|||
{
|
||||
struct tegra_periph_init_data *data;
|
||||
struct clk *clk;
|
||||
int i;
|
||||
unsigned int i;
|
||||
|
||||
/* ac97 */
|
||||
clk = tegra_clk_register_periph_gate("ac97", "pll_a_out0",
|
||||
|
|
@ -1025,44 +1021,45 @@ static struct tegra_cpu_car_ops tegra20_cpu_car_ops = {
|
|||
};
|
||||
|
||||
static struct tegra_clk_init_table init_table[] __initdata = {
|
||||
{TEGRA20_CLK_PLL_P, TEGRA20_CLK_CLK_MAX, 216000000, 1},
|
||||
{TEGRA20_CLK_PLL_P_OUT1, TEGRA20_CLK_CLK_MAX, 28800000, 1},
|
||||
{TEGRA20_CLK_PLL_P_OUT2, TEGRA20_CLK_CLK_MAX, 48000000, 1},
|
||||
{TEGRA20_CLK_PLL_P_OUT3, TEGRA20_CLK_CLK_MAX, 72000000, 1},
|
||||
{TEGRA20_CLK_PLL_P_OUT4, TEGRA20_CLK_CLK_MAX, 24000000, 1},
|
||||
{TEGRA20_CLK_PLL_C, TEGRA20_CLK_CLK_MAX, 600000000, 1},
|
||||
{TEGRA20_CLK_PLL_C_OUT1, TEGRA20_CLK_CLK_MAX, 120000000, 1},
|
||||
{TEGRA20_CLK_SCLK, TEGRA20_CLK_PLL_C_OUT1, 0, 1},
|
||||
{TEGRA20_CLK_HCLK, TEGRA20_CLK_CLK_MAX, 0, 1},
|
||||
{TEGRA20_CLK_PCLK, TEGRA20_CLK_CLK_MAX, 60000000, 1},
|
||||
{TEGRA20_CLK_CSITE, TEGRA20_CLK_CLK_MAX, 0, 1},
|
||||
{TEGRA20_CLK_EMC, TEGRA20_CLK_CLK_MAX, 0, 1},
|
||||
{TEGRA20_CLK_CCLK, TEGRA20_CLK_CLK_MAX, 0, 1},
|
||||
{TEGRA20_CLK_UARTA, TEGRA20_CLK_PLL_P, 0, 0},
|
||||
{TEGRA20_CLK_UARTB, TEGRA20_CLK_PLL_P, 0, 0},
|
||||
{TEGRA20_CLK_UARTC, TEGRA20_CLK_PLL_P, 0, 0},
|
||||
{TEGRA20_CLK_UARTD, TEGRA20_CLK_PLL_P, 0, 0},
|
||||
{TEGRA20_CLK_UARTE, TEGRA20_CLK_PLL_P, 0, 0},
|
||||
{TEGRA20_CLK_PLL_A, TEGRA20_CLK_CLK_MAX, 56448000, 1},
|
||||
{TEGRA20_CLK_PLL_A_OUT0, TEGRA20_CLK_CLK_MAX, 11289600, 1},
|
||||
{TEGRA20_CLK_CDEV1, TEGRA20_CLK_CLK_MAX, 0, 1},
|
||||
{TEGRA20_CLK_BLINK, TEGRA20_CLK_CLK_MAX, 32768, 1},
|
||||
{TEGRA20_CLK_I2S1, TEGRA20_CLK_PLL_A_OUT0, 11289600, 0},
|
||||
{TEGRA20_CLK_I2S2, TEGRA20_CLK_PLL_A_OUT0, 11289600, 0},
|
||||
{TEGRA20_CLK_SDMMC1, TEGRA20_CLK_PLL_P, 48000000, 0},
|
||||
{TEGRA20_CLK_SDMMC3, TEGRA20_CLK_PLL_P, 48000000, 0},
|
||||
{TEGRA20_CLK_SDMMC4, TEGRA20_CLK_PLL_P, 48000000, 0},
|
||||
{TEGRA20_CLK_SPI, TEGRA20_CLK_PLL_P, 20000000, 0},
|
||||
{TEGRA20_CLK_SBC1, TEGRA20_CLK_PLL_P, 100000000, 0},
|
||||
{TEGRA20_CLK_SBC2, TEGRA20_CLK_PLL_P, 100000000, 0},
|
||||
{TEGRA20_CLK_SBC3, TEGRA20_CLK_PLL_P, 100000000, 0},
|
||||
{TEGRA20_CLK_SBC4, TEGRA20_CLK_PLL_P, 100000000, 0},
|
||||
{TEGRA20_CLK_HOST1X, TEGRA20_CLK_PLL_C, 150000000, 0},
|
||||
{TEGRA20_CLK_DISP1, TEGRA20_CLK_PLL_P, 600000000, 0},
|
||||
{TEGRA20_CLK_DISP2, TEGRA20_CLK_PLL_P, 600000000, 0},
|
||||
{TEGRA20_CLK_GR2D, TEGRA20_CLK_PLL_C, 300000000, 0},
|
||||
{TEGRA20_CLK_GR3D, TEGRA20_CLK_PLL_C, 300000000, 0},
|
||||
{TEGRA20_CLK_CLK_MAX, TEGRA20_CLK_CLK_MAX, 0, 0}, /* This MUST be the last entry */
|
||||
{ TEGRA20_CLK_PLL_P, TEGRA20_CLK_CLK_MAX, 216000000, 1 },
|
||||
{ TEGRA20_CLK_PLL_P_OUT1, TEGRA20_CLK_CLK_MAX, 28800000, 1 },
|
||||
{ TEGRA20_CLK_PLL_P_OUT2, TEGRA20_CLK_CLK_MAX, 48000000, 1 },
|
||||
{ TEGRA20_CLK_PLL_P_OUT3, TEGRA20_CLK_CLK_MAX, 72000000, 1 },
|
||||
{ TEGRA20_CLK_PLL_P_OUT4, TEGRA20_CLK_CLK_MAX, 24000000, 1 },
|
||||
{ TEGRA20_CLK_PLL_C, TEGRA20_CLK_CLK_MAX, 600000000, 1 },
|
||||
{ TEGRA20_CLK_PLL_C_OUT1, TEGRA20_CLK_CLK_MAX, 120000000, 1 },
|
||||
{ TEGRA20_CLK_SCLK, TEGRA20_CLK_PLL_C_OUT1, 0, 1 },
|
||||
{ TEGRA20_CLK_HCLK, TEGRA20_CLK_CLK_MAX, 0, 1 },
|
||||
{ TEGRA20_CLK_PCLK, TEGRA20_CLK_CLK_MAX, 60000000, 1 },
|
||||
{ TEGRA20_CLK_CSITE, TEGRA20_CLK_CLK_MAX, 0, 1 },
|
||||
{ TEGRA20_CLK_EMC, TEGRA20_CLK_CLK_MAX, 0, 1 },
|
||||
{ TEGRA20_CLK_CCLK, TEGRA20_CLK_CLK_MAX, 0, 1 },
|
||||
{ TEGRA20_CLK_UARTA, TEGRA20_CLK_PLL_P, 0, 0 },
|
||||
{ TEGRA20_CLK_UARTB, TEGRA20_CLK_PLL_P, 0, 0 },
|
||||
{ TEGRA20_CLK_UARTC, TEGRA20_CLK_PLL_P, 0, 0 },
|
||||
{ TEGRA20_CLK_UARTD, TEGRA20_CLK_PLL_P, 0, 0 },
|
||||
{ TEGRA20_CLK_UARTE, TEGRA20_CLK_PLL_P, 0, 0 },
|
||||
{ TEGRA20_CLK_PLL_A, TEGRA20_CLK_CLK_MAX, 56448000, 1 },
|
||||
{ TEGRA20_CLK_PLL_A_OUT0, TEGRA20_CLK_CLK_MAX, 11289600, 1 },
|
||||
{ TEGRA20_CLK_CDEV1, TEGRA20_CLK_CLK_MAX, 0, 1 },
|
||||
{ TEGRA20_CLK_BLINK, TEGRA20_CLK_CLK_MAX, 32768, 1 },
|
||||
{ TEGRA20_CLK_I2S1, TEGRA20_CLK_PLL_A_OUT0, 11289600, 0 },
|
||||
{ TEGRA20_CLK_I2S2, TEGRA20_CLK_PLL_A_OUT0, 11289600, 0 },
|
||||
{ TEGRA20_CLK_SDMMC1, TEGRA20_CLK_PLL_P, 48000000, 0 },
|
||||
{ TEGRA20_CLK_SDMMC3, TEGRA20_CLK_PLL_P, 48000000, 0 },
|
||||
{ TEGRA20_CLK_SDMMC4, TEGRA20_CLK_PLL_P, 48000000, 0 },
|
||||
{ TEGRA20_CLK_SPI, TEGRA20_CLK_PLL_P, 20000000, 0 },
|
||||
{ TEGRA20_CLK_SBC1, TEGRA20_CLK_PLL_P, 100000000, 0 },
|
||||
{ TEGRA20_CLK_SBC2, TEGRA20_CLK_PLL_P, 100000000, 0 },
|
||||
{ TEGRA20_CLK_SBC3, TEGRA20_CLK_PLL_P, 100000000, 0 },
|
||||
{ TEGRA20_CLK_SBC4, TEGRA20_CLK_PLL_P, 100000000, 0 },
|
||||
{ TEGRA20_CLK_HOST1X, TEGRA20_CLK_PLL_C, 150000000, 0 },
|
||||
{ TEGRA20_CLK_DISP1, TEGRA20_CLK_PLL_P, 600000000, 0 },
|
||||
{ TEGRA20_CLK_DISP2, TEGRA20_CLK_PLL_P, 600000000, 0 },
|
||||
{ TEGRA20_CLK_GR2D, TEGRA20_CLK_PLL_C, 300000000, 0 },
|
||||
{ TEGRA20_CLK_GR3D, TEGRA20_CLK_PLL_C, 300000000, 0 },
|
||||
/* must be the last entry */
|
||||
{ TEGRA20_CLK_CLK_MAX, TEGRA20_CLK_CLK_MAX, 0, 0 },
|
||||
};
|
||||
|
||||
static void __init tegra20_clock_apply_init_table(void)
|
||||
|
|
@ -1076,16 +1073,17 @@ static void __init tegra20_clock_apply_init_table(void)
|
|||
* table under two names.
|
||||
*/
|
||||
static struct tegra_clk_duplicate tegra_clk_duplicates[] = {
|
||||
TEGRA_CLK_DUPLICATE(TEGRA20_CLK_USBD, "utmip-pad", NULL),
|
||||
TEGRA_CLK_DUPLICATE(TEGRA20_CLK_USBD, "tegra-ehci.0", NULL),
|
||||
TEGRA_CLK_DUPLICATE(TEGRA20_CLK_USBD, "tegra-otg", NULL),
|
||||
TEGRA_CLK_DUPLICATE(TEGRA20_CLK_CCLK, NULL, "cpu"),
|
||||
TEGRA_CLK_DUPLICATE(TEGRA20_CLK_CLK_MAX, NULL, NULL), /* Must be the last entry */
|
||||
TEGRA_CLK_DUPLICATE(TEGRA20_CLK_USBD, "utmip-pad", NULL),
|
||||
TEGRA_CLK_DUPLICATE(TEGRA20_CLK_USBD, "tegra-ehci.0", NULL),
|
||||
TEGRA_CLK_DUPLICATE(TEGRA20_CLK_USBD, "tegra-otg", NULL),
|
||||
TEGRA_CLK_DUPLICATE(TEGRA20_CLK_CCLK, NULL, "cpu"),
|
||||
/* must be the last entry */
|
||||
TEGRA_CLK_DUPLICATE(TEGRA20_CLK_CLK_MAX, NULL, NULL),
|
||||
};
|
||||
|
||||
static const struct of_device_id pmc_match[] __initconst = {
|
||||
{ .compatible = "nvidia,tegra20-pmc" },
|
||||
{},
|
||||
{ },
|
||||
};
|
||||
|
||||
static void __init tegra20_clock_init(struct device_node *np)
|
||||
|
|
|
|||
2852
drivers/clk/tegra/clk-tegra210.c
Normal file
2852
drivers/clk/tegra/clk-tegra210.c
Normal file
File diff suppressed because it is too large
Load diff
|
|
@ -224,188 +224,192 @@ struct utmi_clk_param {
|
|||
};
|
||||
|
||||
static const struct utmi_clk_param utmi_parameters[] = {
|
||||
/* OSC_FREQUENCY, ENABLE_DLY, STABLE_CNT, ACTIVE_DLY, XTAL_FREQ_CNT */
|
||||
{13000000, 0x02, 0x33, 0x05, 0x7F},
|
||||
{19200000, 0x03, 0x4B, 0x06, 0xBB},
|
||||
{12000000, 0x02, 0x2F, 0x04, 0x76},
|
||||
{26000000, 0x04, 0x66, 0x09, 0xFE},
|
||||
{16800000, 0x03, 0x41, 0x0A, 0xA4},
|
||||
{
|
||||
.osc_frequency = 13000000, .enable_delay_count = 0x02,
|
||||
.stable_count = 0x33, .active_delay_count = 0x05,
|
||||
.xtal_freq_count = 0x7f
|
||||
}, {
|
||||
.osc_frequency = 19200000, .enable_delay_count = 0x03,
|
||||
.stable_count = 0x4b, .active_delay_count = 0x06,
|
||||
.xtal_freq_count = 0xbb
|
||||
}, {
|
||||
.osc_frequency = 12000000, .enable_delay_count = 0x02,
|
||||
.stable_count = 0x2f, .active_delay_count = 0x04,
|
||||
.xtal_freq_count = 0x76
|
||||
}, {
|
||||
.osc_frequency = 26000000, .enable_delay_count = 0x04,
|
||||
.stable_count = 0x66, .active_delay_count = 0x09,
|
||||
.xtal_freq_count = 0xfe
|
||||
}, {
|
||||
.osc_frequency = 16800000, .enable_delay_count = 0x03,
|
||||
.stable_count = 0x41, .active_delay_count = 0x0a,
|
||||
.xtal_freq_count = 0xa4
|
||||
},
|
||||
};
|
||||
|
||||
static struct tegra_clk_pll_freq_table pll_c_freq_table[] = {
|
||||
{ 12000000, 1040000000, 520, 6, 0, 8},
|
||||
{ 13000000, 1040000000, 480, 6, 0, 8},
|
||||
{ 16800000, 1040000000, 495, 8, 0, 8}, /* actual: 1039.5 MHz */
|
||||
{ 19200000, 1040000000, 325, 6, 0, 6},
|
||||
{ 26000000, 1040000000, 520, 13, 0, 8},
|
||||
|
||||
{ 12000000, 832000000, 416, 6, 0, 8},
|
||||
{ 13000000, 832000000, 832, 13, 0, 8},
|
||||
{ 16800000, 832000000, 396, 8, 0, 8}, /* actual: 831.6 MHz */
|
||||
{ 19200000, 832000000, 260, 6, 0, 8},
|
||||
{ 26000000, 832000000, 416, 13, 0, 8},
|
||||
|
||||
{ 12000000, 624000000, 624, 12, 0, 8},
|
||||
{ 13000000, 624000000, 624, 13, 0, 8},
|
||||
{ 16800000, 600000000, 520, 14, 0, 8},
|
||||
{ 19200000, 624000000, 520, 16, 0, 8},
|
||||
{ 26000000, 624000000, 624, 26, 0, 8},
|
||||
|
||||
{ 12000000, 600000000, 600, 12, 0, 8},
|
||||
{ 13000000, 600000000, 600, 13, 0, 8},
|
||||
{ 16800000, 600000000, 500, 14, 0, 8},
|
||||
{ 19200000, 600000000, 375, 12, 0, 6},
|
||||
{ 26000000, 600000000, 600, 26, 0, 8},
|
||||
|
||||
{ 12000000, 520000000, 520, 12, 0, 8},
|
||||
{ 13000000, 520000000, 520, 13, 0, 8},
|
||||
{ 16800000, 520000000, 495, 16, 0, 8}, /* actual: 519.75 MHz */
|
||||
{ 19200000, 520000000, 325, 12, 0, 6},
|
||||
{ 26000000, 520000000, 520, 26, 0, 8},
|
||||
|
||||
{ 12000000, 416000000, 416, 12, 0, 8},
|
||||
{ 13000000, 416000000, 416, 13, 0, 8},
|
||||
{ 16800000, 416000000, 396, 16, 0, 8}, /* actual: 415.8 MHz */
|
||||
{ 19200000, 416000000, 260, 12, 0, 6},
|
||||
{ 26000000, 416000000, 416, 26, 0, 8},
|
||||
{ 0, 0, 0, 0, 0, 0 },
|
||||
{ 12000000, 1040000000, 520, 6, 1, 8 },
|
||||
{ 13000000, 1040000000, 480, 6, 1, 8 },
|
||||
{ 16800000, 1040000000, 495, 8, 1, 8 }, /* actual: 1039.5 MHz */
|
||||
{ 19200000, 1040000000, 325, 6, 1, 6 },
|
||||
{ 26000000, 1040000000, 520, 13, 1, 8 },
|
||||
{ 12000000, 832000000, 416, 6, 1, 8 },
|
||||
{ 13000000, 832000000, 832, 13, 1, 8 },
|
||||
{ 16800000, 832000000, 396, 8, 1, 8 }, /* actual: 831.6 MHz */
|
||||
{ 19200000, 832000000, 260, 6, 1, 8 },
|
||||
{ 26000000, 832000000, 416, 13, 1, 8 },
|
||||
{ 12000000, 624000000, 624, 12, 1, 8 },
|
||||
{ 13000000, 624000000, 624, 13, 1, 8 },
|
||||
{ 16800000, 600000000, 520, 14, 1, 8 },
|
||||
{ 19200000, 624000000, 520, 16, 1, 8 },
|
||||
{ 26000000, 624000000, 624, 26, 1, 8 },
|
||||
{ 12000000, 600000000, 600, 12, 1, 8 },
|
||||
{ 13000000, 600000000, 600, 13, 1, 8 },
|
||||
{ 16800000, 600000000, 500, 14, 1, 8 },
|
||||
{ 19200000, 600000000, 375, 12, 1, 6 },
|
||||
{ 26000000, 600000000, 600, 26, 1, 8 },
|
||||
{ 12000000, 520000000, 520, 12, 1, 8 },
|
||||
{ 13000000, 520000000, 520, 13, 1, 8 },
|
||||
{ 16800000, 520000000, 495, 16, 1, 8 }, /* actual: 519.75 MHz */
|
||||
{ 19200000, 520000000, 325, 12, 1, 6 },
|
||||
{ 26000000, 520000000, 520, 26, 1, 8 },
|
||||
{ 12000000, 416000000, 416, 12, 1, 8 },
|
||||
{ 13000000, 416000000, 416, 13, 1, 8 },
|
||||
{ 16800000, 416000000, 396, 16, 1, 8 }, /* actual: 415.8 MHz */
|
||||
{ 19200000, 416000000, 260, 12, 1, 6 },
|
||||
{ 26000000, 416000000, 416, 26, 1, 8 },
|
||||
{ 0, 0, 0, 0, 0, 0 },
|
||||
};
|
||||
|
||||
static struct tegra_clk_pll_freq_table pll_m_freq_table[] = {
|
||||
{ 12000000, 666000000, 666, 12, 0, 8},
|
||||
{ 13000000, 666000000, 666, 13, 0, 8},
|
||||
{ 16800000, 666000000, 555, 14, 0, 8},
|
||||
{ 19200000, 666000000, 555, 16, 0, 8},
|
||||
{ 26000000, 666000000, 666, 26, 0, 8},
|
||||
{ 12000000, 600000000, 600, 12, 0, 8},
|
||||
{ 13000000, 600000000, 600, 13, 0, 8},
|
||||
{ 16800000, 600000000, 500, 14, 0, 8},
|
||||
{ 19200000, 600000000, 375, 12, 0, 6},
|
||||
{ 26000000, 600000000, 600, 26, 0, 8},
|
||||
{ 0, 0, 0, 0, 0, 0 },
|
||||
{ 12000000, 666000000, 666, 12, 1, 8 },
|
||||
{ 13000000, 666000000, 666, 13, 1, 8 },
|
||||
{ 16800000, 666000000, 555, 14, 1, 8 },
|
||||
{ 19200000, 666000000, 555, 16, 1, 8 },
|
||||
{ 26000000, 666000000, 666, 26, 1, 8 },
|
||||
{ 12000000, 600000000, 600, 12, 1, 8 },
|
||||
{ 13000000, 600000000, 600, 13, 1, 8 },
|
||||
{ 16800000, 600000000, 500, 14, 1, 8 },
|
||||
{ 19200000, 600000000, 375, 12, 1, 6 },
|
||||
{ 26000000, 600000000, 600, 26, 1, 8 },
|
||||
{ 0, 0, 0, 0, 0, 0 },
|
||||
};
|
||||
|
||||
static struct tegra_clk_pll_freq_table pll_p_freq_table[] = {
|
||||
{ 12000000, 216000000, 432, 12, 1, 8},
|
||||
{ 13000000, 216000000, 432, 13, 1, 8},
|
||||
{ 16800000, 216000000, 360, 14, 1, 8},
|
||||
{ 19200000, 216000000, 360, 16, 1, 8},
|
||||
{ 26000000, 216000000, 432, 26, 1, 8},
|
||||
{ 0, 0, 0, 0, 0, 0 },
|
||||
{ 12000000, 216000000, 432, 12, 2, 8 },
|
||||
{ 13000000, 216000000, 432, 13, 2, 8 },
|
||||
{ 16800000, 216000000, 360, 14, 2, 8 },
|
||||
{ 19200000, 216000000, 360, 16, 2, 8 },
|
||||
{ 26000000, 216000000, 432, 26, 2, 8 },
|
||||
{ 0, 0, 0, 0, 0, 0 },
|
||||
};
|
||||
|
||||
static struct tegra_clk_pll_freq_table pll_a_freq_table[] = {
|
||||
{ 9600000, 564480000, 294, 5, 0, 4},
|
||||
{ 9600000, 552960000, 288, 5, 0, 4},
|
||||
{ 9600000, 24000000, 5, 2, 0, 1},
|
||||
|
||||
{ 28800000, 56448000, 49, 25, 0, 1},
|
||||
{ 28800000, 73728000, 64, 25, 0, 1},
|
||||
{ 28800000, 24000000, 5, 6, 0, 1},
|
||||
{ 0, 0, 0, 0, 0, 0 },
|
||||
{ 9600000, 564480000, 294, 5, 1, 4 },
|
||||
{ 9600000, 552960000, 288, 5, 1, 4 },
|
||||
{ 9600000, 24000000, 5, 2, 1, 1 },
|
||||
{ 28800000, 56448000, 49, 25, 1, 1 },
|
||||
{ 28800000, 73728000, 64, 25, 1, 1 },
|
||||
{ 28800000, 24000000, 5, 6, 1, 1 },
|
||||
{ 0, 0, 0, 0, 0, 0 },
|
||||
};
|
||||
|
||||
static struct tegra_clk_pll_freq_table pll_d_freq_table[] = {
|
||||
{ 12000000, 216000000, 216, 12, 0, 4},
|
||||
{ 13000000, 216000000, 216, 13, 0, 4},
|
||||
{ 16800000, 216000000, 180, 14, 0, 4},
|
||||
{ 19200000, 216000000, 180, 16, 0, 4},
|
||||
{ 26000000, 216000000, 216, 26, 0, 4},
|
||||
|
||||
{ 12000000, 594000000, 594, 12, 0, 8},
|
||||
{ 13000000, 594000000, 594, 13, 0, 8},
|
||||
{ 16800000, 594000000, 495, 14, 0, 8},
|
||||
{ 19200000, 594000000, 495, 16, 0, 8},
|
||||
{ 26000000, 594000000, 594, 26, 0, 8},
|
||||
|
||||
{ 12000000, 1000000000, 1000, 12, 0, 12},
|
||||
{ 13000000, 1000000000, 1000, 13, 0, 12},
|
||||
{ 19200000, 1000000000, 625, 12, 0, 8},
|
||||
{ 26000000, 1000000000, 1000, 26, 0, 12},
|
||||
|
||||
{ 0, 0, 0, 0, 0, 0 },
|
||||
{ 12000000, 216000000, 216, 12, 1, 4 },
|
||||
{ 13000000, 216000000, 216, 13, 1, 4 },
|
||||
{ 16800000, 216000000, 180, 14, 1, 4 },
|
||||
{ 19200000, 216000000, 180, 16, 1, 4 },
|
||||
{ 26000000, 216000000, 216, 26, 1, 4 },
|
||||
{ 12000000, 594000000, 594, 12, 1, 8 },
|
||||
{ 13000000, 594000000, 594, 13, 1, 8 },
|
||||
{ 16800000, 594000000, 495, 14, 1, 8 },
|
||||
{ 19200000, 594000000, 495, 16, 1, 8 },
|
||||
{ 26000000, 594000000, 594, 26, 1, 8 },
|
||||
{ 12000000, 1000000000, 1000, 12, 1, 12 },
|
||||
{ 13000000, 1000000000, 1000, 13, 1, 12 },
|
||||
{ 19200000, 1000000000, 625, 12, 1, 8 },
|
||||
{ 26000000, 1000000000, 1000, 26, 1, 12 },
|
||||
{ 0, 0, 0, 0, 0, 0 },
|
||||
};
|
||||
|
||||
static struct pdiv_map pllu_p[] = {
|
||||
static const struct pdiv_map pllu_p[] = {
|
||||
{ .pdiv = 1, .hw_val = 1 },
|
||||
{ .pdiv = 2, .hw_val = 0 },
|
||||
{ .pdiv = 0, .hw_val = 0 },
|
||||
};
|
||||
|
||||
static struct tegra_clk_pll_freq_table pll_u_freq_table[] = {
|
||||
{ 12000000, 480000000, 960, 12, 0, 12},
|
||||
{ 13000000, 480000000, 960, 13, 0, 12},
|
||||
{ 16800000, 480000000, 400, 7, 0, 5},
|
||||
{ 19200000, 480000000, 200, 4, 0, 3},
|
||||
{ 26000000, 480000000, 960, 26, 0, 12},
|
||||
{ 0, 0, 0, 0, 0, 0 },
|
||||
{ 12000000, 480000000, 960, 12, 1, 12 },
|
||||
{ 13000000, 480000000, 960, 13, 1, 12 },
|
||||
{ 16800000, 480000000, 400, 7, 1, 5 },
|
||||
{ 19200000, 480000000, 200, 4, 1, 3 },
|
||||
{ 26000000, 480000000, 960, 26, 1, 12 },
|
||||
{ 0, 0, 0, 0, 0, 0 },
|
||||
};
|
||||
|
||||
static struct tegra_clk_pll_freq_table pll_x_freq_table[] = {
|
||||
/* 1.7 GHz */
|
||||
{ 12000000, 1700000000, 850, 6, 0, 8},
|
||||
{ 13000000, 1700000000, 915, 7, 0, 8}, /* actual: 1699.2 MHz */
|
||||
{ 16800000, 1700000000, 708, 7, 0, 8}, /* actual: 1699.2 MHz */
|
||||
{ 19200000, 1700000000, 885, 10, 0, 8}, /* actual: 1699.2 MHz */
|
||||
{ 26000000, 1700000000, 850, 13, 0, 8},
|
||||
|
||||
{ 12000000, 1700000000, 850, 6, 1, 8 },
|
||||
{ 13000000, 1700000000, 915, 7, 1, 8 }, /* actual: 1699.2 MHz */
|
||||
{ 16800000, 1700000000, 708, 7, 1, 8 }, /* actual: 1699.2 MHz */
|
||||
{ 19200000, 1700000000, 885, 10, 1, 8 }, /* actual: 1699.2 MHz */
|
||||
{ 26000000, 1700000000, 850, 13, 1, 8 },
|
||||
/* 1.6 GHz */
|
||||
{ 12000000, 1600000000, 800, 6, 0, 8},
|
||||
{ 13000000, 1600000000, 738, 6, 0, 8}, /* actual: 1599.0 MHz */
|
||||
{ 16800000, 1600000000, 857, 9, 0, 8}, /* actual: 1599.7 MHz */
|
||||
{ 19200000, 1600000000, 500, 6, 0, 8},
|
||||
{ 26000000, 1600000000, 800, 13, 0, 8},
|
||||
|
||||
{ 12000000, 1600000000, 800, 6, 1, 8 },
|
||||
{ 13000000, 1600000000, 738, 6, 1, 8 }, /* actual: 1599.0 MHz */
|
||||
{ 16800000, 1600000000, 857, 9, 1, 8 }, /* actual: 1599.7 MHz */
|
||||
{ 19200000, 1600000000, 500, 6, 1, 8 },
|
||||
{ 26000000, 1600000000, 800, 13, 1, 8 },
|
||||
/* 1.5 GHz */
|
||||
{ 12000000, 1500000000, 750, 6, 0, 8},
|
||||
{ 13000000, 1500000000, 923, 8, 0, 8}, /* actual: 1499.8 MHz */
|
||||
{ 16800000, 1500000000, 625, 7, 0, 8},
|
||||
{ 19200000, 1500000000, 625, 8, 0, 8},
|
||||
{ 26000000, 1500000000, 750, 13, 0, 8},
|
||||
|
||||
{ 12000000, 1500000000, 750, 6, 1, 8 },
|
||||
{ 13000000, 1500000000, 923, 8, 1, 8 }, /* actual: 1499.8 MHz */
|
||||
{ 16800000, 1500000000, 625, 7, 1, 8 },
|
||||
{ 19200000, 1500000000, 625, 8, 1, 8 },
|
||||
{ 26000000, 1500000000, 750, 13, 1, 8 },
|
||||
/* 1.4 GHz */
|
||||
{ 12000000, 1400000000, 700, 6, 0, 8},
|
||||
{ 13000000, 1400000000, 969, 9, 0, 8}, /* actual: 1399.7 MHz */
|
||||
{ 16800000, 1400000000, 1000, 12, 0, 8},
|
||||
{ 19200000, 1400000000, 875, 12, 0, 8},
|
||||
{ 26000000, 1400000000, 700, 13, 0, 8},
|
||||
|
||||
{ 12000000, 1400000000, 700, 6, 1, 8 },
|
||||
{ 13000000, 1400000000, 969, 9, 1, 8 }, /* actual: 1399.7 MHz */
|
||||
{ 16800000, 1400000000, 1000, 12, 1, 8 },
|
||||
{ 19200000, 1400000000, 875, 12, 1, 8 },
|
||||
{ 26000000, 1400000000, 700, 13, 1, 8 },
|
||||
/* 1.3 GHz */
|
||||
{ 12000000, 1300000000, 975, 9, 0, 8},
|
||||
{ 13000000, 1300000000, 1000, 10, 0, 8},
|
||||
{ 16800000, 1300000000, 928, 12, 0, 8}, /* actual: 1299.2 MHz */
|
||||
{ 19200000, 1300000000, 812, 12, 0, 8}, /* actual: 1299.2 MHz */
|
||||
{ 26000000, 1300000000, 650, 13, 0, 8},
|
||||
|
||||
{ 12000000, 1300000000, 975, 9, 1, 8 },
|
||||
{ 13000000, 1300000000, 1000, 10, 1, 8 },
|
||||
{ 16800000, 1300000000, 928, 12, 1, 8 }, /* actual: 1299.2 MHz */
|
||||
{ 19200000, 1300000000, 812, 12, 1, 8 }, /* actual: 1299.2 MHz */
|
||||
{ 26000000, 1300000000, 650, 13, 1, 8 },
|
||||
/* 1.2 GHz */
|
||||
{ 12000000, 1200000000, 1000, 10, 0, 8},
|
||||
{ 13000000, 1200000000, 923, 10, 0, 8}, /* actual: 1199.9 MHz */
|
||||
{ 16800000, 1200000000, 1000, 14, 0, 8},
|
||||
{ 19200000, 1200000000, 1000, 16, 0, 8},
|
||||
{ 26000000, 1200000000, 600, 13, 0, 8},
|
||||
|
||||
{ 12000000, 1200000000, 1000, 10, 1, 8 },
|
||||
{ 13000000, 1200000000, 923, 10, 1, 8 }, /* actual: 1199.9 MHz */
|
||||
{ 16800000, 1200000000, 1000, 14, 1, 8 },
|
||||
{ 19200000, 1200000000, 1000, 16, 1, 8 },
|
||||
{ 26000000, 1200000000, 600, 13, 1, 8 },
|
||||
/* 1.1 GHz */
|
||||
{ 12000000, 1100000000, 825, 9, 0, 8},
|
||||
{ 13000000, 1100000000, 846, 10, 0, 8}, /* actual: 1099.8 MHz */
|
||||
{ 16800000, 1100000000, 982, 15, 0, 8}, /* actual: 1099.8 MHz */
|
||||
{ 19200000, 1100000000, 859, 15, 0, 8}, /* actual: 1099.5 MHz */
|
||||
{ 26000000, 1100000000, 550, 13, 0, 8},
|
||||
|
||||
{ 12000000, 1100000000, 825, 9, 1, 8 },
|
||||
{ 13000000, 1100000000, 846, 10, 1, 8 }, /* actual: 1099.8 MHz */
|
||||
{ 16800000, 1100000000, 982, 15, 1, 8 }, /* actual: 1099.8 MHz */
|
||||
{ 19200000, 1100000000, 859, 15, 1, 8 }, /* actual: 1099.5 MHz */
|
||||
{ 26000000, 1100000000, 550, 13, 1, 8 },
|
||||
/* 1 GHz */
|
||||
{ 12000000, 1000000000, 1000, 12, 0, 8},
|
||||
{ 13000000, 1000000000, 1000, 13, 0, 8},
|
||||
{ 16800000, 1000000000, 833, 14, 0, 8}, /* actual: 999.6 MHz */
|
||||
{ 19200000, 1000000000, 625, 12, 0, 8},
|
||||
{ 26000000, 1000000000, 1000, 26, 0, 8},
|
||||
{ 12000000, 1000000000, 1000, 12, 1, 8 },
|
||||
{ 13000000, 1000000000, 1000, 13, 1, 8 },
|
||||
{ 16800000, 1000000000, 833, 14, 1, 8 }, /* actual: 999.6 MHz */
|
||||
{ 19200000, 1000000000, 625, 12, 1, 8 },
|
||||
{ 26000000, 1000000000, 1000, 26, 1, 8 },
|
||||
{ 0, 0, 0, 0, 0, 0 },
|
||||
};
|
||||
|
||||
{ 0, 0, 0, 0, 0, 0 },
|
||||
static const struct pdiv_map plle_p[] = {
|
||||
{ .pdiv = 18, .hw_val = 18 },
|
||||
{ .pdiv = 24, .hw_val = 24 },
|
||||
{ .pdiv = 0, .hw_val = 0 },
|
||||
};
|
||||
|
||||
static struct tegra_clk_pll_freq_table pll_e_freq_table[] = {
|
||||
/* PLLE special case: use cpcon field to store cml divider value */
|
||||
{ 12000000, 100000000, 150, 1, 18, 11},
|
||||
{ 216000000, 100000000, 200, 18, 24, 13},
|
||||
{ 0, 0, 0, 0, 0, 0 },
|
||||
{ 12000000, 100000000, 150, 1, 18, 11 },
|
||||
{ 216000000, 100000000, 200, 18, 24, 13 },
|
||||
{ 0, 0, 0, 0, 0, 0 },
|
||||
};
|
||||
|
||||
/* PLL parameters */
|
||||
|
|
@ -422,7 +426,8 @@ static struct tegra_clk_pll_params pll_c_params = {
|
|||
.lock_enable_bit_idx = PLL_MISC_LOCK_ENABLE,
|
||||
.lock_delay = 300,
|
||||
.freq_table = pll_c_freq_table,
|
||||
.flags = TEGRA_PLL_HAS_CPCON | TEGRA_PLL_USE_LOCK,
|
||||
.flags = TEGRA_PLL_HAS_CPCON | TEGRA_PLL_USE_LOCK |
|
||||
TEGRA_PLL_HAS_LOCK_ENABLE,
|
||||
};
|
||||
|
||||
static struct div_nmp pllm_nmp = {
|
||||
|
|
@ -454,7 +459,8 @@ static struct tegra_clk_pll_params pll_m_params = {
|
|||
.pmc_divp_reg = PMC_PLLM_WB0_OVERRIDE,
|
||||
.freq_table = pll_m_freq_table,
|
||||
.flags = TEGRA_PLLM | TEGRA_PLL_HAS_CPCON |
|
||||
TEGRA_PLL_SET_DCCON | TEGRA_PLL_USE_LOCK,
|
||||
TEGRA_PLL_SET_DCCON | TEGRA_PLL_USE_LOCK |
|
||||
TEGRA_PLL_HAS_LOCK_ENABLE | TEGRA_PLL_FIXED,
|
||||
};
|
||||
|
||||
static struct tegra_clk_pll_params pll_p_params = {
|
||||
|
|
@ -470,7 +476,8 @@ static struct tegra_clk_pll_params pll_p_params = {
|
|||
.lock_enable_bit_idx = PLL_MISC_LOCK_ENABLE,
|
||||
.lock_delay = 300,
|
||||
.freq_table = pll_p_freq_table,
|
||||
.flags = TEGRA_PLL_FIXED | TEGRA_PLL_HAS_CPCON | TEGRA_PLL_USE_LOCK,
|
||||
.flags = TEGRA_PLL_FIXED | TEGRA_PLL_HAS_CPCON | TEGRA_PLL_USE_LOCK |
|
||||
TEGRA_PLL_HAS_LOCK_ENABLE,
|
||||
.fixed_rate = 408000000,
|
||||
};
|
||||
|
||||
|
|
@ -487,7 +494,8 @@ static struct tegra_clk_pll_params pll_a_params = {
|
|||
.lock_enable_bit_idx = PLL_MISC_LOCK_ENABLE,
|
||||
.lock_delay = 300,
|
||||
.freq_table = pll_a_freq_table,
|
||||
.flags = TEGRA_PLL_HAS_CPCON | TEGRA_PLL_USE_LOCK,
|
||||
.flags = TEGRA_PLL_HAS_CPCON | TEGRA_PLL_USE_LOCK |
|
||||
TEGRA_PLL_HAS_LOCK_ENABLE,
|
||||
};
|
||||
|
||||
static struct tegra_clk_pll_params pll_d_params = {
|
||||
|
|
@ -504,8 +512,7 @@ static struct tegra_clk_pll_params pll_d_params = {
|
|||
.lock_delay = 1000,
|
||||
.freq_table = pll_d_freq_table,
|
||||
.flags = TEGRA_PLL_HAS_CPCON | TEGRA_PLL_SET_LFCON |
|
||||
TEGRA_PLL_USE_LOCK,
|
||||
|
||||
TEGRA_PLL_USE_LOCK | TEGRA_PLL_HAS_LOCK_ENABLE,
|
||||
};
|
||||
|
||||
static struct tegra_clk_pll_params pll_d2_params = {
|
||||
|
|
@ -522,7 +529,7 @@ static struct tegra_clk_pll_params pll_d2_params = {
|
|||
.lock_delay = 1000,
|
||||
.freq_table = pll_d_freq_table,
|
||||
.flags = TEGRA_PLL_HAS_CPCON | TEGRA_PLL_SET_LFCON |
|
||||
TEGRA_PLL_USE_LOCK,
|
||||
TEGRA_PLL_USE_LOCK | TEGRA_PLL_HAS_LOCK_ENABLE,
|
||||
};
|
||||
|
||||
static struct tegra_clk_pll_params pll_u_params = {
|
||||
|
|
@ -539,7 +546,8 @@ static struct tegra_clk_pll_params pll_u_params = {
|
|||
.lock_delay = 1000,
|
||||
.pdiv_tohw = pllu_p,
|
||||
.freq_table = pll_u_freq_table,
|
||||
.flags = TEGRA_PLLU | TEGRA_PLL_HAS_CPCON | TEGRA_PLL_SET_LFCON,
|
||||
.flags = TEGRA_PLLU | TEGRA_PLL_HAS_CPCON | TEGRA_PLL_SET_LFCON |
|
||||
TEGRA_PLL_HAS_LOCK_ENABLE,
|
||||
};
|
||||
|
||||
static struct tegra_clk_pll_params pll_x_params = {
|
||||
|
|
@ -556,7 +564,7 @@ static struct tegra_clk_pll_params pll_x_params = {
|
|||
.lock_delay = 300,
|
||||
.freq_table = pll_x_freq_table,
|
||||
.flags = TEGRA_PLL_HAS_CPCON | TEGRA_PLL_SET_DCCON |
|
||||
TEGRA_PLL_USE_LOCK,
|
||||
TEGRA_PLL_USE_LOCK | TEGRA_PLL_HAS_LOCK_ENABLE,
|
||||
};
|
||||
|
||||
static struct tegra_clk_pll_params pll_e_params = {
|
||||
|
|
@ -571,19 +579,21 @@ static struct tegra_clk_pll_params pll_e_params = {
|
|||
.lock_mask = PLLE_MISC_LOCK,
|
||||
.lock_enable_bit_idx = PLLE_MISC_LOCK_ENABLE,
|
||||
.lock_delay = 300,
|
||||
.pdiv_tohw = plle_p,
|
||||
.freq_table = pll_e_freq_table,
|
||||
.flags = TEGRA_PLLE_CONFIGURE | TEGRA_PLL_FIXED,
|
||||
.flags = TEGRA_PLLE_CONFIGURE | TEGRA_PLL_FIXED |
|
||||
TEGRA_PLL_HAS_LOCK_ENABLE | TEGRA_PLL_LOCK_MISC,
|
||||
.fixed_rate = 100000000,
|
||||
};
|
||||
|
||||
static unsigned long tegra30_input_freq[] = {
|
||||
[0] = 13000000,
|
||||
[1] = 16800000,
|
||||
[4] = 19200000,
|
||||
[5] = 38400000,
|
||||
[8] = 12000000,
|
||||
[9] = 48000000,
|
||||
[12] = 260000000,
|
||||
[ 0] = 13000000,
|
||||
[ 1] = 16800000,
|
||||
[ 4] = 19200000,
|
||||
[ 5] = 38400000,
|
||||
[ 8] = 12000000,
|
||||
[ 9] = 48000000,
|
||||
[12] = 26000000,
|
||||
};
|
||||
|
||||
static struct tegra_devclk devclks[] __initdata = {
|
||||
|
|
@ -861,13 +871,12 @@ static struct tegra_clk tegra30_clks[tegra_clk_max] __initdata = {
|
|||
[tegra_clk_pll_p_out4] = { .dt_id = TEGRA30_CLK_PLL_P_OUT4, .present = true },
|
||||
[tegra_clk_pll_a] = { .dt_id = TEGRA30_CLK_PLL_A, .present = true },
|
||||
[tegra_clk_pll_a_out0] = { .dt_id = TEGRA30_CLK_PLL_A_OUT0, .present = true },
|
||||
|
||||
};
|
||||
|
||||
static void tegra30_utmi_param_configure(void)
|
||||
{
|
||||
unsigned int i;
|
||||
u32 reg;
|
||||
int i;
|
||||
|
||||
for (i = 0; i < ARRAY_SIZE(utmi_parameters); i++) {
|
||||
if (input_freq == utmi_parameters[i].osc_frequency)
|
||||
|
|
@ -917,7 +926,7 @@ static void tegra30_utmi_param_configure(void)
|
|||
writel_relaxed(reg, clk_base + UTMIP_PLL_CFG1);
|
||||
}
|
||||
|
||||
static const char *pll_e_parents[] = {"pll_ref", "pll_p"};
|
||||
static const char *pll_e_parents[] = { "pll_ref", "pll_p" };
|
||||
|
||||
static void __init tegra30_pll_init(void)
|
||||
{
|
||||
|
|
@ -925,7 +934,7 @@ static void __init tegra30_pll_init(void)
|
|||
|
||||
/* PLLC */
|
||||
clk = tegra_clk_register_pll("pll_c", "pll_ref", clk_base, pmc_base, 0,
|
||||
&pll_c_params, NULL);
|
||||
&pll_c_params, NULL);
|
||||
clks[TEGRA30_CLK_PLL_C] = clk;
|
||||
|
||||
/* PLLC_OUT1 */
|
||||
|
|
@ -1135,7 +1144,7 @@ static void __init tegra30_periph_clk_init(void)
|
|||
{
|
||||
struct tegra_periph_init_data *data;
|
||||
struct clk *clk;
|
||||
int i;
|
||||
unsigned int i;
|
||||
|
||||
/* dsia */
|
||||
clk = tegra_clk_register_periph_gate("dsia", "pll_d_out0", 0, clk_base,
|
||||
|
|
@ -1224,7 +1233,6 @@ static void tegra30_cpu_out_of_reset(u32 cpu)
|
|||
wmb();
|
||||
}
|
||||
|
||||
|
||||
static void tegra30_enable_cpu_clock(u32 cpu)
|
||||
{
|
||||
unsigned int reg;
|
||||
|
|
@ -1237,7 +1245,6 @@ static void tegra30_enable_cpu_clock(u32 cpu)
|
|||
|
||||
static void tegra30_disable_cpu_clock(u32 cpu)
|
||||
{
|
||||
|
||||
unsigned int reg;
|
||||
|
||||
reg = readl(clk_base + TEGRA_CLK_RST_CONTROLLER_CLK_CPU_CMPLX);
|
||||
|
|
@ -1268,7 +1275,7 @@ static void tegra30_cpu_clock_suspend(void)
|
|||
/* switch coresite to clk_m, save off original source */
|
||||
tegra30_cpu_clk_sctx.clk_csite_src =
|
||||
readl(clk_base + CLK_RESET_SOURCE_CSITE);
|
||||
writel(3<<30, clk_base + CLK_RESET_SOURCE_CSITE);
|
||||
writel(3 << 30, clk_base + CLK_RESET_SOURCE_CSITE);
|
||||
|
||||
tegra30_cpu_clk_sctx.cpu_burst =
|
||||
readl(clk_base + CLK_RESET_CCLK_BURST);
|
||||
|
|
@ -1335,44 +1342,45 @@ static struct tegra_cpu_car_ops tegra30_cpu_car_ops = {
|
|||
};
|
||||
|
||||
static struct tegra_clk_init_table init_table[] __initdata = {
|
||||
{TEGRA30_CLK_UARTA, TEGRA30_CLK_PLL_P, 408000000, 0},
|
||||
{TEGRA30_CLK_UARTB, TEGRA30_CLK_PLL_P, 408000000, 0},
|
||||
{TEGRA30_CLK_UARTC, TEGRA30_CLK_PLL_P, 408000000, 0},
|
||||
{TEGRA30_CLK_UARTD, TEGRA30_CLK_PLL_P, 408000000, 0},
|
||||
{TEGRA30_CLK_UARTE, TEGRA30_CLK_PLL_P, 408000000, 0},
|
||||
{TEGRA30_CLK_PLL_A, TEGRA30_CLK_CLK_MAX, 564480000, 1},
|
||||
{TEGRA30_CLK_PLL_A_OUT0, TEGRA30_CLK_CLK_MAX, 11289600, 1},
|
||||
{TEGRA30_CLK_EXTERN1, TEGRA30_CLK_PLL_A_OUT0, 0, 1},
|
||||
{TEGRA30_CLK_CLK_OUT_1_MUX, TEGRA30_CLK_EXTERN1, 0, 0},
|
||||
{TEGRA30_CLK_CLK_OUT_1, TEGRA30_CLK_CLK_MAX, 0, 1},
|
||||
{TEGRA30_CLK_BLINK, TEGRA30_CLK_CLK_MAX, 0, 1},
|
||||
{TEGRA30_CLK_I2S0, TEGRA30_CLK_PLL_A_OUT0, 11289600, 0},
|
||||
{TEGRA30_CLK_I2S1, TEGRA30_CLK_PLL_A_OUT0, 11289600, 0},
|
||||
{TEGRA30_CLK_I2S2, TEGRA30_CLK_PLL_A_OUT0, 11289600, 0},
|
||||
{TEGRA30_CLK_I2S3, TEGRA30_CLK_PLL_A_OUT0, 11289600, 0},
|
||||
{TEGRA30_CLK_I2S4, TEGRA30_CLK_PLL_A_OUT0, 11289600, 0},
|
||||
{TEGRA30_CLK_SDMMC1, TEGRA30_CLK_PLL_P, 48000000, 0},
|
||||
{TEGRA30_CLK_SDMMC2, TEGRA30_CLK_PLL_P, 48000000, 0},
|
||||
{TEGRA30_CLK_SDMMC3, TEGRA30_CLK_PLL_P, 48000000, 0},
|
||||
{TEGRA30_CLK_PLL_M, TEGRA30_CLK_CLK_MAX, 0, 1},
|
||||
{TEGRA30_CLK_PCLK, TEGRA30_CLK_CLK_MAX, 0, 1},
|
||||
{TEGRA30_CLK_CSITE, TEGRA30_CLK_CLK_MAX, 0, 1},
|
||||
{TEGRA30_CLK_EMC, TEGRA30_CLK_CLK_MAX, 0, 1},
|
||||
{TEGRA30_CLK_MSELECT, TEGRA30_CLK_CLK_MAX, 0, 1},
|
||||
{TEGRA30_CLK_SBC1, TEGRA30_CLK_PLL_P, 100000000, 0},
|
||||
{TEGRA30_CLK_SBC2, TEGRA30_CLK_PLL_P, 100000000, 0},
|
||||
{TEGRA30_CLK_SBC3, TEGRA30_CLK_PLL_P, 100000000, 0},
|
||||
{TEGRA30_CLK_SBC4, TEGRA30_CLK_PLL_P, 100000000, 0},
|
||||
{TEGRA30_CLK_SBC5, TEGRA30_CLK_PLL_P, 100000000, 0},
|
||||
{TEGRA30_CLK_SBC6, TEGRA30_CLK_PLL_P, 100000000, 0},
|
||||
{TEGRA30_CLK_HOST1X, TEGRA30_CLK_PLL_C, 150000000, 0},
|
||||
{TEGRA30_CLK_DISP1, TEGRA30_CLK_PLL_P, 600000000, 0},
|
||||
{TEGRA30_CLK_DISP2, TEGRA30_CLK_PLL_P, 600000000, 0},
|
||||
{TEGRA30_CLK_TWD, TEGRA30_CLK_CLK_MAX, 0, 1},
|
||||
{TEGRA30_CLK_GR2D, TEGRA30_CLK_PLL_C, 300000000, 0},
|
||||
{TEGRA30_CLK_GR3D, TEGRA30_CLK_PLL_C, 300000000, 0},
|
||||
{TEGRA30_CLK_GR3D2, TEGRA30_CLK_PLL_C, 300000000, 0},
|
||||
{TEGRA30_CLK_CLK_MAX, TEGRA30_CLK_CLK_MAX, 0, 0}, /* This MUST be the last entry. */
|
||||
{ TEGRA30_CLK_UARTA, TEGRA30_CLK_PLL_P, 408000000, 0 },
|
||||
{ TEGRA30_CLK_UARTB, TEGRA30_CLK_PLL_P, 408000000, 0 },
|
||||
{ TEGRA30_CLK_UARTC, TEGRA30_CLK_PLL_P, 408000000, 0 },
|
||||
{ TEGRA30_CLK_UARTD, TEGRA30_CLK_PLL_P, 408000000, 0 },
|
||||
{ TEGRA30_CLK_UARTE, TEGRA30_CLK_PLL_P, 408000000, 0 },
|
||||
{ TEGRA30_CLK_PLL_A, TEGRA30_CLK_CLK_MAX, 564480000, 1 },
|
||||
{ TEGRA30_CLK_PLL_A_OUT0, TEGRA30_CLK_CLK_MAX, 11289600, 1 },
|
||||
{ TEGRA30_CLK_EXTERN1, TEGRA30_CLK_PLL_A_OUT0, 0, 1 },
|
||||
{ TEGRA30_CLK_CLK_OUT_1_MUX, TEGRA30_CLK_EXTERN1, 0, 0 },
|
||||
{ TEGRA30_CLK_CLK_OUT_1, TEGRA30_CLK_CLK_MAX, 0, 1 },
|
||||
{ TEGRA30_CLK_BLINK, TEGRA30_CLK_CLK_MAX, 0, 1 },
|
||||
{ TEGRA30_CLK_I2S0, TEGRA30_CLK_PLL_A_OUT0, 11289600, 0 },
|
||||
{ TEGRA30_CLK_I2S1, TEGRA30_CLK_PLL_A_OUT0, 11289600, 0 },
|
||||
{ TEGRA30_CLK_I2S2, TEGRA30_CLK_PLL_A_OUT0, 11289600, 0 },
|
||||
{ TEGRA30_CLK_I2S3, TEGRA30_CLK_PLL_A_OUT0, 11289600, 0 },
|
||||
{ TEGRA30_CLK_I2S4, TEGRA30_CLK_PLL_A_OUT0, 11289600, 0 },
|
||||
{ TEGRA30_CLK_SDMMC1, TEGRA30_CLK_PLL_P, 48000000, 0 },
|
||||
{ TEGRA30_CLK_SDMMC2, TEGRA30_CLK_PLL_P, 48000000, 0 },
|
||||
{ TEGRA30_CLK_SDMMC3, TEGRA30_CLK_PLL_P, 48000000, 0 },
|
||||
{ TEGRA30_CLK_PLL_M, TEGRA30_CLK_CLK_MAX, 0, 1 },
|
||||
{ TEGRA30_CLK_PCLK, TEGRA30_CLK_CLK_MAX, 0, 1 },
|
||||
{ TEGRA30_CLK_CSITE, TEGRA30_CLK_CLK_MAX, 0, 1 },
|
||||
{ TEGRA30_CLK_EMC, TEGRA30_CLK_CLK_MAX, 0, 1 },
|
||||
{ TEGRA30_CLK_MSELECT, TEGRA30_CLK_CLK_MAX, 0, 1 },
|
||||
{ TEGRA30_CLK_SBC1, TEGRA30_CLK_PLL_P, 100000000, 0 },
|
||||
{ TEGRA30_CLK_SBC2, TEGRA30_CLK_PLL_P, 100000000, 0 },
|
||||
{ TEGRA30_CLK_SBC3, TEGRA30_CLK_PLL_P, 100000000, 0 },
|
||||
{ TEGRA30_CLK_SBC4, TEGRA30_CLK_PLL_P, 100000000, 0 },
|
||||
{ TEGRA30_CLK_SBC5, TEGRA30_CLK_PLL_P, 100000000, 0 },
|
||||
{ TEGRA30_CLK_SBC6, TEGRA30_CLK_PLL_P, 100000000, 0 },
|
||||
{ TEGRA30_CLK_HOST1X, TEGRA30_CLK_PLL_C, 150000000, 0 },
|
||||
{ TEGRA30_CLK_DISP1, TEGRA30_CLK_PLL_P, 600000000, 0 },
|
||||
{ TEGRA30_CLK_DISP2, TEGRA30_CLK_PLL_P, 600000000, 0 },
|
||||
{ TEGRA30_CLK_TWD, TEGRA30_CLK_CLK_MAX, 0, 1 },
|
||||
{ TEGRA30_CLK_GR2D, TEGRA30_CLK_PLL_C, 300000000, 0 },
|
||||
{ TEGRA30_CLK_GR3D, TEGRA30_CLK_PLL_C, 300000000, 0 },
|
||||
{ TEGRA30_CLK_GR3D2, TEGRA30_CLK_PLL_C, 300000000, 0 },
|
||||
/* must be the last entry */
|
||||
{ TEGRA30_CLK_CLK_MAX, TEGRA30_CLK_CLK_MAX, 0, 0 },
|
||||
};
|
||||
|
||||
static void __init tegra30_clock_apply_init_table(void)
|
||||
|
|
@ -1397,12 +1405,13 @@ static struct tegra_clk_duplicate tegra_clk_duplicates[] = {
|
|||
TEGRA_CLK_DUPLICATE(TEGRA30_CLK_CML1, "tegra_sata_cml", NULL),
|
||||
TEGRA_CLK_DUPLICATE(TEGRA30_CLK_CML0, "tegra_pcie", "cml"),
|
||||
TEGRA_CLK_DUPLICATE(TEGRA30_CLK_VCP, "nvavp", "vcp"),
|
||||
TEGRA_CLK_DUPLICATE(TEGRA30_CLK_CLK_MAX, NULL, NULL), /* MUST be the last entry */
|
||||
/* must be the last entry */
|
||||
TEGRA_CLK_DUPLICATE(TEGRA30_CLK_CLK_MAX, NULL, NULL),
|
||||
};
|
||||
|
||||
static const struct of_device_id pmc_match[] __initconst = {
|
||||
{ .compatible = "nvidia,tegra30-pmc" },
|
||||
{},
|
||||
{ },
|
||||
};
|
||||
|
||||
static struct tegra_audio_clk_info tegra30_audio_plls[] = {
|
||||
|
|
@ -1441,7 +1450,6 @@ static void __init tegra30_clock_init(struct device_node *np)
|
|||
NULL) < 0)
|
||||
return;
|
||||
|
||||
|
||||
tegra_fixed_clk_init(tegra30_clks);
|
||||
tegra30_pll_init();
|
||||
tegra30_super_clk_init();
|
||||
|
|
|
|||
|
|
@ -110,14 +110,16 @@ struct clk *tegra_clk_register_mc(const char *name, const char *parent_name,
|
|||
* @m: input divider
|
||||
* @p: post divider
|
||||
* @cpcon: charge pump current
|
||||
* @sdm_data: fraction divider setting (0 = disabled)
|
||||
*/
|
||||
struct tegra_clk_pll_freq_table {
|
||||
unsigned long input_rate;
|
||||
unsigned long output_rate;
|
||||
u16 n;
|
||||
u32 n;
|
||||
u16 m;
|
||||
u8 p;
|
||||
u8 cpcon;
|
||||
u16 sdm_data;
|
||||
};
|
||||
|
||||
/**
|
||||
|
|
@ -156,6 +158,10 @@ struct div_nmp {
|
|||
u8 override_divp_shift;
|
||||
};
|
||||
|
||||
#define MAX_PLL_MISC_REG_COUNT 6
|
||||
|
||||
struct tegra_clk_pll;
|
||||
|
||||
/**
|
||||
* struct tegra_clk_pll_params - PLL parameters
|
||||
*
|
||||
|
|
@ -172,6 +178,14 @@ struct div_nmp {
|
|||
* @lock_enable_bit_idx: Bit index to enable PLL lock
|
||||
* @iddq_reg: PLL IDDQ register offset
|
||||
* @iddq_bit_idx: Bit index to enable PLL IDDQ
|
||||
* @reset_reg: Register offset of where RESET bit is
|
||||
* @reset_bit_idx: Shift of reset bit in reset_reg
|
||||
* @sdm_din_reg: Register offset where SDM settings are
|
||||
* @sdm_din_mask: Mask of SDM divider bits
|
||||
* @sdm_ctrl_reg: Register offset where SDM enable is
|
||||
* @sdm_ctrl_en_mask: Mask of SDM enable bit
|
||||
* @ssc_ctrl_reg: Register offset where SSC settings are
|
||||
* @ssc_ctrl_en_mask: Mask of SSC enable bit
|
||||
* @aux_reg: AUX register offset
|
||||
* @dyn_ramp_reg: Dynamic ramp control register offset
|
||||
* @ext_misc_reg: Miscellaneous control register offsets
|
||||
|
|
@ -182,10 +196,27 @@ struct div_nmp {
|
|||
* @stepb_shift: Dynamic ramp step B field shift
|
||||
* @lock_delay: Delay in us if PLL lock is not used
|
||||
* @max_p: maximum value for the p divider
|
||||
* @defaults_set: Boolean signaling all reg defaults for PLL set.
|
||||
* @pdiv_tohw: mapping of p divider to register values
|
||||
* @div_nmp: offsets and widths on n, m and p fields
|
||||
* @freq_table: array of frequencies supported by PLL
|
||||
* @fixed_rate: PLL rate if it is fixed
|
||||
* @mdiv_default: Default value for fixed mdiv for this PLL
|
||||
* @round_p_to_pdiv: Callback used to round p to the closed pdiv
|
||||
* @set_gain: Callback to adjust N div for SDM enabled
|
||||
* PLL's based on fractional divider value.
|
||||
* @calc_rate: Callback used to change how out of table
|
||||
* rates (dividers and multipler) are calculated.
|
||||
* @adjust_vco: Callback to adjust the programming range of the
|
||||
* divider range (if SDM is present)
|
||||
* @set_defaults: Callback which will try to initialize PLL
|
||||
* registers to sane default values. This is first
|
||||
* tried during PLL registration, but if the PLL
|
||||
* is already enabled, it will be done the first
|
||||
* time the rate is changed while the PLL is
|
||||
* disabled.
|
||||
* @dyn_ramp: Callback which can be used to define a custom
|
||||
* dynamic ramp function for a given PLL.
|
||||
*
|
||||
* Flags:
|
||||
* TEGRA_PLL_USE_LOCK - This flag indicated to use lock bits for
|
||||
|
|
@ -207,6 +238,11 @@ struct div_nmp {
|
|||
* base register.
|
||||
* TEGRA_PLL_BYPASS - PLL has bypass bit
|
||||
* TEGRA_PLL_HAS_LOCK_ENABLE - PLL has bit to enable lock monitoring
|
||||
* TEGRA_MDIV_NEW - Switch to new method for calculating fixed mdiv
|
||||
* it may be more accurate (especially if SDM present)
|
||||
* TEGRA_PLLMB - PLLMB has should be treated similar to PLLM. This
|
||||
* flag indicated that it is PLLMB.
|
||||
* TEGRA_PLL_VCO_OUT - Used to indicate that the PLL has a VCO output
|
||||
*/
|
||||
struct tegra_clk_pll_params {
|
||||
unsigned long input_min;
|
||||
|
|
@ -223,9 +259,17 @@ struct tegra_clk_pll_params {
|
|||
u32 lock_enable_bit_idx;
|
||||
u32 iddq_reg;
|
||||
u32 iddq_bit_idx;
|
||||
u32 reset_reg;
|
||||
u32 reset_bit_idx;
|
||||
u32 sdm_din_reg;
|
||||
u32 sdm_din_mask;
|
||||
u32 sdm_ctrl_reg;
|
||||
u32 sdm_ctrl_en_mask;
|
||||
u32 ssc_ctrl_reg;
|
||||
u32 ssc_ctrl_en_mask;
|
||||
u32 aux_reg;
|
||||
u32 dyn_ramp_reg;
|
||||
u32 ext_misc_reg[3];
|
||||
u32 ext_misc_reg[MAX_PLL_MISC_REG_COUNT];
|
||||
u32 pmc_divnm_reg;
|
||||
u32 pmc_divp_reg;
|
||||
u32 flags;
|
||||
|
|
@ -233,10 +277,22 @@ struct tegra_clk_pll_params {
|
|||
int stepb_shift;
|
||||
int lock_delay;
|
||||
int max_p;
|
||||
struct pdiv_map *pdiv_tohw;
|
||||
bool defaults_set;
|
||||
const struct pdiv_map *pdiv_tohw;
|
||||
struct div_nmp *div_nmp;
|
||||
struct tegra_clk_pll_freq_table *freq_table;
|
||||
unsigned long fixed_rate;
|
||||
u16 mdiv_default;
|
||||
u32 (*round_p_to_pdiv)(u32 p, u32 *pdiv);
|
||||
void (*set_gain)(struct tegra_clk_pll_freq_table *cfg);
|
||||
int (*calc_rate)(struct clk_hw *hw,
|
||||
struct tegra_clk_pll_freq_table *cfg,
|
||||
unsigned long rate, unsigned long parent_rate);
|
||||
unsigned long (*adjust_vco)(struct tegra_clk_pll_params *pll_params,
|
||||
unsigned long parent_rate);
|
||||
void (*set_defaults)(struct tegra_clk_pll *pll);
|
||||
int (*dyn_ramp)(struct tegra_clk_pll *pll,
|
||||
struct tegra_clk_pll_freq_table *cfg);
|
||||
};
|
||||
|
||||
#define TEGRA_PLL_USE_LOCK BIT(0)
|
||||
|
|
@ -250,6 +306,9 @@ struct tegra_clk_pll_params {
|
|||
#define TEGRA_PLL_LOCK_MISC BIT(8)
|
||||
#define TEGRA_PLL_BYPASS BIT(9)
|
||||
#define TEGRA_PLL_HAS_LOCK_ENABLE BIT(10)
|
||||
#define TEGRA_MDIV_NEW BIT(11)
|
||||
#define TEGRA_PLLMB BIT(12)
|
||||
#define TEGRA_PLL_VCO_OUT BIT(13)
|
||||
|
||||
/**
|
||||
* struct tegra_clk_pll - Tegra PLL clock
|
||||
|
|
@ -303,6 +362,12 @@ struct clk *tegra_clk_register_pllxc(const char *name, const char *parent_name,
|
|||
struct tegra_clk_pll_params *pll_params,
|
||||
spinlock_t *lock);
|
||||
|
||||
struct clk *tegra_clk_register_pllxc_tegra210(const char *name,
|
||||
const char *parent_name, void __iomem *clk_base,
|
||||
void __iomem *pmc, unsigned long flags,
|
||||
struct tegra_clk_pll_params *pll_params,
|
||||
spinlock_t *lock);
|
||||
|
||||
struct clk *tegra_clk_register_pllm(const char *name, const char *parent_name,
|
||||
void __iomem *clk_base, void __iomem *pmc,
|
||||
unsigned long flags,
|
||||
|
|
@ -327,11 +392,35 @@ struct clk *tegra_clk_register_plle_tegra114(const char *name,
|
|||
struct tegra_clk_pll_params *pll_params,
|
||||
spinlock_t *lock);
|
||||
|
||||
struct clk *tegra_clk_register_plle_tegra210(const char *name,
|
||||
const char *parent_name,
|
||||
void __iomem *clk_base, unsigned long flags,
|
||||
struct tegra_clk_pll_params *pll_params,
|
||||
spinlock_t *lock);
|
||||
|
||||
struct clk *tegra_clk_register_pllc_tegra210(const char *name,
|
||||
const char *parent_name, void __iomem *clk_base,
|
||||
void __iomem *pmc, unsigned long flags,
|
||||
struct tegra_clk_pll_params *pll_params,
|
||||
spinlock_t *lock);
|
||||
|
||||
struct clk *tegra_clk_register_pllss_tegra210(const char *name,
|
||||
const char *parent_name, void __iomem *clk_base,
|
||||
unsigned long flags,
|
||||
struct tegra_clk_pll_params *pll_params,
|
||||
spinlock_t *lock);
|
||||
|
||||
struct clk *tegra_clk_register_pllss(const char *name, const char *parent_name,
|
||||
void __iomem *clk_base, unsigned long flags,
|
||||
struct tegra_clk_pll_params *pll_params,
|
||||
spinlock_t *lock);
|
||||
|
||||
struct clk *tegra_clk_register_pllmb(const char *name, const char *parent_name,
|
||||
void __iomem *clk_base, void __iomem *pmc,
|
||||
unsigned long flags,
|
||||
struct tegra_clk_pll_params *pll_params,
|
||||
spinlock_t *lock);
|
||||
|
||||
/**
|
||||
* struct tegra_clk_pll_out - PLL divider down clock
|
||||
*
|
||||
|
|
@ -653,6 +742,9 @@ int tegra_osc_clk_init(void __iomem *clk_base, struct tegra_clk *clks,
|
|||
void tegra_super_clk_gen4_init(void __iomem *clk_base,
|
||||
void __iomem *pmc_base, struct tegra_clk *tegra_clks,
|
||||
struct tegra_clk_pll_params *pll_params);
|
||||
void tegra_super_clk_gen5_init(void __iomem *clk_base,
|
||||
void __iomem *pmc_base, struct tegra_clk *tegra_clks,
|
||||
struct tegra_clk_pll_params *pll_params);
|
||||
|
||||
#ifdef CONFIG_TEGRA_CLK_EMC
|
||||
struct clk *tegra_clk_register_emc(void __iomem *base, struct device_node *np,
|
||||
|
|
@ -674,5 +766,8 @@ void tegra114_clock_deassert_dfll_dvco_reset(void);
|
|||
|
||||
typedef void (*tegra_clk_apply_init_table_func)(void);
|
||||
extern tegra_clk_apply_init_table_func tegra_clk_apply_init_table;
|
||||
int tegra_pll_wait_for_lock(struct tegra_clk_pll *pll);
|
||||
u16 tegra_pll_get_fixed_mdiv(struct clk_hw *hw, unsigned long input_rate);
|
||||
int tegra_pll_p_div_to_hw(struct tegra_clk_pll *pll, u8 p_div);
|
||||
|
||||
#endif /* TEGRA_CLK_H */
|
||||
|
|
|
|||
401
include/dt-bindings/clock/tegra210-car.h
Normal file
401
include/dt-bindings/clock/tegra210-car.h
Normal file
|
|
@ -0,0 +1,401 @@
|
|||
/*
|
||||
* This header provides constants for binding nvidia,tegra210-car.
|
||||
*
|
||||
* The first 224 clocks are numbered to match the bits in the CAR's CLK_OUT_ENB
|
||||
* registers. These IDs often match those in the CAR's RST_DEVICES registers,
|
||||
* but not in all cases. Some bits in CLK_OUT_ENB affect multiple clocks. In
|
||||
* this case, those clocks are assigned IDs above 224 in order to highlight
|
||||
* this issue. Implementations that interpret these clock IDs as bit values
|
||||
* within the CLK_OUT_ENB or RST_DEVICES registers should be careful to
|
||||
* explicitly handle these special cases.
|
||||
*
|
||||
* The balance of the clocks controlled by the CAR are assigned IDs of 224 and
|
||||
* above.
|
||||
*/
|
||||
|
||||
#ifndef _DT_BINDINGS_CLOCK_TEGRA210_CAR_H
|
||||
#define _DT_BINDINGS_CLOCK_TEGRA210_CAR_H
|
||||
|
||||
/* 0 */
|
||||
/* 1 */
|
||||
/* 2 */
|
||||
#define TEGRA210_CLK_ISPB 3
|
||||
#define TEGRA210_CLK_RTC 4
|
||||
#define TEGRA210_CLK_TIMER 5
|
||||
#define TEGRA210_CLK_UARTA 6
|
||||
/* 7 (register bit affects uartb and vfir) */
|
||||
#define TEGRA210_CLK_GPIO 8
|
||||
#define TEGRA210_CLK_SDMMC2 9
|
||||
/* 10 (register bit affects spdif_in and spdif_out) */
|
||||
#define TEGRA210_CLK_I2S1 11
|
||||
#define TEGRA210_CLK_I2C1 12
|
||||
/* 13 */
|
||||
#define TEGRA210_CLK_SDMMC1 14
|
||||
#define TEGRA210_CLK_SDMMC4 15
|
||||
/* 16 */
|
||||
#define TEGRA210_CLK_PWM 17
|
||||
#define TEGRA210_CLK_I2S2 18
|
||||
/* 19 */
|
||||
/* 20 (register bit affects vi and vi_sensor) */
|
||||
/* 21 */
|
||||
#define TEGRA210_CLK_USBD 22
|
||||
#define TEGRA210_CLK_ISP 23
|
||||
/* 24 */
|
||||
/* 25 */
|
||||
#define TEGRA210_CLK_DISP2 26
|
||||
#define TEGRA210_CLK_DISP1 27
|
||||
#define TEGRA210_CLK_HOST1X 28
|
||||
/* 29 */
|
||||
#define TEGRA210_CLK_I2S0 30
|
||||
/* 31 */
|
||||
|
||||
#define TEGRA210_CLK_MC 32
|
||||
#define TEGRA210_CLK_AHBDMA 33
|
||||
#define TEGRA210_CLK_APBDMA 34
|
||||
/* 35 */
|
||||
/* 36 */
|
||||
/* 37 */
|
||||
#define TEGRA210_CLK_PMC 38
|
||||
/* 39 (register bit affects fuse and fuse_burn) */
|
||||
#define TEGRA210_CLK_KFUSE 40
|
||||
#define TEGRA210_CLK_SBC1 41
|
||||
/* 42 */
|
||||
/* 43 */
|
||||
#define TEGRA210_CLK_SBC2 44
|
||||
/* 45 */
|
||||
#define TEGRA210_CLK_SBC3 46
|
||||
#define TEGRA210_CLK_I2C5 47
|
||||
#define TEGRA210_CLK_DSIA 48
|
||||
/* 49 */
|
||||
/* 50 */
|
||||
/* 51 */
|
||||
#define TEGRA210_CLK_CSI 52
|
||||
/* 53 */
|
||||
#define TEGRA210_CLK_I2C2 54
|
||||
#define TEGRA210_CLK_UARTC 55
|
||||
#define TEGRA210_CLK_MIPI_CAL 56
|
||||
#define TEGRA210_CLK_EMC 57
|
||||
#define TEGRA210_CLK_USB2 58
|
||||
/* 59 */
|
||||
/* 60 */
|
||||
/* 61 */
|
||||
/* 62 */
|
||||
#define TEGRA210_CLK_BSEV 63
|
||||
|
||||
/* 64 */
|
||||
#define TEGRA210_CLK_UARTD 65
|
||||
/* 66 */
|
||||
#define TEGRA210_CLK_I2C3 67
|
||||
#define TEGRA210_CLK_SBC4 68
|
||||
#define TEGRA210_CLK_SDMMC3 69
|
||||
#define TEGRA210_CLK_PCIE 70
|
||||
#define TEGRA210_CLK_OWR 71
|
||||
#define TEGRA210_CLK_AFI 72
|
||||
#define TEGRA210_CLK_CSITE 73
|
||||
/* 74 */
|
||||
/* 75 */
|
||||
/* 76 */
|
||||
/* 77 */
|
||||
#define TEGRA210_CLK_SOC_THERM 78
|
||||
#define TEGRA210_CLK_DTV 79
|
||||
/* 80 */
|
||||
#define TEGRA210_CLK_I2CSLOW 81
|
||||
#define TEGRA210_CLK_DSIB 82
|
||||
#define TEGRA210_CLK_TSEC 83
|
||||
/* 84 */
|
||||
/* 85 */
|
||||
/* 86 */
|
||||
/* 87 */
|
||||
/* 88 */
|
||||
#define TEGRA210_CLK_XUSB_HOST 89
|
||||
/* 90 */
|
||||
/* 91 */
|
||||
#define TEGRA210_CLK_CSUS 92
|
||||
/* 93 */
|
||||
/* 94 */
|
||||
/* 95 (bit affects xusb_dev and xusb_dev_src) */
|
||||
|
||||
/* 96 */
|
||||
/* 97 */
|
||||
/* 98 */
|
||||
#define TEGRA210_CLK_MSELECT 99
|
||||
#define TEGRA210_CLK_TSENSOR 100
|
||||
#define TEGRA210_CLK_I2S3 101
|
||||
#define TEGRA210_CLK_I2S4 102
|
||||
#define TEGRA210_CLK_I2C4 103
|
||||
/* 104 */
|
||||
/* 105 */
|
||||
#define TEGRA210_CLK_D_AUDIO 106
|
||||
/* 107 ( affects abp -> ape) */
|
||||
/* 108 */
|
||||
/* 109 */
|
||||
/* 110 */
|
||||
#define TEGRA210_CLK_HDA2CODEC_2X 111
|
||||
/* 112 */
|
||||
/* 113 */
|
||||
/* 114 */
|
||||
/* 115 */
|
||||
/* 116 */
|
||||
/* 117 */
|
||||
#define TEGRA210_CLK_SPDIF_2X 118
|
||||
#define TEGRA210_CLK_ACTMON 119
|
||||
#define TEGRA210_CLK_EXTERN1 120
|
||||
#define TEGRA210_CLK_EXTERN2 121
|
||||
#define TEGRA210_CLK_EXTERN3 122
|
||||
#define TEGRA210_CLK_SATA_OOB 123
|
||||
#define TEGRA210_CLK_SATA 124
|
||||
#define TEGRA210_CLK_HDA 125
|
||||
/* 126 */
|
||||
/* 127 */
|
||||
|
||||
#define TEGRA210_CLK_HDA2HDMI 128
|
||||
/* 129 */
|
||||
/* 130 */
|
||||
/* 131 */
|
||||
/* 132 */
|
||||
/* 133 */
|
||||
/* 134 */
|
||||
/* 135 */
|
||||
/* 136 */
|
||||
/* 137 */
|
||||
/* 138 */
|
||||
/* 139 */
|
||||
/* 140 */
|
||||
/* 141 */
|
||||
/* 142 */
|
||||
/* (bit affects xusb_falcon_src, xusb_fs_src, xusb_host_src and xusb_ss_src) */
|
||||
#define TEGRA210_CLK_XUSB_GATE 143
|
||||
#define TEGRA210_CLK_CILAB 144
|
||||
#define TEGRA210_CLK_CILCD 145
|
||||
#define TEGRA210_CLK_CILE 146
|
||||
#define TEGRA210_CLK_DSIALP 147
|
||||
#define TEGRA210_CLK_DSIBLP 148
|
||||
#define TEGRA210_CLK_ENTROPY 149
|
||||
/* 150 */
|
||||
/* 151 */
|
||||
/* 152 */
|
||||
/* 153 */
|
||||
/* 154 */
|
||||
/* 155 (bit affects dfll_ref and dfll_soc) */
|
||||
#define TEGRA210_CLK_XUSB_SS 156
|
||||
/* 157 */
|
||||
/* 158 */
|
||||
/* 159 */
|
||||
|
||||
/* 160 */
|
||||
#define TEGRA210_CLK_DMIC1 161
|
||||
#define TEGRA210_CLK_DMIC2 162
|
||||
/* 163 */
|
||||
/* 164 */
|
||||
/* 165 */
|
||||
#define TEGRA210_CLK_I2C6 166
|
||||
/* 167 */
|
||||
/* 168 */
|
||||
/* 169 */
|
||||
/* 170 */
|
||||
#define TEGRA210_CLK_VIM2_CLK 171
|
||||
/* 172 */
|
||||
#define TEGRA210_CLK_MIPIBIF 173
|
||||
/* 174 */
|
||||
/* 175 */
|
||||
/* 176 */
|
||||
#define TEGRA210_CLK_CLK72MHZ 177
|
||||
#define TEGRA210_CLK_VIC03 178
|
||||
/* 179 */
|
||||
/* 180 */
|
||||
#define TEGRA210_CLK_DPAUX 181
|
||||
#define TEGRA210_CLK_SOR0 182
|
||||
#define TEGRA210_CLK_SOR1 183
|
||||
#define TEGRA210_CLK_GPU 184
|
||||
#define TEGRA210_CLK_DBGAPB 185
|
||||
/* 186 */
|
||||
#define TEGRA210_CLK_PLL_P_OUT_ADSP 187
|
||||
/* 188 */
|
||||
#define TEGRA210_CLK_PLL_G_REF 189
|
||||
/* 190 */
|
||||
/* 191 */
|
||||
|
||||
/* 192 */
|
||||
#define TEGRA210_CLK_SDMMC_LEGACY 193
|
||||
#define TEGRA210_CLK_NVDEC 194
|
||||
#define TEGRA210_CLK_NVJPG 195
|
||||
/* 196 */
|
||||
#define TEGRA210_CLK_DMIC3 197
|
||||
#define TEGRA210_CLK_APE 198
|
||||
/* 199 */
|
||||
/* 200 */
|
||||
/* 201 */
|
||||
#define TEGRA210_CLK_MAUD 202
|
||||
/* 203 */
|
||||
/* 204 */
|
||||
/* 205 */
|
||||
#define TEGRA210_CLK_TSECB 206
|
||||
#define TEGRA210_CLK_DPAUX1 207
|
||||
#define TEGRA210_CLK_VI_I2C 208
|
||||
#define TEGRA210_CLK_HSIC_TRK 209
|
||||
#define TEGRA210_CLK_USB2_TRK 210
|
||||
#define TEGRA210_CLK_QSPI 211
|
||||
#define TEGRA210_CLK_UARTAPE 212
|
||||
/* 213 */
|
||||
/* 214 */
|
||||
/* 215 */
|
||||
/* 216 */
|
||||
/* 217 */
|
||||
/* 218 */
|
||||
#define TEGRA210_CLK_NVENC 219
|
||||
/* 220 */
|
||||
/* 221 */
|
||||
#define TEGRA210_CLK_SOR_SAFE 222
|
||||
#define TEGRA210_CLK_PLL_P_OUT_CPU 223
|
||||
|
||||
|
||||
#define TEGRA210_CLK_UARTB 224
|
||||
#define TEGRA210_CLK_VFIR 225
|
||||
#define TEGRA210_CLK_SPDIF_IN 226
|
||||
#define TEGRA210_CLK_SPDIF_OUT 227
|
||||
#define TEGRA210_CLK_VI 228
|
||||
#define TEGRA210_CLK_VI_SENSOR 229
|
||||
#define TEGRA210_CLK_FUSE 230
|
||||
#define TEGRA210_CLK_FUSE_BURN 231
|
||||
#define TEGRA210_CLK_CLK_32K 232
|
||||
#define TEGRA210_CLK_CLK_M 233
|
||||
#define TEGRA210_CLK_CLK_M_DIV2 234
|
||||
#define TEGRA210_CLK_CLK_M_DIV4 235
|
||||
#define TEGRA210_CLK_PLL_REF 236
|
||||
#define TEGRA210_CLK_PLL_C 237
|
||||
#define TEGRA210_CLK_PLL_C_OUT1 238
|
||||
#define TEGRA210_CLK_PLL_C2 239
|
||||
#define TEGRA210_CLK_PLL_C3 240
|
||||
#define TEGRA210_CLK_PLL_M 241
|
||||
#define TEGRA210_CLK_PLL_M_OUT1 242
|
||||
#define TEGRA210_CLK_PLL_P 243
|
||||
#define TEGRA210_CLK_PLL_P_OUT1 244
|
||||
#define TEGRA210_CLK_PLL_P_OUT2 245
|
||||
#define TEGRA210_CLK_PLL_P_OUT3 246
|
||||
#define TEGRA210_CLK_PLL_P_OUT4 247
|
||||
#define TEGRA210_CLK_PLL_A 248
|
||||
#define TEGRA210_CLK_PLL_A_OUT0 249
|
||||
#define TEGRA210_CLK_PLL_D 250
|
||||
#define TEGRA210_CLK_PLL_D_OUT0 251
|
||||
#define TEGRA210_CLK_PLL_D2 252
|
||||
#define TEGRA210_CLK_PLL_D2_OUT0 253
|
||||
#define TEGRA210_CLK_PLL_U 254
|
||||
#define TEGRA210_CLK_PLL_U_480M 255
|
||||
|
||||
#define TEGRA210_CLK_PLL_U_60M 256
|
||||
#define TEGRA210_CLK_PLL_U_48M 257
|
||||
/* 258 */
|
||||
#define TEGRA210_CLK_PLL_X 259
|
||||
#define TEGRA210_CLK_PLL_X_OUT0 260
|
||||
#define TEGRA210_CLK_PLL_RE_VCO 261
|
||||
#define TEGRA210_CLK_PLL_RE_OUT 262
|
||||
#define TEGRA210_CLK_PLL_E 263
|
||||
#define TEGRA210_CLK_SPDIF_IN_SYNC 264
|
||||
#define TEGRA210_CLK_I2S0_SYNC 265
|
||||
#define TEGRA210_CLK_I2S1_SYNC 266
|
||||
#define TEGRA210_CLK_I2S2_SYNC 267
|
||||
#define TEGRA210_CLK_I2S3_SYNC 268
|
||||
#define TEGRA210_CLK_I2S4_SYNC 269
|
||||
#define TEGRA210_CLK_VIMCLK_SYNC 270
|
||||
#define TEGRA210_CLK_AUDIO0 271
|
||||
#define TEGRA210_CLK_AUDIO1 272
|
||||
#define TEGRA210_CLK_AUDIO2 273
|
||||
#define TEGRA210_CLK_AUDIO3 274
|
||||
#define TEGRA210_CLK_AUDIO4 275
|
||||
#define TEGRA210_CLK_SPDIF 276
|
||||
#define TEGRA210_CLK_CLK_OUT_1 277
|
||||
#define TEGRA210_CLK_CLK_OUT_2 278
|
||||
#define TEGRA210_CLK_CLK_OUT_3 279
|
||||
#define TEGRA210_CLK_BLINK 280
|
||||
/* 281 */
|
||||
/* 282 */
|
||||
/* 283 */
|
||||
#define TEGRA210_CLK_XUSB_HOST_SRC 284
|
||||
#define TEGRA210_CLK_XUSB_FALCON_SRC 285
|
||||
#define TEGRA210_CLK_XUSB_FS_SRC 286
|
||||
#define TEGRA210_CLK_XUSB_SS_SRC 287
|
||||
|
||||
#define TEGRA210_CLK_XUSB_DEV_SRC 288
|
||||
#define TEGRA210_CLK_XUSB_DEV 289
|
||||
#define TEGRA210_CLK_XUSB_HS_SRC 290
|
||||
#define TEGRA210_CLK_SCLK 291
|
||||
#define TEGRA210_CLK_HCLK 292
|
||||
#define TEGRA210_CLK_PCLK 293
|
||||
#define TEGRA210_CLK_CCLK_G 294
|
||||
#define TEGRA210_CLK_CCLK_LP 295
|
||||
#define TEGRA210_CLK_DFLL_REF 296
|
||||
#define TEGRA210_CLK_DFLL_SOC 297
|
||||
#define TEGRA210_CLK_VI_SENSOR2 298
|
||||
#define TEGRA210_CLK_PLL_P_OUT5 299
|
||||
#define TEGRA210_CLK_CML0 300
|
||||
#define TEGRA210_CLK_CML1 301
|
||||
#define TEGRA210_CLK_PLL_C4 302
|
||||
#define TEGRA210_CLK_PLL_DP 303
|
||||
#define TEGRA210_CLK_PLL_E_MUX 304
|
||||
#define TEGRA210_CLK_PLL_MB 305
|
||||
#define TEGRA210_CLK_PLL_A1 306
|
||||
#define TEGRA210_CLK_PLL_D_DSI_OUT 307
|
||||
#define TEGRA210_CLK_PLL_C4_OUT0 308
|
||||
#define TEGRA210_CLK_PLL_C4_OUT1 309
|
||||
#define TEGRA210_CLK_PLL_C4_OUT2 310
|
||||
#define TEGRA210_CLK_PLL_C4_OUT3 311
|
||||
#define TEGRA210_CLK_PLL_U_OUT 312
|
||||
#define TEGRA210_CLK_PLL_U_OUT1 313
|
||||
#define TEGRA210_CLK_PLL_U_OUT2 314
|
||||
#define TEGRA210_CLK_USB2_HSIC_TRK 315
|
||||
#define TEGRA210_CLK_PLL_P_OUT_HSIO 316
|
||||
#define TEGRA210_CLK_PLL_P_OUT_XUSB 317
|
||||
#define TEGRA210_CLK_XUSB_SSP_SRC 318
|
||||
/* 319 */
|
||||
/* 320 */
|
||||
/* 321 */
|
||||
/* 322 */
|
||||
/* 323 */
|
||||
/* 324 */
|
||||
/* 325 */
|
||||
/* 326 */
|
||||
/* 327 */
|
||||
/* 328 */
|
||||
/* 329 */
|
||||
/* 330 */
|
||||
/* 331 */
|
||||
/* 332 */
|
||||
/* 333 */
|
||||
/* 334 */
|
||||
/* 335 */
|
||||
/* 336 */
|
||||
/* 337 */
|
||||
/* 338 */
|
||||
/* 339 */
|
||||
/* 340 */
|
||||
/* 341 */
|
||||
/* 342 */
|
||||
/* 343 */
|
||||
/* 344 */
|
||||
/* 345 */
|
||||
/* 346 */
|
||||
/* 347 */
|
||||
/* 348 */
|
||||
/* 349 */
|
||||
|
||||
#define TEGRA210_CLK_AUDIO0_MUX 350
|
||||
#define TEGRA210_CLK_AUDIO1_MUX 351
|
||||
#define TEGRA210_CLK_AUDIO2_MUX 352
|
||||
#define TEGRA210_CLK_AUDIO3_MUX 353
|
||||
#define TEGRA210_CLK_AUDIO4_MUX 354
|
||||
#define TEGRA210_CLK_SPDIF_MUX 355
|
||||
#define TEGRA210_CLK_CLK_OUT_1_MUX 356
|
||||
#define TEGRA210_CLK_CLK_OUT_2_MUX 357
|
||||
#define TEGRA210_CLK_CLK_OUT_3_MUX 358
|
||||
#define TEGRA210_CLK_DSIA_MUX 359
|
||||
#define TEGRA210_CLK_DSIB_MUX 360
|
||||
#define TEGRA210_CLK_SOR0_LVDS 361
|
||||
#define TEGRA210_CLK_XUSB_SS_DIV2 362
|
||||
|
||||
#define TEGRA210_CLK_PLL_M_UD 363
|
||||
#define TEGRA210_CLK_PLL_C_UD 364
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#define TEGRA210_CLK_SCLK_MUX 365
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#define TEGRA210_CLK_CLK_MAX 366
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#endif /* _DT_BINDINGS_CLOCK_TEGRA210_CAR_H */
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Reference in a new issue