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IB/mlx5: Add hca_core_clock_offset to udata in init_ucontext
Pass hca_core_clock_offset to user-space is mandatory in order to let the user-space read the free-running clock register from the right offset in the memory mapped page. Passing this value is done by changing the vendor's command and response of init_ucontext to be in extensible form. Signed-off-by: Matan Barak <matanb@mellanox.com> Reviewed-by: Moshe Lazer <moshel@mellanox.com> Signed-off-by: Doug Ledford <dledford@redhat.com>
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7c60bcbb68
commit
b368d7cb8c
4 changed files with 47 additions and 12 deletions
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@ -795,8 +795,8 @@ static struct ib_ucontext *mlx5_ib_alloc_ucontext(struct ib_device *ibdev,
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struct ib_udata *udata)
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{
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struct mlx5_ib_dev *dev = to_mdev(ibdev);
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struct mlx5_ib_alloc_ucontext_req_v2 req;
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struct mlx5_ib_alloc_ucontext_resp resp;
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struct mlx5_ib_alloc_ucontext_req_v2 req = {};
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struct mlx5_ib_alloc_ucontext_resp resp = {};
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struct mlx5_ib_ucontext *context;
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struct mlx5_uuar_info *uuari;
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struct mlx5_uar *uars;
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@ -811,20 +811,19 @@ static struct ib_ucontext *mlx5_ib_alloc_ucontext(struct ib_device *ibdev,
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if (!dev->ib_active)
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return ERR_PTR(-EAGAIN);
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memset(&req, 0, sizeof(req));
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reqlen = udata->inlen - sizeof(struct ib_uverbs_cmd_hdr);
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if (reqlen == sizeof(struct mlx5_ib_alloc_ucontext_req))
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ver = 0;
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else if (reqlen == sizeof(struct mlx5_ib_alloc_ucontext_req_v2))
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else if (reqlen >= sizeof(struct mlx5_ib_alloc_ucontext_req_v2))
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ver = 2;
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else
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return ERR_PTR(-EINVAL);
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err = ib_copy_from_udata(&req, udata, reqlen);
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err = ib_copy_from_udata(&req, udata, min(reqlen, sizeof(req)));
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if (err)
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return ERR_PTR(err);
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if (req.flags || req.reserved)
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if (req.flags)
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return ERR_PTR(-EINVAL);
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if (req.total_num_uuars > MLX5_MAX_UUARS)
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@ -833,6 +832,14 @@ static struct ib_ucontext *mlx5_ib_alloc_ucontext(struct ib_device *ibdev,
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if (req.total_num_uuars == 0)
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return ERR_PTR(-EINVAL);
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if (req.comp_mask)
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return ERR_PTR(-EOPNOTSUPP);
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if (reqlen > sizeof(req) &&
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!ib_is_udata_cleared(udata, sizeof(req),
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udata->inlen - sizeof(req)))
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return ERR_PTR(-EOPNOTSUPP);
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req.total_num_uuars = ALIGN(req.total_num_uuars,
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MLX5_NON_FP_BF_REGS_PER_PAGE);
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if (req.num_low_latency_uuars > req.total_num_uuars - 1)
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@ -848,6 +855,8 @@ static struct ib_ucontext *mlx5_ib_alloc_ucontext(struct ib_device *ibdev,
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resp.max_send_wqebb = 1 << MLX5_CAP_GEN(dev->mdev, log_max_qp_sz);
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resp.max_recv_wr = 1 << MLX5_CAP_GEN(dev->mdev, log_max_qp_sz);
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resp.max_srq_recv_wr = 1 << MLX5_CAP_GEN(dev->mdev, log_max_srq_sz);
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resp.response_length = min(offsetof(typeof(resp), response_length) +
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sizeof(resp.response_length), udata->outlen);
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context = kzalloc(sizeof(*context), GFP_KERNEL);
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if (!context)
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@ -898,8 +907,20 @@ static struct ib_ucontext *mlx5_ib_alloc_ucontext(struct ib_device *ibdev,
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resp.tot_uuars = req.total_num_uuars;
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resp.num_ports = MLX5_CAP_GEN(dev->mdev, num_ports);
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err = ib_copy_to_udata(udata, &resp,
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sizeof(resp) - sizeof(resp.reserved));
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if (field_avail(typeof(resp), reserved2, udata->outlen))
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resp.response_length += sizeof(resp.reserved2);
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if (field_avail(typeof(resp), hca_core_clock_offset, udata->outlen)) {
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resp.comp_mask |=
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MLX5_IB_ALLOC_UCONTEXT_RESP_MASK_CORE_CLOCK_OFFSET;
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resp.hca_core_clock_offset =
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offsetof(struct mlx5_init_seg, internal_timer_h) %
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PAGE_SIZE;
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resp.response_length += sizeof(resp.hca_core_clock_offset);
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}
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err = ib_copy_to_udata(udata, &resp, resp.response_length);
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if (err)
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goto out_uars;
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@ -55,6 +55,9 @@ pr_err("%s:%s:%d:(pid %d): " format, (dev)->ib_dev.name, __func__, \
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pr_warn("%s:%s:%d:(pid %d): " format, (dev)->ib_dev.name, __func__, \
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__LINE__, current->pid, ##arg)
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#define field_avail(type, fld, sz) (offsetof(type, fld) + \
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sizeof(((type *)0)->fld) <= (sz))
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enum {
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MLX5_IB_MMAP_CMD_SHIFT = 8,
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MLX5_IB_MMAP_CMD_MASK = 0xff,
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@ -66,7 +66,11 @@ struct mlx5_ib_alloc_ucontext_req_v2 {
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__u32 total_num_uuars;
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__u32 num_low_latency_uuars;
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__u32 flags;
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__u32 reserved;
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__u32 comp_mask;
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};
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enum mlx5_ib_alloc_ucontext_resp_mask {
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MLX5_IB_ALLOC_UCONTEXT_RESP_MASK_CORE_CLOCK_OFFSET = 1UL << 0,
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};
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struct mlx5_ib_alloc_ucontext_resp {
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@ -80,7 +84,11 @@ struct mlx5_ib_alloc_ucontext_resp {
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__u32 max_recv_wr;
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__u32 max_srq_recv_wr;
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__u16 num_ports;
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__u16 reserved;
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__u16 reserved1;
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__u32 comp_mask;
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__u32 response_length;
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__u32 reserved2;
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__u64 hca_core_clock_offset;
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};
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struct mlx5_ib_alloc_pd_resp {
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@ -462,9 +462,12 @@ struct mlx5_init_seg {
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__be32 rsvd1[120];
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__be32 initializing;
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struct health_buffer health;
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__be32 rsvd2[884];
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__be32 rsvd2[880];
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__be32 internal_timer_h;
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__be32 internal_timer_l;
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__be32 rsvd3[2];
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__be32 health_counter;
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__be32 rsvd3[1019];
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__be32 rsvd4[1019];
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__be64 ieee1588_clk;
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__be32 ieee1588_clk_type;
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__be32 clr_intx;
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