mirror of
https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git
synced 2024-08-26 02:39:48 +00:00
Merge branch 'for-2.6.25' of master.kernel.org:/pub/scm/linux/kernel/git/galak/powerpc into for-2.6.25
This commit is contained in:
commit
b370b08274
31 changed files with 190 additions and 174 deletions
|
@ -151,6 +151,7 @@ brg@9f0 {
|
|||
compatible = "fsl,mpc875-brg",
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||||
"fsl,cpm1-brg",
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||||
"fsl,cpm-brg";
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||||
clock-frequency = <50000000>;
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||||
reg = <0x9f0 0x10>;
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||||
};
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||||
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||||
|
|
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@ -150,6 +150,7 @@ brg@9f0 {
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|||
compatible = "fsl,mpc875-brg",
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"fsl,cpm1-brg",
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"fsl,cpm-brg";
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clock-frequency = <50000000>;
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reg = <0x9f0 0x10>;
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};
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||||
|
|
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@ -118,6 +118,10 @@ i2c@3000 {
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interrupts = <14 0x8>;
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interrupt-parent = <&ipic>;
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dfsrr;
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rtc@68 {
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compatible = "dallas,ds1339";
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reg = <0x68>;
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};
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};
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i2c@3100 {
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|
|
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@ -96,7 +96,7 @@ immr@e0000000 {
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#address-cells = <1>;
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#size-cells = <1>;
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device_type = "soc";
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compatible = "simple-bus";
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compatible = "fsl,mpc8315-immr", "simple-bus";
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ranges = <0 0xe0000000 0x00100000>;
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reg = <0xe0000000 0x00000200>;
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bus-frequency = <0>;
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@ -332,7 +332,7 @@ pci1: pci@e0008600 {
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0xc000 0x0 0x0 0x3 &ipic 23 0x8
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0xc000 0x0 0x0 0x4 &ipic 20 0x8>;
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interrupt-parent = <&ipic>;
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interrupts = <66 0x8>;
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interrupts = <67 0x8>;
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bus-range = <0 0>;
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ranges = <0x02000000 0x0 0xb0000000 0xb0000000 0x0 0x10000000
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0x42000000 0x0 0xa0000000 0xa0000000 0x0 0x10000000
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|
|
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@ -42,6 +42,18 @@ PowerPC,8572@0 {
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bus-frequency = <0>;
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clock-frequency = <0>;
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};
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PowerPC,8572@1 {
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device_type = "cpu";
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reg = <1>;
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d-cache-line-size = <20>; // 32 bytes
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i-cache-line-size = <20>; // 32 bytes
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d-cache-size = <8000>; // L1, 32K
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i-cache-size = <8000>; // L1, 32K
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timebase-frequency = <0>;
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bus-frequency = <0>;
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clock-frequency = <0>;
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};
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};
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memory {
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|
|
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@ -166,6 +166,7 @@ brg@9f0 {
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compatible = "fsl,mpc885-brg",
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"fsl,cpm1-brg",
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"fsl,cpm-brg";
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clock-frequency = <0>;
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reg = <9f0 10>;
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};
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|
|
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@ -15,7 +15,7 @@
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/ {
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model = "StorCenter";
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compatible = "storcenter";
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compatible = "iomega,storcenter";
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#address-cells = <1>;
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#size-cells = <1>;
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@ -62,12 +62,12 @@ i2c@3000 {
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#size-cells = <0>;
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compatible = "fsl-i2c";
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reg = <0x3000 0x100>;
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interrupts = <5 2>;
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interrupts = <17 2>;
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interrupt-parent = <&mpic>;
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rtc@68 {
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compatible = "dallas,ds1337";
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reg = <68>;
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reg = <0x68>;
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};
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};
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@ -78,7 +78,7 @@ serial0: serial@4500 {
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reg = <0x4500 0x20>;
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clock-frequency = <97553800>; /* Hz */
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current-speed = <115200>;
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interrupts = <9 2>;
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interrupts = <25 2>;
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interrupt-parent = <&mpic>;
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};
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@ -89,7 +89,7 @@ serial1: serial@4600 {
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reg = <0x4600 0x20>;
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clock-frequency = <97553800>; /* Hz */
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current-speed = <9600>;
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interrupts = <10 2>;
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interrupts = <26 2>;
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interrupt-parent = <&mpic>;
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};
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@ -136,6 +136,6 @@ pci0: pci@fe800000 {
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};
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chosen {
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linux,stdout-path = "/soc/serial@4500";
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linux,stdout-path = &serial0;
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};
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};
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|
|
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@ -186,7 +186,7 @@ CONFIG_PREEMPT_NONE=y
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# CONFIG_PREEMPT is not set
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CONFIG_BINFMT_ELF=y
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# CONFIG_BINFMT_MISC is not set
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# CONFIG_MATH_EMULATION is not set
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CONFIG_MATH_EMULATION=y
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CONFIG_ARCH_ENABLE_MEMORY_HOTPLUG=y
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CONFIG_ARCH_FLATMEM_ENABLE=y
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CONFIG_ARCH_POPULATES_NODE_MAP=y
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@ -416,14 +416,14 @@ CONFIG_PHYLIB=y
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# MII PHY device drivers
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#
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CONFIG_MARVELL_PHY=y
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# CONFIG_DAVICOM_PHY is not set
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CONFIG_DAVICOM_PHY=y
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# CONFIG_QSEMI_PHY is not set
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# CONFIG_LXT_PHY is not set
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# CONFIG_CICADA_PHY is not set
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# CONFIG_VITESSE_PHY is not set
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CONFIG_VITESSE_PHY=y
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# CONFIG_SMSC_PHY is not set
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# CONFIG_BROADCOM_PHY is not set
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# CONFIG_ICPLUS_PHY is not set
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CONFIG_ICPLUS_PHY=y
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# CONFIG_FIXED_PHY is not set
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# CONFIG_MDIO_BITBANG is not set
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CONFIG_NET_ETHERNET=y
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@ -436,7 +436,7 @@ CONFIG_MII=y
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CONFIG_NETDEV_1000=y
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CONFIG_GIANFAR=y
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# CONFIG_GFAR_NAPI is not set
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# CONFIG_UCC_GETH is not set
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CONFIG_UCC_GETH=y
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CONFIG_NETDEV_10000=y
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#
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|
|
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@ -959,6 +959,9 @@ static struct cpu_spec __initdata cpu_specs[] = {
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.icache_bsize = 32,
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.dcache_bsize = 32,
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.cpu_setup = __setup_cpu_603,
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.num_pmcs = 4,
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.oprofile_cpu_type = "ppc/e300",
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.oprofile_type = PPC_OPROFILE_FSL_EMB,
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.platform = "ppc603",
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},
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{ /* e300c4 (e300c1, plus one IU) */
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@ -971,6 +974,9 @@ static struct cpu_spec __initdata cpu_specs[] = {
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.dcache_bsize = 32,
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.cpu_setup = __setup_cpu_603,
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.machine_check = machine_check_generic,
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.num_pmcs = 4,
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.oprofile_cpu_type = "ppc/e300",
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.oprofile_type = PPC_OPROFILE_FSL_EMB,
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.platform = "ppc603",
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},
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{ /* default match, we assume split I/D cache & TB (non-601)... */
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@ -1435,7 +1441,7 @@ static struct cpu_spec __initdata cpu_specs[] = {
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.dcache_bsize = 32,
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.num_pmcs = 4,
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.oprofile_cpu_type = "ppc/e500",
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.oprofile_type = PPC_OPROFILE_BOOKE,
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.oprofile_type = PPC_OPROFILE_FSL_EMB,
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.machine_check = machine_check_e500,
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.platform = "ppc8540",
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},
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@ -1453,7 +1459,7 @@ static struct cpu_spec __initdata cpu_specs[] = {
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.dcache_bsize = 32,
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.num_pmcs = 4,
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.oprofile_cpu_type = "ppc/e500",
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.oprofile_type = PPC_OPROFILE_BOOKE,
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.oprofile_type = PPC_OPROFILE_FSL_EMB,
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.machine_check = machine_check_e500,
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.platform = "ppc8548",
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},
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|
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@ -26,7 +26,7 @@
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static void dummy_perf(struct pt_regs *regs)
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{
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#if defined(CONFIG_FSL_BOOKE) && !defined(CONFIG_E200)
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#if defined(CONFIG_FSL_EMB_PERFMON)
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mtpmr(PMRN_PMGC0, mfpmr(PMRN_PMGC0) & ~PMGC0_PMIE);
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#elif defined(CONFIG_PPC64) || defined(CONFIG_6xx)
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if (cur_cpu_spec->pmc_type == PPC_PMC_IBM)
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|
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@ -15,5 +15,5 @@ oprofile-$(CONFIG_OPROFILE_CELL) += op_model_cell.o \
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cell/spu_profiler.o cell/vma_map.o \
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cell/spu_task_sync.o
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oprofile-$(CONFIG_PPC64) += op_model_rs64.o op_model_power4.o op_model_pa6t.o
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oprofile-$(CONFIG_FSL_BOOKE) += op_model_fsl_booke.o
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oprofile-$(CONFIG_FSL_EMB_PERFMON) += op_model_fsl_emb.o
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oprofile-$(CONFIG_6xx) += op_model_7450.o
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@ -202,9 +202,9 @@ int __init oprofile_arch_init(struct oprofile_operations *ops)
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model = &op_model_7450;
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break;
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#endif
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#ifdef CONFIG_FSL_BOOKE
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case PPC_OPROFILE_BOOKE:
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model = &op_model_fsl_booke;
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#if defined(CONFIG_FSL_EMB_PERFMON)
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case PPC_OPROFILE_FSL_EMB:
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model = &op_model_fsl_emb;
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break;
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#endif
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default:
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|
|
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@ -1,7 +1,5 @@
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/*
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* arch/powerpc/oprofile/op_model_fsl_booke.c
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*
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* Freescale Book-E oprofile support, based on ppc64 oprofile support
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* Freescale Embedded oprofile support, based on ppc64 oprofile support
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* Copyright (C) 2004 Anton Blanchard <anton@au.ibm.com>, IBM
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*
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* Copyright (c) 2004 Freescale Semiconductor, Inc
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@ -22,7 +20,7 @@
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#include <asm/system.h>
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#include <asm/processor.h>
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#include <asm/cputable.h>
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#include <asm/reg_booke.h>
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#include <asm/reg_fsl_emb.h>
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#include <asm/page.h>
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#include <asm/pmc.h>
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#include <asm/oprofile_impl.h>
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|
@ -244,7 +242,7 @@ static void dump_pmcs(void)
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mfpmr(PMRN_PMLCA3), mfpmr(PMRN_PMLCB3));
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}
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static int fsl_booke_cpu_setup(struct op_counter_config *ctr)
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static int fsl_emb_cpu_setup(struct op_counter_config *ctr)
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{
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int i;
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|
@ -262,7 +260,7 @@ static int fsl_booke_cpu_setup(struct op_counter_config *ctr)
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return 0;
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}
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|
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static int fsl_booke_reg_setup(struct op_counter_config *ctr,
|
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static int fsl_emb_reg_setup(struct op_counter_config *ctr,
|
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struct op_system_config *sys,
|
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int num_ctrs)
|
||||
{
|
||||
|
@ -281,7 +279,7 @@ static int fsl_booke_reg_setup(struct op_counter_config *ctr,
|
|||
return 0;
|
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}
|
||||
|
||||
static int fsl_booke_start(struct op_counter_config *ctr)
|
||||
static int fsl_emb_start(struct op_counter_config *ctr)
|
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{
|
||||
int i;
|
||||
|
||||
|
@ -315,7 +313,7 @@ static int fsl_booke_start(struct op_counter_config *ctr)
|
|||
return 0;
|
||||
}
|
||||
|
||||
static void fsl_booke_stop(void)
|
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static void fsl_emb_stop(void)
|
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{
|
||||
/* freeze counters */
|
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pmc_stop_ctrs();
|
||||
|
@ -329,7 +327,7 @@ static void fsl_booke_stop(void)
|
|||
}
|
||||
|
||||
|
||||
static void fsl_booke_handle_interrupt(struct pt_regs *regs,
|
||||
static void fsl_emb_handle_interrupt(struct pt_regs *regs,
|
||||
struct op_counter_config *ctr)
|
||||
{
|
||||
unsigned long pc;
|
||||
|
@ -362,10 +360,10 @@ static void fsl_booke_handle_interrupt(struct pt_regs *regs,
|
|||
pmc_start_ctrs(1);
|
||||
}
|
||||
|
||||
struct op_powerpc_model op_model_fsl_booke = {
|
||||
.reg_setup = fsl_booke_reg_setup,
|
||||
.cpu_setup = fsl_booke_cpu_setup,
|
||||
.start = fsl_booke_start,
|
||||
.stop = fsl_booke_stop,
|
||||
.handle_interrupt = fsl_booke_handle_interrupt,
|
||||
struct op_powerpc_model op_model_fsl_emb = {
|
||||
.reg_setup = fsl_emb_reg_setup,
|
||||
.cpu_setup = fsl_emb_cpu_setup,
|
||||
.start = fsl_emb_start,
|
||||
.stop = fsl_emb_stop,
|
||||
.handle_interrupt = fsl_emb_handle_interrupt,
|
||||
};
|
|
@ -101,7 +101,7 @@ static void __init mpc832x_rdb_setup_arch(void)
|
|||
#ifdef CONFIG_QUICC_ENGINE
|
||||
qe_reset();
|
||||
|
||||
if ((np = of_find_node_by_name(np, "par_io")) != NULL) {
|
||||
if ((np = of_find_node_by_name(NULL, "par_io")) != NULL) {
|
||||
par_io_init(np);
|
||||
of_node_put(np);
|
||||
|
||||
|
|
|
@ -14,6 +14,8 @@
|
|||
#define MPC83XX_SCCR_USB_DRCM_11 0x00300000
|
||||
#define MPC83XX_SCCR_USB_DRCM_01 0x00100000
|
||||
#define MPC83XX_SCCR_USB_DRCM_10 0x00200000
|
||||
#define MPC8315_SCCR_USB_MASK 0x00c00000
|
||||
#define MPC8315_SCCR_USB_DRCM_11 0x00c00000
|
||||
#define MPC837X_SCCR_USB_DRCM_11 0x00c00000
|
||||
|
||||
/* system i/o configuration register low */
|
||||
|
|
|
@ -104,6 +104,7 @@ int mpc831x_usb_cfg(void)
|
|||
u32 temp;
|
||||
void __iomem *immap, *usb_regs;
|
||||
struct device_node *np = NULL;
|
||||
struct device_node *immr_node = NULL;
|
||||
const void *prop;
|
||||
struct resource res;
|
||||
int ret = 0;
|
||||
|
@ -124,10 +125,15 @@ int mpc831x_usb_cfg(void)
|
|||
}
|
||||
|
||||
/* Configure clock */
|
||||
temp = in_be32(immap + MPC83XX_SCCR_OFFS);
|
||||
temp &= ~MPC83XX_SCCR_USB_MASK;
|
||||
temp |= MPC83XX_SCCR_USB_DRCM_11; /* 1:3 */
|
||||
out_be32(immap + MPC83XX_SCCR_OFFS, temp);
|
||||
immr_node = of_get_parent(np);
|
||||
if (immr_node && of_device_is_compatible(immr_node, "fsl,mpc8315-immr"))
|
||||
clrsetbits_be32(immap + MPC83XX_SCCR_OFFS,
|
||||
MPC8315_SCCR_USB_MASK,
|
||||
MPC8315_SCCR_USB_DRCM_11);
|
||||
else
|
||||
clrsetbits_be32(immap + MPC83XX_SCCR_OFFS,
|
||||
MPC83XX_SCCR_USB_MASK,
|
||||
MPC83XX_SCCR_USB_DRCM_11);
|
||||
|
||||
/* Configure pin mux for ULPI. There is no pin mux for UTMI */
|
||||
if (prop && !strcmp(prop, "ulpi")) {
|
||||
|
@ -144,6 +150,9 @@ int mpc831x_usb_cfg(void)
|
|||
|
||||
iounmap(immap);
|
||||
|
||||
if (immr_node)
|
||||
of_node_put(immr_node);
|
||||
|
||||
/* Map USB SOC space */
|
||||
ret = of_address_to_resource(np, 0, &res);
|
||||
if (ret) {
|
||||
|
|
|
@ -15,12 +15,12 @@
|
|||
|
||||
#include <asm/time.h>
|
||||
#include <asm/machdep.h>
|
||||
#include <asm/commproc.h>
|
||||
#include <asm/cpm1.h>
|
||||
#include <asm/fs_pd.h>
|
||||
#include <asm/udbg.h>
|
||||
#include <asm/prom.h>
|
||||
|
||||
#include <sysdev/commproc.h>
|
||||
#include "mpc8xx.h"
|
||||
|
||||
struct cpm_pin {
|
||||
int port, pin, flags;
|
||||
|
@ -108,7 +108,7 @@ define_machine(adder875) {
|
|||
.name = "Adder MPC875",
|
||||
.probe = adder875_probe,
|
||||
.setup_arch = adder875_setup,
|
||||
.init_IRQ = m8xx_pic_init,
|
||||
.init_IRQ = mpc8xx_pics_init,
|
||||
.get_irq = mpc8xx_get_irq,
|
||||
.restart = mpc8xx_restart,
|
||||
.calibrate_decr = generic_calibrate_decr,
|
||||
|
|
|
@ -15,7 +15,6 @@
|
|||
#include <asm/machdep.h>
|
||||
#include <asm/io.h>
|
||||
#include <asm/udbg.h>
|
||||
#include <asm/commproc.h>
|
||||
#include <asm/cpm1.h>
|
||||
|
||||
#include "mpc8xx.h"
|
||||
|
|
|
@ -24,6 +24,7 @@ config PPC_83xx
|
|||
select MPC83xx
|
||||
select IPIC
|
||||
select WANT_DEVICE_TREE
|
||||
select FSL_EMB_PERFMON
|
||||
|
||||
config PPC_86xx
|
||||
bool "Freescale 86xx"
|
||||
|
|
|
@ -94,6 +94,7 @@ config 8xx
|
|||
bool
|
||||
|
||||
config E500
|
||||
select FSL_EMB_PERFMON
|
||||
bool
|
||||
|
||||
config PPC_FPU
|
||||
|
@ -115,6 +116,9 @@ config FSL_BOOKE
|
|||
depends on E200 || E500
|
||||
default y
|
||||
|
||||
config FSL_EMB_PERFMON
|
||||
bool
|
||||
|
||||
config PTE_64BIT
|
||||
bool
|
||||
depends on 44x || E500
|
||||
|
|
|
@ -132,33 +132,18 @@ static void __init storcenter_init_IRQ(void)
|
|||
|
||||
paddr = (phys_addr_t)of_translate_address(dnp, prop);
|
||||
mpic = mpic_alloc(dnp, paddr, MPIC_PRIMARY | MPIC_WANTS_RESET,
|
||||
4, 32, " EPIC ");
|
||||
16, 32, " OpenPIC ");
|
||||
|
||||
of_node_put(dnp);
|
||||
|
||||
BUG_ON(mpic == NULL);
|
||||
|
||||
/* PCI IRQs */
|
||||
/*
|
||||
* 2.6.12 patch:
|
||||
* openpic_set_sources(0, 5, OpenPIC_Addr + 0x10200);
|
||||
* openpic_set_sources(5, 2, OpenPIC_Addr + 0x11120);
|
||||
* first_irq, num_irqs, __iomem first_ISR
|
||||
* o_ss: i, src: 0, fdf50200
|
||||
* o_ss: i, src: 1, fdf50220
|
||||
* o_ss: i, src: 2, fdf50240
|
||||
* o_ss: i, src: 3, fdf50260
|
||||
* o_ss: i, src: 4, fdf50280
|
||||
* o_ss: i, src: 5, fdf51120
|
||||
* o_ss: i, src: 6, fdf51140
|
||||
* 16 Serial Interrupts followed by 16 Internal Interrupts.
|
||||
* I2C is the second internal, so it is at 17, 0x11020.
|
||||
*/
|
||||
mpic_assign_isu(mpic, 0, paddr + 0x10200);
|
||||
mpic_assign_isu(mpic, 1, paddr + 0x10220);
|
||||
mpic_assign_isu(mpic, 2, paddr + 0x10240);
|
||||
mpic_assign_isu(mpic, 3, paddr + 0x10260);
|
||||
mpic_assign_isu(mpic, 4, paddr + 0x10280);
|
||||
mpic_assign_isu(mpic, 5, paddr + 0x11120);
|
||||
mpic_assign_isu(mpic, 6, paddr + 0x11140);
|
||||
mpic_assign_isu(mpic, 1, paddr + 0x11000);
|
||||
|
||||
mpic_init(mpic);
|
||||
}
|
||||
|
@ -178,7 +163,7 @@ static int __init storcenter_probe(void)
|
|||
{
|
||||
unsigned long root = of_get_flat_dt_root();
|
||||
|
||||
return of_flat_dt_is_compatible(root, "storcenter");
|
||||
return of_flat_dt_is_compatible(root, "iomega,storcenter");
|
||||
}
|
||||
|
||||
define_machine(storcenter){
|
||||
|
|
|
@ -1342,7 +1342,7 @@ static int __init of_fsl_spi_probe(char *type, char *compatible, u32 sysclk,
|
|||
if (ret)
|
||||
goto unreg;
|
||||
|
||||
ret = platform_device_register(pdev);
|
||||
ret = platform_device_add(pdev);
|
||||
if (ret)
|
||||
goto unreg;
|
||||
|
||||
|
|
|
@ -66,7 +66,7 @@ phys_addr_t get_qe_base(void)
|
|||
{
|
||||
struct device_node *qe;
|
||||
unsigned int size;
|
||||
const void *prop;
|
||||
const u32 *prop;
|
||||
|
||||
if (qebase != -1)
|
||||
return qebase;
|
||||
|
@ -79,7 +79,8 @@ phys_addr_t get_qe_base(void)
|
|||
}
|
||||
|
||||
prop = of_get_property(qe, "reg", &size);
|
||||
qebase = of_translate_address(qe, prop);
|
||||
if (prop && size >= sizeof(*prop))
|
||||
qebase = of_translate_address(qe, prop);
|
||||
of_node_put(qe);
|
||||
|
||||
return qebase;
|
||||
|
@ -172,10 +173,9 @@ unsigned int get_brg_clk(void)
|
|||
}
|
||||
|
||||
prop = of_get_property(qe, "brg-frequency", &size);
|
||||
if (!prop || size != sizeof(*prop))
|
||||
return brg_clk;
|
||||
if (prop && size == sizeof(*prop))
|
||||
brg_clk = *prop;
|
||||
|
||||
brg_clk = *prop;
|
||||
of_node_put(qe);
|
||||
|
||||
return brg_clk;
|
||||
|
|
|
@ -1737,10 +1737,8 @@ config SC92031
|
|||
|
||||
config CPMAC
|
||||
tristate "TI AR7 CPMAC Ethernet support (EXPERIMENTAL)"
|
||||
depends on NET_ETHERNET && EXPERIMENTAL && AR7
|
||||
depends on NET_ETHERNET && EXPERIMENTAL && AR7 && BROKEN
|
||||
select PHYLIB
|
||||
select FIXED_PHY
|
||||
select FIXED_MII_100_FDX
|
||||
help
|
||||
TI AR7 CPMAC Ethernet support
|
||||
|
||||
|
|
|
@ -845,15 +845,6 @@ static void cpmac_adjust_link(struct net_device *dev)
|
|||
spin_unlock(&priv->lock);
|
||||
}
|
||||
|
||||
static int cpmac_link_update(struct net_device *dev,
|
||||
struct fixed_phy_status *status)
|
||||
{
|
||||
status->link = 1;
|
||||
status->speed = 100;
|
||||
status->duplex = 1;
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int cpmac_open(struct net_device *dev)
|
||||
{
|
||||
int i, size, res;
|
||||
|
@ -996,11 +987,11 @@ static int external_switch;
|
|||
static int __devinit cpmac_probe(struct platform_device *pdev)
|
||||
{
|
||||
int rc, phy_id, i;
|
||||
int mdio_bus_id = cpmac_mii.id;
|
||||
struct resource *mem;
|
||||
struct cpmac_priv *priv;
|
||||
struct net_device *dev;
|
||||
struct plat_cpmac_data *pdata;
|
||||
struct fixed_info *fixed_phy;
|
||||
DECLARE_MAC_BUF(mac);
|
||||
|
||||
pdata = pdev->dev.platform_data;
|
||||
|
@ -1014,9 +1005,23 @@ static int __devinit cpmac_probe(struct platform_device *pdev)
|
|||
}
|
||||
|
||||
if (phy_id == PHY_MAX_ADDR) {
|
||||
if (external_switch || dumb_switch)
|
||||
if (external_switch || dumb_switch) {
|
||||
struct fixed_phy_status status = {};
|
||||
|
||||
mdio_bus_id = 0;
|
||||
|
||||
/*
|
||||
* FIXME: this should be in the platform code!
|
||||
* Since there is not platform code at all (that is,
|
||||
* no mainline users of that driver), place it here
|
||||
* for now.
|
||||
*/
|
||||
phy_id = 0;
|
||||
else {
|
||||
status.link = 1;
|
||||
status.duplex = 1;
|
||||
status.speed = 100;
|
||||
fixed_phy_add(PHY_POLL, phy_id, &status);
|
||||
} else {
|
||||
printk(KERN_ERR "cpmac: no PHY present\n");
|
||||
return -ENODEV;
|
||||
}
|
||||
|
@ -1060,32 +1065,8 @@ static int __devinit cpmac_probe(struct platform_device *pdev)
|
|||
priv->msg_enable = netif_msg_init(debug_level, 0xff);
|
||||
memcpy(dev->dev_addr, pdata->dev_addr, sizeof(dev->dev_addr));
|
||||
|
||||
if (phy_id == 31) {
|
||||
snprintf(priv->phy_name, BUS_ID_SIZE, PHY_ID_FMT, cpmac_mii.id,
|
||||
phy_id);
|
||||
} else {
|
||||
/* Let's try to get a free fixed phy... */
|
||||
for (i = 0; i < MAX_PHY_AMNT; i++) {
|
||||
fixed_phy = fixed_mdio_get_phydev(i);
|
||||
if (!fixed_phy)
|
||||
continue;
|
||||
if (!fixed_phy->phydev->attached_dev) {
|
||||
strncpy(priv->phy_name,
|
||||
fixed_phy->phydev->dev.bus_id,
|
||||
BUS_ID_SIZE);
|
||||
fixed_mdio_set_link_update(fixed_phy->phydev,
|
||||
&cpmac_link_update);
|
||||
goto phy_found;
|
||||
}
|
||||
}
|
||||
if (netif_msg_drv(priv))
|
||||
printk(KERN_ERR "%s: Could not find fixed PHY\n",
|
||||
dev->name);
|
||||
rc = -ENODEV;
|
||||
goto fail;
|
||||
}
|
||||
snprintf(priv->phy_name, BUS_ID_SIZE, PHY_ID_FMT, mdio_bus_id, phy_id);
|
||||
|
||||
phy_found:
|
||||
priv->phy = phy_connect(dev, priv->phy_name, &cpmac_adjust_link, 0,
|
||||
PHY_INTERFACE_MODE_MII);
|
||||
if (IS_ERR(priv->phy)) {
|
||||
|
|
|
@ -46,7 +46,7 @@ enum powerpc_oprofile_type {
|
|||
PPC_OPROFILE_RS64 = 1,
|
||||
PPC_OPROFILE_POWER4 = 2,
|
||||
PPC_OPROFILE_G4 = 3,
|
||||
PPC_OPROFILE_BOOKE = 4,
|
||||
PPC_OPROFILE_FSL_EMB = 4,
|
||||
PPC_OPROFILE_CELL = 5,
|
||||
PPC_OPROFILE_PA6T = 6,
|
||||
};
|
||||
|
|
|
@ -54,7 +54,7 @@ struct op_powerpc_model {
|
|||
int num_counters;
|
||||
};
|
||||
|
||||
extern struct op_powerpc_model op_model_fsl_booke;
|
||||
extern struct op_powerpc_model op_model_fsl_emb;
|
||||
extern struct op_powerpc_model op_model_rs64;
|
||||
extern struct op_powerpc_model op_model_power4;
|
||||
extern struct op_powerpc_model op_model_7450;
|
||||
|
|
|
@ -18,6 +18,10 @@
|
|||
#include <asm/reg_booke.h>
|
||||
#endif /* CONFIG_BOOKE || CONFIG_40x */
|
||||
|
||||
#ifdef CONFIG_FSL_EMB_PERFMON
|
||||
#include <asm/reg_fsl_emb.h>
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_8xx
|
||||
#include <asm/reg_8xx.h>
|
||||
#endif /* CONFIG_8xx */
|
||||
|
|
|
@ -9,68 +9,6 @@
|
|||
#ifndef __ASM_POWERPC_REG_BOOKE_H__
|
||||
#define __ASM_POWERPC_REG_BOOKE_H__
|
||||
|
||||
#ifndef __ASSEMBLY__
|
||||
/* Performance Monitor Registers */
|
||||
#define mfpmr(rn) ({unsigned int rval; \
|
||||
asm volatile("mfpmr %0," __stringify(rn) \
|
||||
: "=r" (rval)); rval;})
|
||||
#define mtpmr(rn, v) asm volatile("mtpmr " __stringify(rn) ",%0" : : "r" (v))
|
||||
#endif /* __ASSEMBLY__ */
|
||||
|
||||
/* Freescale Book E Performance Monitor APU Registers */
|
||||
#define PMRN_PMC0 0x010 /* Performance Monitor Counter 0 */
|
||||
#define PMRN_PMC1 0x011 /* Performance Monitor Counter 1 */
|
||||
#define PMRN_PMC2 0x012 /* Performance Monitor Counter 1 */
|
||||
#define PMRN_PMC3 0x013 /* Performance Monitor Counter 1 */
|
||||
#define PMRN_PMLCA0 0x090 /* PM Local Control A0 */
|
||||
#define PMRN_PMLCA1 0x091 /* PM Local Control A1 */
|
||||
#define PMRN_PMLCA2 0x092 /* PM Local Control A2 */
|
||||
#define PMRN_PMLCA3 0x093 /* PM Local Control A3 */
|
||||
|
||||
#define PMLCA_FC 0x80000000 /* Freeze Counter */
|
||||
#define PMLCA_FCS 0x40000000 /* Freeze in Supervisor */
|
||||
#define PMLCA_FCU 0x20000000 /* Freeze in User */
|
||||
#define PMLCA_FCM1 0x10000000 /* Freeze when PMM==1 */
|
||||
#define PMLCA_FCM0 0x08000000 /* Freeze when PMM==0 */
|
||||
#define PMLCA_CE 0x04000000 /* Condition Enable */
|
||||
|
||||
#define PMLCA_EVENT_MASK 0x007f0000 /* Event field */
|
||||
#define PMLCA_EVENT_SHIFT 16
|
||||
|
||||
#define PMRN_PMLCB0 0x110 /* PM Local Control B0 */
|
||||
#define PMRN_PMLCB1 0x111 /* PM Local Control B1 */
|
||||
#define PMRN_PMLCB2 0x112 /* PM Local Control B2 */
|
||||
#define PMRN_PMLCB3 0x113 /* PM Local Control B3 */
|
||||
|
||||
#define PMLCB_THRESHMUL_MASK 0x0700 /* Threshhold Multiple Field */
|
||||
#define PMLCB_THRESHMUL_SHIFT 8
|
||||
|
||||
#define PMLCB_THRESHOLD_MASK 0x003f /* Threshold Field */
|
||||
#define PMLCB_THRESHOLD_SHIFT 0
|
||||
|
||||
#define PMRN_PMGC0 0x190 /* PM Global Control 0 */
|
||||
|
||||
#define PMGC0_FAC 0x80000000 /* Freeze all Counters */
|
||||
#define PMGC0_PMIE 0x40000000 /* Interrupt Enable */
|
||||
#define PMGC0_FCECE 0x20000000 /* Freeze countes on
|
||||
Enabled Condition or
|
||||
Event */
|
||||
|
||||
#define PMRN_UPMC0 0x000 /* User Performance Monitor Counter 0 */
|
||||
#define PMRN_UPMC1 0x001 /* User Performance Monitor Counter 1 */
|
||||
#define PMRN_UPMC2 0x002 /* User Performance Monitor Counter 1 */
|
||||
#define PMRN_UPMC3 0x003 /* User Performance Monitor Counter 1 */
|
||||
#define PMRN_UPMLCA0 0x080 /* User PM Local Control A0 */
|
||||
#define PMRN_UPMLCA1 0x081 /* User PM Local Control A1 */
|
||||
#define PMRN_UPMLCA2 0x082 /* User PM Local Control A2 */
|
||||
#define PMRN_UPMLCA3 0x083 /* User PM Local Control A3 */
|
||||
#define PMRN_UPMLCB0 0x100 /* User PM Local Control B0 */
|
||||
#define PMRN_UPMLCB1 0x101 /* User PM Local Control B1 */
|
||||
#define PMRN_UPMLCB2 0x102 /* User PM Local Control B2 */
|
||||
#define PMRN_UPMLCB3 0x103 /* User PM Local Control B3 */
|
||||
#define PMRN_UPMGC0 0x180 /* User PM Global Control 0 */
|
||||
|
||||
|
||||
/* Machine State Register (MSR) Fields */
|
||||
#define MSR_UCLE (1<<26) /* User-mode cache lock enable */
|
||||
#define MSR_SPE (1<<25) /* Enable SPE */
|
||||
|
|
72
include/asm-powerpc/reg_fsl_emb.h
Normal file
72
include/asm-powerpc/reg_fsl_emb.h
Normal file
|
@ -0,0 +1,72 @@
|
|||
/*
|
||||
* Contains register definitions for the Freescale Embedded Performance
|
||||
* Monitor.
|
||||
*/
|
||||
#ifdef __KERNEL__
|
||||
#ifndef __ASM_POWERPC_REG_FSL_EMB_H__
|
||||
#define __ASM_POWERPC_REG_FSL_EMB_H__
|
||||
|
||||
#ifndef __ASSEMBLY__
|
||||
/* Performance Monitor Registers */
|
||||
#define mfpmr(rn) ({unsigned int rval; \
|
||||
asm volatile("mfpmr %0," __stringify(rn) \
|
||||
: "=r" (rval)); rval;})
|
||||
#define mtpmr(rn, v) asm volatile("mtpmr " __stringify(rn) ",%0" : : "r" (v))
|
||||
#endif /* __ASSEMBLY__ */
|
||||
|
||||
/* Freescale Book E Performance Monitor APU Registers */
|
||||
#define PMRN_PMC0 0x010 /* Performance Monitor Counter 0 */
|
||||
#define PMRN_PMC1 0x011 /* Performance Monitor Counter 1 */
|
||||
#define PMRN_PMC2 0x012 /* Performance Monitor Counter 1 */
|
||||
#define PMRN_PMC3 0x013 /* Performance Monitor Counter 1 */
|
||||
#define PMRN_PMLCA0 0x090 /* PM Local Control A0 */
|
||||
#define PMRN_PMLCA1 0x091 /* PM Local Control A1 */
|
||||
#define PMRN_PMLCA2 0x092 /* PM Local Control A2 */
|
||||
#define PMRN_PMLCA3 0x093 /* PM Local Control A3 */
|
||||
|
||||
#define PMLCA_FC 0x80000000 /* Freeze Counter */
|
||||
#define PMLCA_FCS 0x40000000 /* Freeze in Supervisor */
|
||||
#define PMLCA_FCU 0x20000000 /* Freeze in User */
|
||||
#define PMLCA_FCM1 0x10000000 /* Freeze when PMM==1 */
|
||||
#define PMLCA_FCM0 0x08000000 /* Freeze when PMM==0 */
|
||||
#define PMLCA_CE 0x04000000 /* Condition Enable */
|
||||
|
||||
#define PMLCA_EVENT_MASK 0x007f0000 /* Event field */
|
||||
#define PMLCA_EVENT_SHIFT 16
|
||||
|
||||
#define PMRN_PMLCB0 0x110 /* PM Local Control B0 */
|
||||
#define PMRN_PMLCB1 0x111 /* PM Local Control B1 */
|
||||
#define PMRN_PMLCB2 0x112 /* PM Local Control B2 */
|
||||
#define PMRN_PMLCB3 0x113 /* PM Local Control B3 */
|
||||
|
||||
#define PMLCB_THRESHMUL_MASK 0x0700 /* Threshhold Multiple Field */
|
||||
#define PMLCB_THRESHMUL_SHIFT 8
|
||||
|
||||
#define PMLCB_THRESHOLD_MASK 0x003f /* Threshold Field */
|
||||
#define PMLCB_THRESHOLD_SHIFT 0
|
||||
|
||||
#define PMRN_PMGC0 0x190 /* PM Global Control 0 */
|
||||
|
||||
#define PMGC0_FAC 0x80000000 /* Freeze all Counters */
|
||||
#define PMGC0_PMIE 0x40000000 /* Interrupt Enable */
|
||||
#define PMGC0_FCECE 0x20000000 /* Freeze countes on
|
||||
Enabled Condition or
|
||||
Event */
|
||||
|
||||
#define PMRN_UPMC0 0x000 /* User Performance Monitor Counter 0 */
|
||||
#define PMRN_UPMC1 0x001 /* User Performance Monitor Counter 1 */
|
||||
#define PMRN_UPMC2 0x002 /* User Performance Monitor Counter 1 */
|
||||
#define PMRN_UPMC3 0x003 /* User Performance Monitor Counter 1 */
|
||||
#define PMRN_UPMLCA0 0x080 /* User PM Local Control A0 */
|
||||
#define PMRN_UPMLCA1 0x081 /* User PM Local Control A1 */
|
||||
#define PMRN_UPMLCA2 0x082 /* User PM Local Control A2 */
|
||||
#define PMRN_UPMLCA3 0x083 /* User PM Local Control A3 */
|
||||
#define PMRN_UPMLCB0 0x100 /* User PM Local Control B0 */
|
||||
#define PMRN_UPMLCB1 0x101 /* User PM Local Control B1 */
|
||||
#define PMRN_UPMLCB2 0x102 /* User PM Local Control B2 */
|
||||
#define PMRN_UPMLCB3 0x103 /* User PM Local Control B3 */
|
||||
#define PMRN_UPMGC0 0x180 /* User PM Global Control 0 */
|
||||
|
||||
|
||||
#endif /* __ASM_POWERPC_REG_FSL_EMB_H__ */
|
||||
#endif /* __KERNEL__ */
|
Loading…
Reference in a new issue