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drm/amd/pp: Use atombios api directly in powerplay (v2)
In order to remove the cgs wrapper functions for atombios api. v2: squash in whitespace cleanup (Alex) Reviewed-by: Huang Rui <ray.huang@amd.com> Signed-off-by: Rex Zhu <Rex.Zhu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
This commit is contained in:
Rex Zhu
Alex Deucher
parent
e8ee21d2a4
commit
b3892e2bb5
12 changed files with 149 additions and 123 deletions
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@ -23,7 +23,7 @@
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#include "pp_debug.h"
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#include <linux/module.h>
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#include <linux/slab.h>
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#include "atom.h"
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#include "ppatomctrl.h"
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#include "atombios.h"
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#include "cgs_common.h"
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@ -128,7 +128,6 @@ static int atomctrl_set_mc_reg_address_table(
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return 0;
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}
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int atomctrl_initialize_mc_reg_table(
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struct pp_hwmgr *hwmgr,
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uint8_t module_index,
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@ -141,7 +140,7 @@ int atomctrl_initialize_mc_reg_table(
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u16 size;
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vram_info = (ATOM_VRAM_INFO_HEADER_V2_1 *)
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cgs_atom_get_data_table(hwmgr->device,
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smu_atom_get_data_table(hwmgr->adev,
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GetIndexIntoMasterTable(DATA, VRAM_Info), &size, &frev, &crev);
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if (module_index >= vram_info->ucNumOfVRAMModule) {
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@ -174,6 +173,8 @@ int atomctrl_set_engine_dram_timings_rv770(
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uint32_t engine_clock,
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uint32_t memory_clock)
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{
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struct amdgpu_device *adev = hwmgr->adev;
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SET_ENGINE_CLOCK_PS_ALLOCATION engine_clock_parameters;
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/* They are both in 10KHz Units. */
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@ -184,9 +185,10 @@ int atomctrl_set_engine_dram_timings_rv770(
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/* in 10 khz units.*/
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engine_clock_parameters.sReserved.ulClock =
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cpu_to_le32(memory_clock & SET_CLOCK_FREQ_MASK);
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return cgs_atom_exec_cmd_table(hwmgr->device,
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return amdgpu_atom_execute_table(adev->mode_info.atom_context,
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GetIndexIntoMasterTable(COMMAND, DynamicMemorySettings),
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&engine_clock_parameters);
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(uint32_t *)&engine_clock_parameters);
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}
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/**
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@ -203,7 +205,7 @@ static ATOM_VOLTAGE_OBJECT_INFO *get_voltage_info_table(void *device)
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union voltage_object_info *voltage_info;
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voltage_info = (union voltage_object_info *)
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cgs_atom_get_data_table(device, index,
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smu_atom_get_data_table(device, index,
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&size, &frev, &crev);
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if (voltage_info != NULL)
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@ -247,16 +249,16 @@ int atomctrl_get_memory_pll_dividers_si(
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pp_atomctrl_memory_clock_param *mpll_param,
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bool strobe_mode)
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{
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struct amdgpu_device *adev = hwmgr->adev;
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COMPUTE_MEMORY_CLOCK_PARAM_PARAMETERS_V2_1 mpll_parameters;
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int result;
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mpll_parameters.ulClock = cpu_to_le32(clock_value);
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mpll_parameters.ucInputFlag = (uint8_t)((strobe_mode) ? 1 : 0);
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result = cgs_atom_exec_cmd_table
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(hwmgr->device,
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result = amdgpu_atom_execute_table(adev->mode_info.atom_context,
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GetIndexIntoMasterTable(COMMAND, ComputeMemoryClockParam),
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&mpll_parameters);
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(uint32_t *)&mpll_parameters);
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if (0 == result) {
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mpll_param->mpll_fb_divider.clk_frac =
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@ -295,14 +297,15 @@ int atomctrl_get_memory_pll_dividers_si(
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int atomctrl_get_memory_pll_dividers_vi(struct pp_hwmgr *hwmgr,
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uint32_t clock_value, pp_atomctrl_memory_clock_param *mpll_param)
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{
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struct amdgpu_device *adev = hwmgr->adev;
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COMPUTE_MEMORY_CLOCK_PARAM_PARAMETERS_V2_2 mpll_parameters;
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int result;
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mpll_parameters.ulClock.ulClock = cpu_to_le32(clock_value);
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result = cgs_atom_exec_cmd_table(hwmgr->device,
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result = amdgpu_atom_execute_table(adev->mode_info.atom_context,
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GetIndexIntoMasterTable(COMMAND, ComputeMemoryClockParam),
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&mpll_parameters);
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(uint32_t *)&mpll_parameters);
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if (!result)
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mpll_param->mpll_post_divider =
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@ -315,15 +318,15 @@ int atomctrl_get_engine_pll_dividers_kong(struct pp_hwmgr *hwmgr,
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uint32_t clock_value,
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pp_atomctrl_clock_dividers_kong *dividers)
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{
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struct amdgpu_device *adev = hwmgr->adev;
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COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS_V4 pll_parameters;
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int result;
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pll_parameters.ulClock = cpu_to_le32(clock_value);
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result = cgs_atom_exec_cmd_table
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(hwmgr->device,
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result = amdgpu_atom_execute_table(adev->mode_info.atom_context,
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GetIndexIntoMasterTable(COMMAND, ComputeMemoryEnginePLL),
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&pll_parameters);
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(uint32_t *)&pll_parameters);
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if (0 == result) {
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dividers->pll_post_divider = pll_parameters.ucPostDiv;
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@ -338,16 +341,16 @@ int atomctrl_get_engine_pll_dividers_vi(
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uint32_t clock_value,
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pp_atomctrl_clock_dividers_vi *dividers)
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{
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struct amdgpu_device *adev = hwmgr->adev;
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COMPUTE_GPU_CLOCK_OUTPUT_PARAMETERS_V1_6 pll_patameters;
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int result;
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pll_patameters.ulClock.ulClock = cpu_to_le32(clock_value);
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pll_patameters.ulClock.ucPostDiv = COMPUTE_GPUCLK_INPUT_FLAG_SCLK;
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result = cgs_atom_exec_cmd_table
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(hwmgr->device,
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result = amdgpu_atom_execute_table(adev->mode_info.atom_context,
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GetIndexIntoMasterTable(COMMAND, ComputeMemoryEnginePLL),
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&pll_patameters);
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(uint32_t *)&pll_patameters);
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if (0 == result) {
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dividers->pll_post_divider =
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@ -375,16 +378,16 @@ int atomctrl_get_engine_pll_dividers_ai(struct pp_hwmgr *hwmgr,
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uint32_t clock_value,
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pp_atomctrl_clock_dividers_ai *dividers)
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{
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struct amdgpu_device *adev = hwmgr->adev;
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COMPUTE_GPU_CLOCK_OUTPUT_PARAMETERS_V1_7 pll_patameters;
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int result;
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pll_patameters.ulClock.ulClock = cpu_to_le32(clock_value);
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pll_patameters.ulClock.ucPostDiv = COMPUTE_GPUCLK_INPUT_FLAG_SCLK;
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result = cgs_atom_exec_cmd_table
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(hwmgr->device,
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result = amdgpu_atom_execute_table(adev->mode_info.atom_context,
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GetIndexIntoMasterTable(COMMAND, ComputeMemoryEnginePLL),
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&pll_patameters);
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(uint32_t *)&pll_patameters);
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if (0 == result) {
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dividers->usSclk_fcw_frac = le16_to_cpu(pll_patameters.usSclk_fcw_frac);
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@ -407,6 +410,7 @@ int atomctrl_get_dfs_pll_dividers_vi(
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uint32_t clock_value,
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pp_atomctrl_clock_dividers_vi *dividers)
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{
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struct amdgpu_device *adev = hwmgr->adev;
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COMPUTE_GPU_CLOCK_OUTPUT_PARAMETERS_V1_6 pll_patameters;
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int result;
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@ -414,10 +418,9 @@ int atomctrl_get_dfs_pll_dividers_vi(
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pll_patameters.ulClock.ucPostDiv =
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COMPUTE_GPUCLK_INPUT_FLAG_DEFAULT_GPUCLK;
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result = cgs_atom_exec_cmd_table
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(hwmgr->device,
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result = amdgpu_atom_execute_table(adev->mode_info.atom_context,
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GetIndexIntoMasterTable(COMMAND, ComputeMemoryEnginePLL),
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&pll_patameters);
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(uint32_t *)&pll_patameters);
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if (0 == result) {
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dividers->pll_post_divider =
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@ -452,7 +455,7 @@ uint32_t atomctrl_get_reference_clock(struct pp_hwmgr *hwmgr)
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uint32_t clock;
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fw_info = (ATOM_FIRMWARE_INFO *)
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cgs_atom_get_data_table(hwmgr->device,
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smu_atom_get_data_table(hwmgr->adev,
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GetIndexIntoMasterTable(DATA, FirmwareInfo),
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&size, &frev, &crev);
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@ -476,7 +479,7 @@ bool atomctrl_is_voltage_controlled_by_gpio_v3(
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uint8_t voltage_mode)
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{
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ATOM_VOLTAGE_OBJECT_INFO_V3_1 *voltage_info =
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(ATOM_VOLTAGE_OBJECT_INFO_V3_1 *)get_voltage_info_table(hwmgr->device);
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(ATOM_VOLTAGE_OBJECT_INFO_V3_1 *)get_voltage_info_table(hwmgr->adev);
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bool ret;
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PP_ASSERT_WITH_CODE((NULL != voltage_info),
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@ -495,7 +498,7 @@ int atomctrl_get_voltage_table_v3(
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pp_atomctrl_voltage_table *voltage_table)
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{
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ATOM_VOLTAGE_OBJECT_INFO_V3_1 *voltage_info =
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(ATOM_VOLTAGE_OBJECT_INFO_V3_1 *)get_voltage_info_table(hwmgr->device);
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(ATOM_VOLTAGE_OBJECT_INFO_V3_1 *)get_voltage_info_table(hwmgr->adev);
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const ATOM_VOLTAGE_OBJECT_V3 *voltage_object;
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unsigned int i;
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@ -572,7 +575,7 @@ static ATOM_GPIO_PIN_LUT *get_gpio_lookup_table(void *device)
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void *table_address;
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table_address = (ATOM_GPIO_PIN_LUT *)
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cgs_atom_get_data_table(device,
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smu_atom_get_data_table(device,
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GetIndexIntoMasterTable(DATA, GPIO_Pin_LUT),
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&size, &frev, &crev);
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@ -592,7 +595,7 @@ bool atomctrl_get_pp_assign_pin(
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{
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bool bRet = false;
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ATOM_GPIO_PIN_LUT *gpio_lookup_table =
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get_gpio_lookup_table(hwmgr->device);
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get_gpio_lookup_table(hwmgr->adev);
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PP_ASSERT_WITH_CODE((NULL != gpio_lookup_table),
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"Could not find GPIO lookup Table in BIOS.", return false);
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@ -613,7 +616,7 @@ int atomctrl_calculate_voltage_evv_on_sclk(
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bool debug)
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{
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ATOM_ASIC_PROFILING_INFO_V3_4 *getASICProfilingInfo;
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struct amdgpu_device *adev = hwmgr->adev;
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EFUSE_LINEAR_FUNC_PARAM sRO_fuse;
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EFUSE_LINEAR_FUNC_PARAM sCACm_fuse;
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EFUSE_LINEAR_FUNC_PARAM sCACb_fuse;
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@ -640,7 +643,7 @@ int atomctrl_calculate_voltage_evv_on_sclk(
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int result;
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getASICProfilingInfo = (ATOM_ASIC_PROFILING_INFO_V3_4 *)
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cgs_atom_get_data_table(hwmgr->device,
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smu_atom_get_data_table(hwmgr->adev,
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GetIndexIntoMasterTable(DATA, ASIC_ProfilingInfo),
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NULL, NULL, NULL);
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@ -706,9 +709,9 @@ int atomctrl_calculate_voltage_evv_on_sclk(
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sOutput_FuseValues.sEfuse = sInput_FuseValues;
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result = cgs_atom_exec_cmd_table(hwmgr->device,
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result = amdgpu_atom_execute_table(adev->mode_info.atom_context,
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GetIndexIntoMasterTable(COMMAND, ReadEfuseValue),
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&sOutput_FuseValues);
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(uint32_t *)&sOutput_FuseValues);
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if (result)
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return result;
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@ -727,9 +730,9 @@ int atomctrl_calculate_voltage_evv_on_sclk(
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sOutput_FuseValues.sEfuse = sInput_FuseValues;
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result = cgs_atom_exec_cmd_table(hwmgr->device,
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result = amdgpu_atom_execute_table(adev->mode_info.atom_context,
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GetIndexIntoMasterTable(COMMAND, ReadEfuseValue),
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&sOutput_FuseValues);
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(uint32_t *)&sOutput_FuseValues);
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if (result)
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return result;
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@ -747,9 +750,9 @@ int atomctrl_calculate_voltage_evv_on_sclk(
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sInput_FuseValues.ucBitLength = sCACb_fuse.ucEfuseLength;
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sOutput_FuseValues.sEfuse = sInput_FuseValues;
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result = cgs_atom_exec_cmd_table(hwmgr->device,
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result = amdgpu_atom_execute_table(adev->mode_info.atom_context,
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GetIndexIntoMasterTable(COMMAND, ReadEfuseValue),
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&sOutput_FuseValues);
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(uint32_t *)&sOutput_FuseValues);
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if (result)
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return result;
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@ -768,9 +771,9 @@ int atomctrl_calculate_voltage_evv_on_sclk(
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sOutput_FuseValues.sEfuse = sInput_FuseValues;
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result = cgs_atom_exec_cmd_table(hwmgr->device,
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result = amdgpu_atom_execute_table(adev->mode_info.atom_context,
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GetIndexIntoMasterTable(COMMAND, ReadEfuseValue),
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&sOutput_FuseValues);
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(uint32_t *)&sOutput_FuseValues);
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if (result)
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return result;
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@ -790,9 +793,9 @@ int atomctrl_calculate_voltage_evv_on_sclk(
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sOutput_FuseValues.sEfuse = sInput_FuseValues;
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result = cgs_atom_exec_cmd_table(hwmgr->device,
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result = amdgpu_atom_execute_table(adev->mode_info.atom_context,
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GetIndexIntoMasterTable(COMMAND, ReadEfuseValue),
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&sOutput_FuseValues);
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(uint32_t *)&sOutput_FuseValues);
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if (result)
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return result;
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@ -811,9 +814,9 @@ int atomctrl_calculate_voltage_evv_on_sclk(
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sInput_FuseValues.ucBitLength = sKv_b_fuse.ucEfuseLength;
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sOutput_FuseValues.sEfuse = sInput_FuseValues;
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result = cgs_atom_exec_cmd_table(hwmgr->device,
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result = amdgpu_atom_execute_table(adev->mode_info.atom_context,
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GetIndexIntoMasterTable(COMMAND, ReadEfuseValue),
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&sOutput_FuseValues);
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(uint32_t *)&sOutput_FuseValues);
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if (result)
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return result;
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@ -842,9 +845,9 @@ int atomctrl_calculate_voltage_evv_on_sclk(
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sOutput_FuseValues.sEfuse = sInput_FuseValues;
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result = cgs_atom_exec_cmd_table(hwmgr->device,
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result = amdgpu_atom_execute_table(adev->mode_info.atom_context,
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GetIndexIntoMasterTable(COMMAND, ReadEfuseValue),
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&sOutput_FuseValues);
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(uint32_t *)&sOutput_FuseValues);
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if (result)
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return result;
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@ -1053,8 +1056,9 @@ int atomctrl_get_voltage_evv_on_sclk(
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uint32_t sclk, uint16_t virtual_voltage_Id,
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uint16_t *voltage)
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{
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int result;
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struct amdgpu_device *adev = hwmgr->adev;
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GET_VOLTAGE_INFO_INPUT_PARAMETER_V1_2 get_voltage_info_param_space;
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int result;
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get_voltage_info_param_space.ucVoltageType =
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voltage_type;
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@ -1065,9 +1069,9 @@ int atomctrl_get_voltage_evv_on_sclk(
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get_voltage_info_param_space.ulSCLKFreq =
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cpu_to_le32(sclk);
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result = cgs_atom_exec_cmd_table(hwmgr->device,
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result = amdgpu_atom_execute_table(adev->mode_info.atom_context,
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GetIndexIntoMasterTable(COMMAND, GetVoltageInfo),
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&get_voltage_info_param_space);
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(uint32_t *)&get_voltage_info_param_space);
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if (0 != result)
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return result;
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@ -1088,9 +1092,10 @@ int atomctrl_get_voltage_evv(struct pp_hwmgr *hwmgr,
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uint16_t virtual_voltage_id,
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uint16_t *voltage)
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{
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struct amdgpu_device *adev = hwmgr->adev;
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GET_VOLTAGE_INFO_INPUT_PARAMETER_V1_2 get_voltage_info_param_space;
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int result;
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int entry_id;
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GET_VOLTAGE_INFO_INPUT_PARAMETER_V1_2 get_voltage_info_param_space;
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/* search for leakage voltage ID 0xff01 ~ 0xff08 and sckl */
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for (entry_id = 0; entry_id < hwmgr->dyn_state.vddc_dependency_on_sclk->count; entry_id++) {
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@ -1111,9 +1116,9 @@ int atomctrl_get_voltage_evv(struct pp_hwmgr *hwmgr,
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get_voltage_info_param_space.ulSCLKFreq =
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cpu_to_le32(hwmgr->dyn_state.vddc_dependency_on_sclk->entries[entry_id].clk);
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result = cgs_atom_exec_cmd_table(hwmgr->device,
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result = amdgpu_atom_execute_table(adev->mode_info.atom_context,
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GetIndexIntoMasterTable(COMMAND, GetVoltageInfo),
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&get_voltage_info_param_space);
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(uint32_t *)&get_voltage_info_param_space);
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if (0 != result)
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return result;
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@ -1135,7 +1140,7 @@ uint32_t atomctrl_get_mpll_reference_clock(struct pp_hwmgr *hwmgr)
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u16 size;
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fw_info = (ATOM_COMMON_TABLE_HEADER *)
|
||||
cgs_atom_get_data_table(hwmgr->device,
|
||||
smu_atom_get_data_table(hwmgr->adev,
|
||||
GetIndexIntoMasterTable(DATA, FirmwareInfo),
|
||||
&size, &frev, &crev);
|
||||
|
||||
|
|
@ -1167,7 +1172,7 @@ static ATOM_ASIC_INTERNAL_SS_INFO *asic_internal_ss_get_ss_table(void *device)
|
|||
u16 size;
|
||||
|
||||
table = (ATOM_ASIC_INTERNAL_SS_INFO *)
|
||||
cgs_atom_get_data_table(device,
|
||||
smu_atom_get_data_table(device,
|
||||
GetIndexIntoMasterTable(DATA, ASIC_InternalSS_Info),
|
||||
&size, &frev, &crev);
|
||||
|
||||
|
|
@ -1188,7 +1193,7 @@ static int asic_internal_ss_get_ss_asignment(struct pp_hwmgr *hwmgr,
|
|||
|
||||
memset(ssEntry, 0x00, sizeof(pp_atomctrl_internal_ss_info));
|
||||
|
||||
table = asic_internal_ss_get_ss_table(hwmgr->device);
|
||||
table = asic_internal_ss_get_ss_table(hwmgr->adev);
|
||||
|
||||
if (NULL == table)
|
||||
return -1;
|
||||
|
|
@ -1260,9 +1265,10 @@ int atomctrl_get_engine_clock_spread_spectrum(
|
|||
ASIC_INTERNAL_ENGINE_SS, engine_clock, ssInfo);
|
||||
}
|
||||
|
||||
int atomctrl_read_efuse(void *device, uint16_t start_index,
|
||||
int atomctrl_read_efuse(struct pp_hwmgr *hwmgr, uint16_t start_index,
|
||||
uint16_t end_index, uint32_t mask, uint32_t *efuse)
|
||||
{
|
||||
struct amdgpu_device *adev = hwmgr->adev;
|
||||
int result;
|
||||
READ_EFUSE_VALUE_PARAMETER efuse_param;
|
||||
|
||||
|
|
@ -1272,9 +1278,9 @@ int atomctrl_read_efuse(void *device, uint16_t start_index,
|
|||
efuse_param.sEfuse.ucBitLength = (uint8_t)
|
||||
((end_index - start_index) + 1);
|
||||
|
||||
result = cgs_atom_exec_cmd_table(device,
|
||||
result = amdgpu_atom_execute_table(adev->mode_info.atom_context,
|
||||
GetIndexIntoMasterTable(COMMAND, ReadEfuseValue),
|
||||
&efuse_param);
|
||||
(uint32_t *)&efuse_param);
|
||||
if (!result)
|
||||
*efuse = le32_to_cpu(efuse_param.ulEfuseValue) & mask;
|
||||
|
||||
|
|
@ -1284,6 +1290,7 @@ int atomctrl_read_efuse(void *device, uint16_t start_index,
|
|||
int atomctrl_set_ac_timing_ai(struct pp_hwmgr *hwmgr, uint32_t memory_clock,
|
||||
uint8_t level)
|
||||
{
|
||||
struct amdgpu_device *adev = hwmgr->adev;
|
||||
DYNAMICE_MEMORY_SETTINGS_PARAMETER_V2_1 memory_clock_parameters;
|
||||
int result;
|
||||
|
||||
|
|
@ -1293,10 +1300,9 @@ int atomctrl_set_ac_timing_ai(struct pp_hwmgr *hwmgr, uint32_t memory_clock,
|
|||
ADJUST_MC_SETTING_PARAM;
|
||||
memory_clock_parameters.asDPMMCReg.ucMclkDPMState = level;
|
||||
|
||||
result = cgs_atom_exec_cmd_table
|
||||
(hwmgr->device,
|
||||
result = amdgpu_atom_execute_table(adev->mode_info.atom_context,
|
||||
GetIndexIntoMasterTable(COMMAND, DynamicMemorySettings),
|
||||
&memory_clock_parameters);
|
||||
(uint32_t *)&memory_clock_parameters);
|
||||
|
||||
return result;
|
||||
}
|
||||
|
|
@ -1304,7 +1310,7 @@ int atomctrl_set_ac_timing_ai(struct pp_hwmgr *hwmgr, uint32_t memory_clock,
|
|||
int atomctrl_get_voltage_evv_on_sclk_ai(struct pp_hwmgr *hwmgr, uint8_t voltage_type,
|
||||
uint32_t sclk, uint16_t virtual_voltage_Id, uint32_t *voltage)
|
||||
{
|
||||
|
||||
struct amdgpu_device *adev = hwmgr->adev;
|
||||
int result;
|
||||
GET_VOLTAGE_INFO_INPUT_PARAMETER_V1_3 get_voltage_info_param_space;
|
||||
|
||||
|
|
@ -1313,9 +1319,9 @@ int atomctrl_get_voltage_evv_on_sclk_ai(struct pp_hwmgr *hwmgr, uint8_t voltage_
|
|||
get_voltage_info_param_space.usVoltageLevel = cpu_to_le16(virtual_voltage_Id);
|
||||
get_voltage_info_param_space.ulSCLKFreq = cpu_to_le32(sclk);
|
||||
|
||||
result = cgs_atom_exec_cmd_table(hwmgr->device,
|
||||
result = amdgpu_atom_execute_table(adev->mode_info.atom_context,
|
||||
GetIndexIntoMasterTable(COMMAND, GetVoltageInfo),
|
||||
&get_voltage_info_param_space);
|
||||
(uint32_t *)&get_voltage_info_param_space);
|
||||
|
||||
if (0 != result)
|
||||
return result;
|
||||
|
|
@ -1334,7 +1340,7 @@ int atomctrl_get_smc_sclk_range_table(struct pp_hwmgr *hwmgr, struct pp_atom_ctr
|
|||
u16 size;
|
||||
|
||||
ATOM_SMU_INFO_V2_1 *psmu_info =
|
||||
(ATOM_SMU_INFO_V2_1 *)cgs_atom_get_data_table(hwmgr->device,
|
||||
(ATOM_SMU_INFO_V2_1 *)smu_atom_get_data_table(hwmgr->adev,
|
||||
GetIndexIntoMasterTable(DATA, SMU_Info),
|
||||
&size, &frev, &crev);
|
||||
|
||||
|
|
@ -1362,7 +1368,7 @@ int atomctrl_get_avfs_information(struct pp_hwmgr *hwmgr,
|
|||
return -EINVAL;
|
||||
|
||||
profile = (ATOM_ASIC_PROFILING_INFO_V3_6 *)
|
||||
cgs_atom_get_data_table(hwmgr->device,
|
||||
smu_atom_get_data_table(hwmgr->adev,
|
||||
GetIndexIntoMasterTable(DATA, ASIC_ProfilingInfo),
|
||||
NULL, NULL, NULL);
|
||||
if (!profile)
|
||||
|
|
@ -1402,7 +1408,7 @@ int atomctrl_get_svi2_info(struct pp_hwmgr *hwmgr, uint8_t voltage_type,
|
|||
uint16_t *load_line)
|
||||
{
|
||||
ATOM_VOLTAGE_OBJECT_INFO_V3_1 *voltage_info =
|
||||
(ATOM_VOLTAGE_OBJECT_INFO_V3_1 *)get_voltage_info_table(hwmgr->device);
|
||||
(ATOM_VOLTAGE_OBJECT_INFO_V3_1 *)get_voltage_info_table(hwmgr->adev);
|
||||
|
||||
const ATOM_VOLTAGE_OBJECT_V3 *voltage_object;
|
||||
|
||||
|
|
@ -1421,16 +1427,17 @@ int atomctrl_get_svi2_info(struct pp_hwmgr *hwmgr, uint8_t voltage_type,
|
|||
|
||||
int atomctrl_get_leakage_id_from_efuse(struct pp_hwmgr *hwmgr, uint16_t *virtual_voltage_id)
|
||||
{
|
||||
int result;
|
||||
struct amdgpu_device *adev = hwmgr->adev;
|
||||
SET_VOLTAGE_PS_ALLOCATION allocation;
|
||||
SET_VOLTAGE_PARAMETERS_V1_3 *voltage_parameters =
|
||||
(SET_VOLTAGE_PARAMETERS_V1_3 *)&allocation.sASICSetVoltage;
|
||||
int result;
|
||||
|
||||
voltage_parameters->ucVoltageMode = ATOM_GET_LEAKAGE_ID;
|
||||
|
||||
result = cgs_atom_exec_cmd_table(hwmgr->device,
|
||||
result = amdgpu_atom_execute_table(adev->mode_info.atom_context,
|
||||
GetIndexIntoMasterTable(COMMAND, SetVoltage),
|
||||
voltage_parameters);
|
||||
(uint32_t *)voltage_parameters);
|
||||
|
||||
*virtual_voltage_id = voltage_parameters->usVoltageLevel;
|
||||
|
||||
|
|
@ -1453,7 +1460,7 @@ int atomctrl_get_leakage_vddc_base_on_leakage(struct pp_hwmgr *hwmgr,
|
|||
ix = GetIndexIntoMasterTable(DATA, ASIC_ProfilingInfo);
|
||||
|
||||
profile = (ATOM_ASIC_PROFILING_INFO_V2_1 *)
|
||||
cgs_atom_get_data_table(hwmgr->device,
|
||||
smu_atom_get_data_table(hwmgr->adev,
|
||||
ix,
|
||||
NULL, NULL, NULL);
|
||||
if (!profile)
|
||||
|
|
|
|||
|
|
@ -298,7 +298,7 @@ extern int atomctrl_get_memory_pll_dividers_vi(struct pp_hwmgr *hwmgr,
|
|||
extern int atomctrl_get_engine_pll_dividers_kong(struct pp_hwmgr *hwmgr,
|
||||
uint32_t clock_value,
|
||||
pp_atomctrl_clock_dividers_kong *dividers);
|
||||
extern int atomctrl_read_efuse(void *device, uint16_t start_index,
|
||||
extern int atomctrl_read_efuse(struct pp_hwmgr *hwmgr, uint16_t start_index,
|
||||
uint16_t end_index, uint32_t mask, uint32_t *efuse);
|
||||
extern int atomctrl_calculate_voltage_evv_on_sclk(struct pp_hwmgr *hwmgr, uint8_t voltage_type,
|
||||
uint32_t sclk, uint16_t virtual_voltage_Id, uint16_t *voltage, uint16_t dpm_level, bool debug);
|
||||
|
|
|
|||
|
|
@ -23,9 +23,9 @@
|
|||
|
||||
#include "ppatomfwctrl.h"
|
||||
#include "atomfirmware.h"
|
||||
#include "atom.h"
|
||||
#include "pp_debug.h"
|
||||
|
||||
|
||||
static const union atom_voltage_object_v4 *pp_atomfwctrl_lookup_voltage_type_v4(
|
||||
const struct atom_voltage_objects_info_v4_1 *voltage_object_info_table,
|
||||
uint8_t voltage_type, uint8_t voltage_mode)
|
||||
|
|
@ -38,35 +38,34 @@ static const union atom_voltage_object_v4 *pp_atomfwctrl_lookup_voltage_type_v4(
|
|||
|
||||
while (offset < size) {
|
||||
const union atom_voltage_object_v4 *voltage_object =
|
||||
(const union atom_voltage_object_v4 *)(start + offset);
|
||||
(const union atom_voltage_object_v4 *)(start + offset);
|
||||
|
||||
if (voltage_type == voltage_object->gpio_voltage_obj.header.voltage_type &&
|
||||
voltage_mode == voltage_object->gpio_voltage_obj.header.voltage_mode)
|
||||
return voltage_object;
|
||||
if (voltage_type == voltage_object->gpio_voltage_obj.header.voltage_type &&
|
||||
voltage_mode == voltage_object->gpio_voltage_obj.header.voltage_mode)
|
||||
return voltage_object;
|
||||
|
||||
offset += le16_to_cpu(voltage_object->gpio_voltage_obj.header.object_size);
|
||||
offset += le16_to_cpu(voltage_object->gpio_voltage_obj.header.object_size);
|
||||
|
||||
}
|
||||
}
|
||||
|
||||
return NULL;
|
||||
return NULL;
|
||||
}
|
||||
|
||||
static struct atom_voltage_objects_info_v4_1 *pp_atomfwctrl_get_voltage_info_table(
|
||||
struct pp_hwmgr *hwmgr)
|
||||
{
|
||||
const void *table_address;
|
||||
uint16_t idx;
|
||||
const void *table_address;
|
||||
uint16_t idx;
|
||||
|
||||
idx = GetIndexIntoMasterDataTable(voltageobject_info);
|
||||
table_address = cgs_atom_get_data_table(hwmgr->device,
|
||||
idx, NULL, NULL, NULL);
|
||||
idx = GetIndexIntoMasterDataTable(voltageobject_info);
|
||||
table_address = smu_atom_get_data_table(hwmgr->adev,
|
||||
idx, NULL, NULL, NULL);
|
||||
|
||||
PP_ASSERT_WITH_CODE(
|
||||
table_address,
|
||||
"Error retrieving BIOS Table Address!",
|
||||
return NULL);
|
||||
PP_ASSERT_WITH_CODE(table_address,
|
||||
"Error retrieving BIOS Table Address!",
|
||||
return NULL);
|
||||
|
||||
return (struct atom_voltage_objects_info_v4_1 *)table_address;
|
||||
return (struct atom_voltage_objects_info_v4_1 *)table_address;
|
||||
}
|
||||
|
||||
/**
|
||||
|
|
@ -167,7 +166,7 @@ static struct atom_gpio_pin_lut_v2_1 *pp_atomfwctrl_get_gpio_lookup_table(
|
|||
uint16_t idx;
|
||||
|
||||
idx = GetIndexIntoMasterDataTable(gpio_pin_lut);
|
||||
table_address = cgs_atom_get_data_table(hwmgr->device,
|
||||
table_address = smu_atom_get_data_table(hwmgr->adev,
|
||||
idx, NULL, NULL, NULL);
|
||||
PP_ASSERT_WITH_CODE(table_address,
|
||||
"Error retrieving BIOS Table Address!",
|
||||
|
|
@ -248,28 +247,30 @@ int pp_atomfwctrl_get_gpu_pll_dividers_vega10(struct pp_hwmgr *hwmgr,
|
|||
uint32_t clock_type, uint32_t clock_value,
|
||||
struct pp_atomfwctrl_clock_dividers_soc15 *dividers)
|
||||
{
|
||||
struct amdgpu_device *adev = hwmgr->adev;
|
||||
struct compute_gpu_clock_input_parameter_v1_8 pll_parameters;
|
||||
struct compute_gpu_clock_output_parameter_v1_8 *pll_output;
|
||||
int result;
|
||||
uint32_t idx;
|
||||
|
||||
pll_parameters.gpuclock_10khz = (uint32_t)clock_value;
|
||||
pll_parameters.gpu_clock_type = clock_type;
|
||||
|
||||
idx = GetIndexIntoMasterCmdTable(computegpuclockparam);
|
||||
result = cgs_atom_exec_cmd_table(hwmgr->device, idx, &pll_parameters);
|
||||
|
||||
if (!result) {
|
||||
pll_output = (struct compute_gpu_clock_output_parameter_v1_8 *)
|
||||
&pll_parameters;
|
||||
dividers->ulClock = le32_to_cpu(pll_output->gpuclock_10khz);
|
||||
dividers->ulDid = le32_to_cpu(pll_output->dfs_did);
|
||||
dividers->ulPll_fb_mult = le32_to_cpu(pll_output->pll_fb_mult);
|
||||
dividers->ulPll_ss_fbsmult = le32_to_cpu(pll_output->pll_ss_fbsmult);
|
||||
dividers->usPll_ss_slew_frac = le16_to_cpu(pll_output->pll_ss_slew_frac);
|
||||
dividers->ucPll_ss_enable = pll_output->pll_ss_enable;
|
||||
}
|
||||
return result;
|
||||
if (amdgpu_atom_execute_table(
|
||||
adev->mode_info.atom_context, idx, (uint32_t *)&pll_parameters))
|
||||
return -EINVAL;
|
||||
|
||||
pll_output = (struct compute_gpu_clock_output_parameter_v1_8 *)
|
||||
&pll_parameters;
|
||||
dividers->ulClock = le32_to_cpu(pll_output->gpuclock_10khz);
|
||||
dividers->ulDid = le32_to_cpu(pll_output->dfs_did);
|
||||
dividers->ulPll_fb_mult = le32_to_cpu(pll_output->pll_fb_mult);
|
||||
dividers->ulPll_ss_fbsmult = le32_to_cpu(pll_output->pll_ss_fbsmult);
|
||||
dividers->usPll_ss_slew_frac = le16_to_cpu(pll_output->pll_ss_slew_frac);
|
||||
dividers->ucPll_ss_enable = pll_output->pll_ss_enable;
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
int pp_atomfwctrl_get_avfs_information(struct pp_hwmgr *hwmgr,
|
||||
|
|
@ -283,7 +284,7 @@ int pp_atomfwctrl_get_avfs_information(struct pp_hwmgr *hwmgr,
|
|||
|
||||
idx = GetIndexIntoMasterDataTable(asic_profiling_info);
|
||||
profile = (struct atom_asic_profiling_info_v4_1 *)
|
||||
cgs_atom_get_data_table(hwmgr->device,
|
||||
smu_atom_get_data_table(hwmgr->adev,
|
||||
idx, NULL, NULL, NULL);
|
||||
|
||||
if (!profile)
|
||||
|
|
@ -467,7 +468,7 @@ int pp_atomfwctrl_get_gpio_information(struct pp_hwmgr *hwmgr,
|
|||
|
||||
idx = GetIndexIntoMasterDataTable(smu_info);
|
||||
info = (struct atom_smu_info_v3_1 *)
|
||||
cgs_atom_get_data_table(hwmgr->device,
|
||||
smu_atom_get_data_table(hwmgr->adev,
|
||||
idx, NULL, NULL, NULL);
|
||||
|
||||
if (!info) {
|
||||
|
|
@ -489,6 +490,7 @@ int pp_atomfwctrl_get_gpio_information(struct pp_hwmgr *hwmgr,
|
|||
|
||||
int pp_atomfwctrl__get_clk_information_by_clkid(struct pp_hwmgr *hwmgr, BIOS_CLKID id, uint32_t *frequency)
|
||||
{
|
||||
struct amdgpu_device *adev = hwmgr->adev;
|
||||
struct atom_get_smu_clock_info_parameters_v3_1 parameters;
|
||||
struct atom_get_smu_clock_info_output_parameters_v3_1 *output;
|
||||
uint32_t ix;
|
||||
|
|
@ -497,13 +499,13 @@ int pp_atomfwctrl__get_clk_information_by_clkid(struct pp_hwmgr *hwmgr, BIOS_CLK
|
|||
parameters.command = GET_SMU_CLOCK_INFO_V3_1_GET_CLOCK_FREQ;
|
||||
|
||||
ix = GetIndexIntoMasterCmdTable(getsmuclockinfo);
|
||||
if (!cgs_atom_exec_cmd_table(hwmgr->device, ix, ¶meters)) {
|
||||
output = (struct atom_get_smu_clock_info_output_parameters_v3_1 *)¶meters;
|
||||
*frequency = output->atom_smu_outputclkfreq.smu_clock_freq_hz / 10000;
|
||||
} else {
|
||||
pr_info("Error execute_table getsmuclockinfo!");
|
||||
return -1;
|
||||
}
|
||||
|
||||
if (amdgpu_atom_execute_table(
|
||||
adev->mode_info.atom_context, ix, (uint32_t *)¶meters))
|
||||
return -EINVAL;
|
||||
|
||||
output = (struct atom_get_smu_clock_info_output_parameters_v3_1 *)¶meters;
|
||||
*frequency = output->atom_smu_outputclkfreq.smu_clock_freq_hz / 10000;
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
|
@ -517,7 +519,7 @@ int pp_atomfwctrl_get_vbios_bootup_values(struct pp_hwmgr *hwmgr,
|
|||
|
||||
ix = GetIndexIntoMasterDataTable(firmwareinfo);
|
||||
info = (struct atom_firmware_info_v3_1 *)
|
||||
cgs_atom_get_data_table(hwmgr->device,
|
||||
smu_atom_get_data_table(hwmgr->adev,
|
||||
ix, NULL, NULL, NULL);
|
||||
|
||||
if (!info) {
|
||||
|
|
@ -553,7 +555,7 @@ int pp_atomfwctrl_get_smc_dpm_information(struct pp_hwmgr *hwmgr,
|
|||
|
||||
ix = GetIndexIntoMasterDataTable(smc_dpm_info);
|
||||
info = (struct atom_smc_dpm_info_v4_1 *)
|
||||
cgs_atom_get_data_table(hwmgr->device,
|
||||
smu_atom_get_data_table(hwmgr->adev,
|
||||
ix, NULL, NULL, NULL);
|
||||
if (!info) {
|
||||
pr_info("Error retrieving BIOS Table Address!");
|
||||
|
|
|
|||
|
|
@ -141,7 +141,7 @@ static const void *get_powerplay_table(struct pp_hwmgr *hwmgr)
|
|||
|
||||
if (!table_address) {
|
||||
table_address = (ATOM_Tonga_POWERPLAYTABLE *)
|
||||
cgs_atom_get_data_table(hwmgr->device,
|
||||
smu_atom_get_data_table(hwmgr->adev,
|
||||
index, &size, &frev, &crev);
|
||||
hwmgr->soft_pp_table = table_address; /*Cache the result in RAM.*/
|
||||
hwmgr->soft_pp_table_size = size;
|
||||
|
|
|
|||
|
|
@ -837,7 +837,7 @@ static const ATOM_PPLIB_POWERPLAYTABLE *get_powerplay_table(
|
|||
hwmgr->soft_pp_table = &soft_dummy_pp_table[0];
|
||||
hwmgr->soft_pp_table_size = sizeof(soft_dummy_pp_table);
|
||||
} else {
|
||||
table_addr = cgs_atom_get_data_table(hwmgr->device,
|
||||
table_addr = smu_atom_get_data_table(hwmgr->adev,
|
||||
GetIndexIntoMasterTable(DATA, PowerPlayInfo),
|
||||
&size, &frev, &crev);
|
||||
hwmgr->soft_pp_table = table_addr;
|
||||
|
|
@ -1058,7 +1058,7 @@ static int init_overdrive_limits(struct pp_hwmgr *hwmgr,
|
|||
return 0;
|
||||
|
||||
/* We assume here that fw_info is unchanged if this call fails.*/
|
||||
fw_info = cgs_atom_get_data_table(hwmgr->device,
|
||||
fw_info = smu_atom_get_data_table(hwmgr->adev,
|
||||
GetIndexIntoMasterTable(DATA, FirmwareInfo),
|
||||
&size, &frev, &crev);
|
||||
|
||||
|
|
|
|||
|
|
@ -2957,8 +2957,7 @@ static int smu7_dpm_patch_boot_state(struct pp_hwmgr *hwmgr,
|
|||
/* First retrieve the Boot clocks and VDDC from the firmware info table.
|
||||
* We assume here that fw_info is unchanged if this call fails.
|
||||
*/
|
||||
fw_info = (ATOM_FIRMWARE_INFO_V2_2 *)cgs_atom_get_data_table(
|
||||
hwmgr->device, index,
|
||||
fw_info = (ATOM_FIRMWARE_INFO_V2_2 *)smu_atom_get_data_table(hwmgr->adev, index,
|
||||
&size, &frev, &crev);
|
||||
if (!fw_info)
|
||||
/* During a test, there is no firmware info table. */
|
||||
|
|
|
|||
|
|
@ -314,8 +314,7 @@ static int smu8_get_system_info_data(struct pp_hwmgr *hwmgr)
|
|||
uint8_t frev, crev;
|
||||
uint16_t size;
|
||||
|
||||
info = (ATOM_INTEGRATED_SYSTEM_INFO_V1_9 *) cgs_atom_get_data_table(
|
||||
hwmgr->device,
|
||||
info = (ATOM_INTEGRATED_SYSTEM_INFO_V1_9 *)smu_atom_get_data_table(hwmgr->adev,
|
||||
GetIndexIntoMasterTable(DATA, IntegratedSystemInfo),
|
||||
&size, &frev, &crev);
|
||||
|
||||
|
|
|
|||
|
|
@ -24,6 +24,7 @@
|
|||
#include "pp_debug.h"
|
||||
#include "ppatomctrl.h"
|
||||
#include "ppsmc.h"
|
||||
#include "atom.h"
|
||||
|
||||
uint8_t convert_to_vid(uint16_t vddc)
|
||||
{
|
||||
|
|
@ -608,3 +609,18 @@ int smu9_register_irq_handlers(struct pp_hwmgr *hwmgr)
|
|||
|
||||
return 0;
|
||||
}
|
||||
|
||||
void *smu_atom_get_data_table(void *dev, uint32_t table, uint16_t *size,
|
||||
uint8_t *frev, uint8_t *crev)
|
||||
{
|
||||
struct amdgpu_device *adev = dev;
|
||||
uint16_t data_start;
|
||||
|
||||
if (amdgpu_atom_parse_data_header(
|
||||
adev->mode_info.atom_context, table, size,
|
||||
frev, crev, &data_start))
|
||||
return (uint8_t *)adev->mode_info.atom_context->bios +
|
||||
data_start;
|
||||
|
||||
return NULL;
|
||||
}
|
||||
|
|
|
|||
|
|
@ -82,6 +82,9 @@ int phm_irq_process(struct amdgpu_device *adev,
|
|||
|
||||
int smu9_register_irq_handlers(struct pp_hwmgr *hwmgr);
|
||||
|
||||
void *smu_atom_get_data_table(void *dev, uint32_t table, uint16_t *size,
|
||||
uint8_t *frev, uint8_t *crev);
|
||||
|
||||
#define PHM_FIELD_SHIFT(reg, field) reg##__##field##__SHIFT
|
||||
#define PHM_FIELD_MASK(reg, field) reg##__##field##_MASK
|
||||
|
||||
|
|
|
|||
|
|
@ -52,7 +52,7 @@ static const void *get_powerplay_table(struct pp_hwmgr *hwmgr)
|
|||
|
||||
if (!table_address) {
|
||||
table_address = (ATOM_Vega10_POWERPLAYTABLE *)
|
||||
cgs_atom_get_data_table(hwmgr->device, index,
|
||||
smu_atom_get_data_table(hwmgr->adev, index,
|
||||
&size, &frev, &crev);
|
||||
|
||||
hwmgr->soft_pp_table = table_address; /*Cache the result in RAM.*/
|
||||
|
|
|
|||
|
|
@ -51,7 +51,7 @@ static const void *get_powerplay_table(struct pp_hwmgr *hwmgr)
|
|||
|
||||
if (!table_address) {
|
||||
table_address = (ATOM_Vega12_POWERPLAYTABLE *)
|
||||
cgs_atom_get_data_table(hwmgr->device, index,
|
||||
smu_atom_get_data_table(hwmgr->adev, index,
|
||||
&size, &frev, &crev);
|
||||
|
||||
hwmgr->soft_pp_table = table_address; /*Cache the result in RAM.*/
|
||||
|
|
|
|||
|
|
@ -337,7 +337,7 @@ static bool fiji_is_hw_avfs_present(struct pp_hwmgr *hwmgr)
|
|||
if (!hwmgr->not_vf)
|
||||
return false;
|
||||
|
||||
if (!atomctrl_read_efuse(hwmgr->device, AVFS_EN_LSB, AVFS_EN_MSB,
|
||||
if (!atomctrl_read_efuse(hwmgr, AVFS_EN_LSB, AVFS_EN_MSB,
|
||||
mask, &efuse)) {
|
||||
if (efuse)
|
||||
return true;
|
||||
|
|
|
|||
Loading…
Reference in a new issue