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davinci: clock: add support for setting sysclk rate
Setting sysclk rate will be useful in cases where the sysclk is not at a fixed ratio to the PLL output but can asynchronously be changed. This support forms the basis of attempt to keep the AEMIF clock constant on OMAP-L138 even as PLL0 output changes as ARM clock is changed to save power. This patch has been tested on OMAP-L138. Signed-off-by: Sekhar Nori <nsekhar@ti.com> Signed-off-by: Kevin Hilman <khilman@deeprootsystems.com>
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0a477f6b8c
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2 changed files with 78 additions and 0 deletions
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@ -287,6 +287,79 @@ static unsigned long clk_sysclk_recalc(struct clk *clk)
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return rate;
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}
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int davinci_set_sysclk_rate(struct clk *clk, unsigned long rate)
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{
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unsigned v;
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struct pll_data *pll;
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unsigned long input;
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unsigned ratio = 0;
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/* If this is the PLL base clock, wrong function to call */
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if (clk->pll_data)
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return -EINVAL;
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/* There must be a parent... */
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if (WARN_ON(!clk->parent))
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return -EINVAL;
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/* ... the parent must be a PLL... */
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if (WARN_ON(!clk->parent->pll_data))
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return -EINVAL;
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/* ... and this clock must have a divider. */
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if (WARN_ON(!clk->div_reg))
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return -EINVAL;
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pll = clk->parent->pll_data;
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input = clk->parent->rate;
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/* If pre-PLL, source clock is before the multiplier and divider(s) */
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if (clk->flags & PRE_PLL)
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input = pll->input_rate;
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if (input > rate) {
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/*
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* Can afford to provide an output little higher than requested
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* only if maximum rate supported by hardware on this sysclk
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* is known.
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*/
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if (clk->maxrate) {
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ratio = DIV_ROUND_CLOSEST(input, rate);
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if (input / ratio > clk->maxrate)
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ratio = 0;
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}
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if (ratio == 0)
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ratio = DIV_ROUND_UP(input, rate);
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ratio--;
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}
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if (ratio > PLLDIV_RATIO_MASK)
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return -EINVAL;
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do {
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v = __raw_readl(pll->base + PLLSTAT);
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} while (v & PLLSTAT_GOSTAT);
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v = __raw_readl(pll->base + clk->div_reg);
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v &= ~PLLDIV_RATIO_MASK;
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v |= ratio | PLLDIV_EN;
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__raw_writel(v, pll->base + clk->div_reg);
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v = __raw_readl(pll->base + PLLCMD);
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v |= PLLCMD_GOSET;
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__raw_writel(v, pll->base + PLLCMD);
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do {
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v = __raw_readl(pll->base + PLLSTAT);
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} while (v & PLLSTAT_GOSTAT);
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return 0;
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}
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EXPORT_SYMBOL(davinci_set_sysclk_rate);
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static unsigned long clk_leafclk_recalc(struct clk *clk)
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{
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if (WARN_ON(!clk->parent))
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@ -70,6 +70,9 @@
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#include <linux/list.h>
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#include <asm/clkdev.h>
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#define PLLSTAT_GOSTAT BIT(0)
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#define PLLCMD_GOSET BIT(0)
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struct pll_data {
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u32 phys_base;
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void __iomem *base;
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@ -86,6 +89,7 @@ struct clk {
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struct module *owner;
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const char *name;
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unsigned long rate;
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unsigned long maxrate; /* H/W supported max rate */
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u8 usecount;
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u8 lpsc;
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u8 gpsc;
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@ -118,6 +122,7 @@ struct clk {
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int davinci_clk_init(struct clk_lookup *clocks);
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int davinci_set_pllrate(struct pll_data *pll, unsigned int prediv,
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unsigned int mult, unsigned int postdiv);
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int davinci_set_sysclk_rate(struct clk *clk, unsigned long rate);
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extern struct platform_device davinci_wdt_device;
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extern void davinci_watchdog_reset(struct platform_device *);
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