mirror of
https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git
synced 2024-09-12 05:48:40 +00:00
Merge branch 'drm-fixes' of git://people.freedesktop.org/~airlied/linux
Pull drm fixes from Dave Airlie: "This is radeon and intel fixes, and is a small bit larger than I'm guessing you'd like it to be. - i915: fixes 32-bit highmem i915 blank screen, semaphore hang and runtime pm fix - radeon: gpuvm stability fix for hangs since 3.15, and hang/reboot regression on TN/RL devices, The only slightly controversial one is the change to use GB for the vm_size, which I'm letting through as its a new interface we defined in this merge window, and I'd prefer to have the released kernel have the final interface rather than changing it later" * 'drm-fixes' of git://people.freedesktop.org/~airlied/linux: drm/radeon: fix cut and paste issue for hawaii. drm/radeon: fix irq ring buffer overflow handling drm/i915: Simplify i915_gem_release_all_mmaps() drm/radeon: fix error handling in radeon_vm_bo_set_addr drm/i915: fix freeze with blank screen booting highmem drm/i915: Reorder the semaphore deadlock check, again drm/radeon/TN: only enable bapm on MSI systems drm/radeon: fix VM IB handling drm/radeon: fix handling of radeon_vm_bo_rmv v3 drm/radeon: let's use GB for vm_size (v2)
This commit is contained in:
commit
b401796c95
14 changed files with 147 additions and 89 deletions
|
@ -1616,22 +1616,6 @@ int i915_gem_fault(struct vm_area_struct *vma, struct vm_fault *vmf)
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return ret;
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}
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void i915_gem_release_all_mmaps(struct drm_i915_private *dev_priv)
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{
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struct i915_vma *vma;
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/*
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* Only the global gtt is relevant for gtt memory mappings, so restrict
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* list traversal to objects bound into the global address space. Note
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* that the active list should be empty, but better safe than sorry.
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*/
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WARN_ON(!list_empty(&dev_priv->gtt.base.active_list));
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list_for_each_entry(vma, &dev_priv->gtt.base.active_list, mm_list)
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i915_gem_release_mmap(vma->obj);
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list_for_each_entry(vma, &dev_priv->gtt.base.inactive_list, mm_list)
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i915_gem_release_mmap(vma->obj);
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}
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/**
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* i915_gem_release_mmap - remove physical page mappings
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* @obj: obj in question
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@ -1657,6 +1641,15 @@ i915_gem_release_mmap(struct drm_i915_gem_object *obj)
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obj->fault_mappable = false;
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}
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void
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i915_gem_release_all_mmaps(struct drm_i915_private *dev_priv)
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{
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struct drm_i915_gem_object *obj;
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list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list)
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i915_gem_release_mmap(obj);
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}
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uint32_t
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i915_gem_get_gtt_size(struct drm_device *dev, uint32_t size, int tiling_mode)
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{
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@ -31,7 +31,7 @@
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struct i915_render_state {
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struct drm_i915_gem_object *obj;
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unsigned long ggtt_offset;
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void *batch;
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u32 *batch;
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u32 size;
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u32 len;
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};
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@ -80,7 +80,7 @@ static struct i915_render_state *render_state_alloc(struct drm_device *dev)
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static void render_state_free(struct i915_render_state *so)
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{
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kunmap(so->batch);
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kunmap(kmap_to_page(so->batch));
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i915_gem_object_ggtt_unpin(so->obj);
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drm_gem_object_unreference(&so->obj->base);
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kfree(so);
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@ -2845,7 +2845,7 @@ static int semaphore_passed(struct intel_engine_cs *ring)
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{
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struct drm_i915_private *dev_priv = ring->dev->dev_private;
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struct intel_engine_cs *signaller;
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u32 seqno, ctl;
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u32 seqno;
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ring->hangcheck.deadlock++;
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@ -2857,15 +2857,12 @@ static int semaphore_passed(struct intel_engine_cs *ring)
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if (signaller->hangcheck.deadlock >= I915_NUM_RINGS)
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return -1;
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/* cursory check for an unkickable deadlock */
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ctl = I915_READ_CTL(signaller);
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if (ctl & RING_WAIT_SEMAPHORE && semaphore_passed(signaller) < 0)
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return -1;
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if (i915_seqno_passed(signaller->get_seqno(signaller, false), seqno))
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return 1;
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if (signaller->hangcheck.deadlock)
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/* cursory check for an unkickable deadlock */
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if (I915_READ_CTL(signaller) & RING_WAIT_SEMAPHORE &&
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semaphore_passed(signaller) < 0)
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return -1;
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return 0;
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@ -2291,6 +2291,7 @@ static void cik_tiling_mode_table_init(struct radeon_device *rdev)
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gb_tile_moden = 0;
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break;
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}
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rdev->config.cik.macrotile_mode_array[reg_offset] = gb_tile_moden;
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WREG32(GB_MACROTILE_MODE0 + (reg_offset * 4), gb_tile_moden);
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}
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} else if (num_pipe_configs == 8) {
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@ -7376,6 +7377,7 @@ static inline u32 cik_get_ih_wptr(struct radeon_device *rdev)
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tmp = RREG32(IH_RB_CNTL);
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tmp |= IH_WPTR_OVERFLOW_CLEAR;
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WREG32(IH_RB_CNTL, tmp);
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wptr &= ~RB_OVERFLOW;
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}
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return (wptr & rdev->ih.ptr_mask);
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}
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@ -4756,6 +4756,7 @@ static u32 evergreen_get_ih_wptr(struct radeon_device *rdev)
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tmp = RREG32(IH_RB_CNTL);
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tmp |= IH_WPTR_OVERFLOW_CLEAR;
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WREG32(IH_RB_CNTL, tmp);
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wptr &= ~RB_OVERFLOW;
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}
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return (wptr & rdev->ih.ptr_mask);
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}
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@ -3795,6 +3795,7 @@ static u32 r600_get_ih_wptr(struct radeon_device *rdev)
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tmp = RREG32(IH_RB_CNTL);
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tmp |= IH_WPTR_OVERFLOW_CLEAR;
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WREG32(IH_RB_CNTL, tmp);
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wptr &= ~RB_OVERFLOW;
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}
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return (wptr & rdev->ih.ptr_mask);
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}
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@ -449,6 +449,7 @@ struct radeon_bo_va {
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/* protected by vm mutex */
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struct list_head vm_list;
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struct list_head vm_status;
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/* constant after initialization */
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struct radeon_vm *vm;
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@ -867,6 +868,9 @@ struct radeon_vm {
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struct list_head va;
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unsigned id;
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/* BOs freed, but not yet updated in the PT */
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struct list_head freed;
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/* contains the page directory */
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struct radeon_bo *page_directory;
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uint64_t pd_gpu_addr;
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@ -875,6 +879,8 @@ struct radeon_vm {
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/* array of page tables, one for each page directory entry */
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struct radeon_vm_pt *page_tables;
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struct radeon_bo_va *ib_bo_va;
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struct mutex mutex;
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/* last fence for cs using this vm */
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struct radeon_fence *fence;
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@ -2832,9 +2838,10 @@ void radeon_vm_fence(struct radeon_device *rdev,
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uint64_t radeon_vm_map_gart(struct radeon_device *rdev, uint64_t addr);
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int radeon_vm_update_page_directory(struct radeon_device *rdev,
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struct radeon_vm *vm);
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int radeon_vm_clear_freed(struct radeon_device *rdev,
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struct radeon_vm *vm);
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int radeon_vm_bo_update(struct radeon_device *rdev,
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struct radeon_vm *vm,
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struct radeon_bo *bo,
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struct radeon_bo_va *bo_va,
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struct ttm_mem_reg *mem);
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void radeon_vm_bo_invalidate(struct radeon_device *rdev,
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struct radeon_bo *bo);
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@ -2847,8 +2854,8 @@ int radeon_vm_bo_set_addr(struct radeon_device *rdev,
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struct radeon_bo_va *bo_va,
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uint64_t offset,
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uint32_t flags);
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int radeon_vm_bo_rmv(struct radeon_device *rdev,
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struct radeon_bo_va *bo_va);
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void radeon_vm_bo_rmv(struct radeon_device *rdev,
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struct radeon_bo_va *bo_va);
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/* audio */
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void r600_audio_update_hdmi(struct work_struct *work);
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@ -461,13 +461,23 @@ static int radeon_bo_vm_update_pte(struct radeon_cs_parser *p,
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struct radeon_vm *vm)
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{
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struct radeon_device *rdev = p->rdev;
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struct radeon_bo_va *bo_va;
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int i, r;
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r = radeon_vm_update_page_directory(rdev, vm);
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if (r)
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return r;
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r = radeon_vm_bo_update(rdev, vm, rdev->ring_tmp_bo.bo,
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r = radeon_vm_clear_freed(rdev, vm);
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if (r)
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return r;
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if (vm->ib_bo_va == NULL) {
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DRM_ERROR("Tmp BO not in VM!\n");
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return -EINVAL;
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}
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r = radeon_vm_bo_update(rdev, vm->ib_bo_va,
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&rdev->ring_tmp_bo.bo->tbo.mem);
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if (r)
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return r;
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@ -480,7 +490,13 @@ static int radeon_bo_vm_update_pte(struct radeon_cs_parser *p,
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continue;
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bo = p->relocs[i].robj;
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r = radeon_vm_bo_update(rdev, vm, bo, &bo->tbo.mem);
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bo_va = radeon_vm_bo_find(vm, bo);
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if (bo_va == NULL) {
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dev_err(rdev->dev, "bo %p not in vm %p\n", bo, vm);
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return -EINVAL;
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}
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r = radeon_vm_bo_update(rdev, bo_va, &bo->tbo.mem);
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if (r)
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return r;
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}
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@ -1056,36 +1056,36 @@ static void radeon_check_arguments(struct radeon_device *rdev)
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if (!radeon_check_pot_argument(radeon_vm_size)) {
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dev_warn(rdev->dev, "VM size (%d) must be a power of 2\n",
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radeon_vm_size);
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radeon_vm_size = 4096;
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radeon_vm_size = 4;
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}
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if (radeon_vm_size < 4) {
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dev_warn(rdev->dev, "VM size (%d) to small, min is 4MB\n",
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if (radeon_vm_size < 1) {
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dev_warn(rdev->dev, "VM size (%d) to small, min is 1GB\n",
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radeon_vm_size);
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radeon_vm_size = 4096;
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radeon_vm_size = 4;
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}
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/*
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* Max GPUVM size for Cayman, SI and CI are 40 bits.
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*/
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if (radeon_vm_size > 1024*1024) {
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dev_warn(rdev->dev, "VM size (%d) to large, max is 1TB\n",
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if (radeon_vm_size > 1024) {
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dev_warn(rdev->dev, "VM size (%d) too large, max is 1TB\n",
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radeon_vm_size);
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radeon_vm_size = 4096;
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radeon_vm_size = 4;
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}
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/* defines number of bits in page table versus page directory,
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* a page is 4KB so we have 12 bits offset, minimum 9 bits in the
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* page table and the remaining bits are in the page directory */
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if (radeon_vm_block_size < 9) {
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dev_warn(rdev->dev, "VM page table size (%d) to small\n",
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dev_warn(rdev->dev, "VM page table size (%d) too small\n",
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radeon_vm_block_size);
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radeon_vm_block_size = 9;
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}
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if (radeon_vm_block_size > 24 ||
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radeon_vm_size < (1ull << radeon_vm_block_size)) {
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dev_warn(rdev->dev, "VM page table size (%d) to large\n",
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(radeon_vm_size * 1024) < (1ull << radeon_vm_block_size)) {
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dev_warn(rdev->dev, "VM page table size (%d) too large\n",
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radeon_vm_block_size);
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radeon_vm_block_size = 9;
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}
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|
@ -1238,7 +1238,7 @@ int radeon_device_init(struct radeon_device *rdev,
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/* Adjust VM size here.
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* Max GPUVM size for cayman+ is 40 bits.
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*/
|
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rdev->vm_manager.max_pfn = radeon_vm_size << 8;
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rdev->vm_manager.max_pfn = radeon_vm_size << 18;
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|
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/* Set asic functions */
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r = radeon_asic_init(rdev);
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|
|
|
@ -173,7 +173,7 @@ int radeon_dpm = -1;
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int radeon_aspm = -1;
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int radeon_runtime_pm = -1;
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int radeon_hard_reset = 0;
|
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int radeon_vm_size = 4096;
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int radeon_vm_size = 4;
|
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int radeon_vm_block_size = 9;
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int radeon_deep_color = 0;
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|
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|
@ -243,7 +243,7 @@ module_param_named(runpm, radeon_runtime_pm, int, 0444);
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MODULE_PARM_DESC(hard_reset, "PCI config reset (1 = force enable, 0 = disable (default))");
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module_param_named(hard_reset, radeon_hard_reset, int, 0444);
|
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|
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MODULE_PARM_DESC(vm_size, "VM address space size in megabytes (default 4GB)");
|
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MODULE_PARM_DESC(vm_size, "VM address space size in gigabytes (default 4GB)");
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module_param_named(vm_size, radeon_vm_size, int, 0444);
|
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|
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MODULE_PARM_DESC(vm_block_size, "VM page table size in bits (default 9)");
|
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|
|
|
@ -579,7 +579,7 @@ int radeon_driver_open_kms(struct drm_device *dev, struct drm_file *file_priv)
|
|||
/* new gpu have virtual address space support */
|
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if (rdev->family >= CHIP_CAYMAN) {
|
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struct radeon_fpriv *fpriv;
|
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struct radeon_bo_va *bo_va;
|
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struct radeon_vm *vm;
|
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int r;
|
||||
|
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fpriv = kzalloc(sizeof(*fpriv), GFP_KERNEL);
|
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|
@ -587,7 +587,8 @@ int radeon_driver_open_kms(struct drm_device *dev, struct drm_file *file_priv)
|
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return -ENOMEM;
|
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}
|
||||
|
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r = radeon_vm_init(rdev, &fpriv->vm);
|
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vm = &fpriv->vm;
|
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r = radeon_vm_init(rdev, vm);
|
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if (r) {
|
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kfree(fpriv);
|
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return r;
|
||||
|
@ -596,22 +597,23 @@ int radeon_driver_open_kms(struct drm_device *dev, struct drm_file *file_priv)
|
|||
if (rdev->accel_working) {
|
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r = radeon_bo_reserve(rdev->ring_tmp_bo.bo, false);
|
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if (r) {
|
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radeon_vm_fini(rdev, &fpriv->vm);
|
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radeon_vm_fini(rdev, vm);
|
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kfree(fpriv);
|
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return r;
|
||||
}
|
||||
|
||||
/* map the ib pool buffer read only into
|
||||
* virtual address space */
|
||||
bo_va = radeon_vm_bo_add(rdev, &fpriv->vm,
|
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rdev->ring_tmp_bo.bo);
|
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r = radeon_vm_bo_set_addr(rdev, bo_va, RADEON_VA_IB_OFFSET,
|
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vm->ib_bo_va = radeon_vm_bo_add(rdev, vm,
|
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rdev->ring_tmp_bo.bo);
|
||||
r = radeon_vm_bo_set_addr(rdev, vm->ib_bo_va,
|
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RADEON_VA_IB_OFFSET,
|
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RADEON_VM_PAGE_READABLE |
|
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RADEON_VM_PAGE_SNOOPED);
|
||||
|
||||
radeon_bo_unreserve(rdev->ring_tmp_bo.bo);
|
||||
if (r) {
|
||||
radeon_vm_fini(rdev, &fpriv->vm);
|
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radeon_vm_fini(rdev, vm);
|
||||
kfree(fpriv);
|
||||
return r;
|
||||
}
|
||||
|
@ -640,21 +642,19 @@ void radeon_driver_postclose_kms(struct drm_device *dev,
|
|||
/* new gpu have virtual address space support */
|
||||
if (rdev->family >= CHIP_CAYMAN && file_priv->driver_priv) {
|
||||
struct radeon_fpriv *fpriv = file_priv->driver_priv;
|
||||
struct radeon_bo_va *bo_va;
|
||||
struct radeon_vm *vm = &fpriv->vm;
|
||||
int r;
|
||||
|
||||
if (rdev->accel_working) {
|
||||
r = radeon_bo_reserve(rdev->ring_tmp_bo.bo, false);
|
||||
if (!r) {
|
||||
bo_va = radeon_vm_bo_find(&fpriv->vm,
|
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rdev->ring_tmp_bo.bo);
|
||||
if (bo_va)
|
||||
radeon_vm_bo_rmv(rdev, bo_va);
|
||||
if (vm->ib_bo_va)
|
||||
radeon_vm_bo_rmv(rdev, vm->ib_bo_va);
|
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radeon_bo_unreserve(rdev->ring_tmp_bo.bo);
|
||||
}
|
||||
}
|
||||
|
||||
radeon_vm_fini(rdev, &fpriv->vm);
|
||||
radeon_vm_fini(rdev, vm);
|
||||
kfree(fpriv);
|
||||
file_priv->driver_priv = NULL;
|
||||
}
|
||||
|
|
|
@ -332,6 +332,7 @@ struct radeon_bo_va *radeon_vm_bo_add(struct radeon_device *rdev,
|
|||
bo_va->ref_count = 1;
|
||||
INIT_LIST_HEAD(&bo_va->bo_list);
|
||||
INIT_LIST_HEAD(&bo_va->vm_list);
|
||||
INIT_LIST_HEAD(&bo_va->vm_status);
|
||||
|
||||
mutex_lock(&vm->mutex);
|
||||
list_add(&bo_va->vm_list, &vm->va);
|
||||
|
@ -468,6 +469,19 @@ int radeon_vm_bo_set_addr(struct radeon_device *rdev,
|
|||
head = &tmp->vm_list;
|
||||
}
|
||||
|
||||
if (bo_va->soffset) {
|
||||
/* add a clone of the bo_va to clear the old address */
|
||||
tmp = kzalloc(sizeof(struct radeon_bo_va), GFP_KERNEL);
|
||||
if (!tmp) {
|
||||
mutex_unlock(&vm->mutex);
|
||||
return -ENOMEM;
|
||||
}
|
||||
tmp->soffset = bo_va->soffset;
|
||||
tmp->eoffset = bo_va->eoffset;
|
||||
tmp->vm = vm;
|
||||
list_add(&tmp->vm_status, &vm->freed);
|
||||
}
|
||||
|
||||
bo_va->soffset = soffset;
|
||||
bo_va->eoffset = eoffset;
|
||||
bo_va->flags = flags;
|
||||
|
@ -823,25 +837,19 @@ static void radeon_vm_update_ptes(struct radeon_device *rdev,
|
|||
* Object have to be reserved and mutex must be locked!
|
||||
*/
|
||||
int radeon_vm_bo_update(struct radeon_device *rdev,
|
||||
struct radeon_vm *vm,
|
||||
struct radeon_bo *bo,
|
||||
struct radeon_bo_va *bo_va,
|
||||
struct ttm_mem_reg *mem)
|
||||
{
|
||||
struct radeon_vm *vm = bo_va->vm;
|
||||
struct radeon_ib ib;
|
||||
struct radeon_bo_va *bo_va;
|
||||
unsigned nptes, ndw;
|
||||
uint64_t addr;
|
||||
int r;
|
||||
|
||||
bo_va = radeon_vm_bo_find(vm, bo);
|
||||
if (bo_va == NULL) {
|
||||
dev_err(rdev->dev, "bo %p not in vm %p\n", bo, vm);
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
if (!bo_va->soffset) {
|
||||
dev_err(rdev->dev, "bo %p don't has a mapping in vm %p\n",
|
||||
bo, vm);
|
||||
bo_va->bo, vm);
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
|
@ -868,7 +876,7 @@ int radeon_vm_bo_update(struct radeon_device *rdev,
|
|||
|
||||
trace_radeon_vm_bo_update(bo_va);
|
||||
|
||||
nptes = radeon_bo_ngpu_pages(bo);
|
||||
nptes = (bo_va->eoffset - bo_va->soffset) / RADEON_GPU_PAGE_SIZE;
|
||||
|
||||
/* padding, etc. */
|
||||
ndw = 64;
|
||||
|
@ -910,6 +918,34 @@ int radeon_vm_bo_update(struct radeon_device *rdev,
|
|||
return 0;
|
||||
}
|
||||
|
||||
/**
|
||||
* radeon_vm_clear_freed - clear freed BOs in the PT
|
||||
*
|
||||
* @rdev: radeon_device pointer
|
||||
* @vm: requested vm
|
||||
*
|
||||
* Make sure all freed BOs are cleared in the PT.
|
||||
* Returns 0 for success.
|
||||
*
|
||||
* PTs have to be reserved and mutex must be locked!
|
||||
*/
|
||||
int radeon_vm_clear_freed(struct radeon_device *rdev,
|
||||
struct radeon_vm *vm)
|
||||
{
|
||||
struct radeon_bo_va *bo_va, *tmp;
|
||||
int r;
|
||||
|
||||
list_for_each_entry_safe(bo_va, tmp, &vm->freed, vm_status) {
|
||||
list_del(&bo_va->vm_status);
|
||||
r = radeon_vm_bo_update(rdev, bo_va, NULL);
|
||||
kfree(bo_va);
|
||||
if (r)
|
||||
return r;
|
||||
}
|
||||
return 0;
|
||||
|
||||
}
|
||||
|
||||
/**
|
||||
* radeon_vm_bo_rmv - remove a bo to a specific vm
|
||||
*
|
||||
|
@ -917,27 +953,27 @@ int radeon_vm_bo_update(struct radeon_device *rdev,
|
|||
* @bo_va: requested bo_va
|
||||
*
|
||||
* Remove @bo_va->bo from the requested vm (cayman+).
|
||||
* Remove @bo_va->bo from the list of bos associated with the bo_va->vm and
|
||||
* remove the ptes for @bo_va in the page table.
|
||||
* Returns 0 for success.
|
||||
*
|
||||
* Object have to be reserved!
|
||||
*/
|
||||
int radeon_vm_bo_rmv(struct radeon_device *rdev,
|
||||
struct radeon_bo_va *bo_va)
|
||||
void radeon_vm_bo_rmv(struct radeon_device *rdev,
|
||||
struct radeon_bo_va *bo_va)
|
||||
{
|
||||
int r = 0;
|
||||
struct radeon_vm *vm = bo_va->vm;
|
||||
|
||||
mutex_lock(&bo_va->vm->mutex);
|
||||
if (bo_va->soffset)
|
||||
r = radeon_vm_bo_update(rdev, bo_va->vm, bo_va->bo, NULL);
|
||||
|
||||
list_del(&bo_va->vm_list);
|
||||
mutex_unlock(&bo_va->vm->mutex);
|
||||
list_del(&bo_va->bo_list);
|
||||
|
||||
kfree(bo_va);
|
||||
return r;
|
||||
mutex_lock(&vm->mutex);
|
||||
list_del(&bo_va->vm_list);
|
||||
|
||||
if (bo_va->soffset) {
|
||||
bo_va->bo = NULL;
|
||||
list_add(&bo_va->vm_status, &vm->freed);
|
||||
} else {
|
||||
kfree(bo_va);
|
||||
}
|
||||
|
||||
mutex_unlock(&vm->mutex);
|
||||
}
|
||||
|
||||
/**
|
||||
|
@ -975,11 +1011,13 @@ int radeon_vm_init(struct radeon_device *rdev, struct radeon_vm *vm)
|
|||
int r;
|
||||
|
||||
vm->id = 0;
|
||||
vm->ib_bo_va = NULL;
|
||||
vm->fence = NULL;
|
||||
vm->last_flush = NULL;
|
||||
vm->last_id_use = NULL;
|
||||
mutex_init(&vm->mutex);
|
||||
INIT_LIST_HEAD(&vm->va);
|
||||
INIT_LIST_HEAD(&vm->freed);
|
||||
|
||||
pd_size = radeon_vm_directory_size(rdev);
|
||||
pd_entries = radeon_vm_num_pdes(rdev);
|
||||
|
@ -1034,7 +1072,8 @@ void radeon_vm_fini(struct radeon_device *rdev, struct radeon_vm *vm)
|
|||
kfree(bo_va);
|
||||
}
|
||||
}
|
||||
|
||||
list_for_each_entry_safe(bo_va, tmp, &vm->freed, vm_status)
|
||||
kfree(bo_va);
|
||||
|
||||
for (i = 0; i < radeon_vm_num_pdes(rdev); i++)
|
||||
radeon_bo_unref(&vm->page_tables[i].bo);
|
||||
|
|
|
@ -6103,6 +6103,7 @@ static inline u32 si_get_ih_wptr(struct radeon_device *rdev)
|
|||
tmp = RREG32(IH_RB_CNTL);
|
||||
tmp |= IH_WPTR_OVERFLOW_CLEAR;
|
||||
WREG32(IH_RB_CNTL, tmp);
|
||||
wptr &= ~RB_OVERFLOW;
|
||||
}
|
||||
return (wptr & rdev->ih.ptr_mask);
|
||||
}
|
||||
|
|
|
@ -1874,15 +1874,16 @@ int trinity_dpm_init(struct radeon_device *rdev)
|
|||
for (i = 0; i < SUMO_MAX_HARDWARE_POWERLEVELS; i++)
|
||||
pi->at[i] = TRINITY_AT_DFLT;
|
||||
|
||||
/* There are stability issues reported on latops with
|
||||
* bapm installed when switching between AC and battery
|
||||
* power. At the same time, some desktop boards hang
|
||||
* if it's not enabled and dpm is enabled.
|
||||
/* There are stability issues reported on with
|
||||
* bapm enabled when switching between AC and battery
|
||||
* power. At the same time, some MSI boards hang
|
||||
* if it's not enabled and dpm is enabled. Just enable
|
||||
* it for MSI boards right now.
|
||||
*/
|
||||
if (rdev->flags & RADEON_IS_MOBILITY)
|
||||
pi->enable_bapm = false;
|
||||
else
|
||||
if (rdev->pdev->subsystem_vendor == 0x1462)
|
||||
pi->enable_bapm = true;
|
||||
else
|
||||
pi->enable_bapm = false;
|
||||
pi->enable_nbps_policy = true;
|
||||
pi->enable_sclk_ds = true;
|
||||
pi->enable_gfx_power_gating = true;
|
||||
|
|
Loading…
Reference in a new issue