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ARM: rockchip: fix undefined instruction of reset_ctrl_regs
Sometimes the debug module may not work well after resume, since it has not been correctly reset when wakeup from suspend. That cause system crash during reusme, and a 'undefined instruction' is displayed on the console. Set the GRF_FORCE_JTAG bit of RK3288_GRF_SOC_CON0 can ensure that debug modul is reset. And we can change the value of RK3288_GRF_SOC_CON0 back when system resume. Signed-off-by: Chris Zhong <zyw@rock-chips.com> Tested-by: Caesar Wang <wxt@rock-chips.com> Reviewed-by: Douglas Anderson <dianders@chromium.org> According to discussions, there does not seem a better solution available. Please also see the potential security implication described in the comment inline in the code. Signed-off-by: Heiko Stuebner <heiko@sntech.de>
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2 changed files with 30 additions and 0 deletions
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@ -44,9 +44,11 @@ static void __iomem *rk3288_bootram_base;
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static phys_addr_t rk3288_bootram_phy;
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static struct regmap *pmu_regmap;
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static struct regmap *grf_regmap;
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static struct regmap *sgrf_regmap;
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static u32 rk3288_pmu_pwr_mode_con;
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static u32 rk3288_grf_soc_con0;
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static u32 rk3288_sgrf_soc_con0;
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static inline u32 rk3288_l2_config(void)
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@ -70,11 +72,25 @@ static void rk3288_slp_mode_set(int level)
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{
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u32 mode_set, mode_set1;
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regmap_read(grf_regmap, RK3288_GRF_SOC_CON0, &rk3288_grf_soc_con0);
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regmap_read(sgrf_regmap, RK3288_SGRF_SOC_CON0, &rk3288_sgrf_soc_con0);
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regmap_read(pmu_regmap, RK3288_PMU_PWRMODE_CON,
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&rk3288_pmu_pwr_mode_con);
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/*
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* We need set this bit GRF_FORCE_JTAG here, for the debug module,
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* otherwise, it may become inaccessible after resume.
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* This creates a potential security issue, as the sdmmc pins may
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* accept jtag data for a short time during resume if no card is
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* inserted.
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* But this is of course also true for the regular boot, before we
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* turn of the jtag/sdmmc autodetect.
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*/
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regmap_write(grf_regmap, RK3288_GRF_SOC_CON0, GRF_FORCE_JTAG |
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GRF_FORCE_JTAG_WRITE);
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/*
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* SGRF_FAST_BOOT_EN - system to boot from FAST_BOOT_ADDR
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* PCLK_WDT_GATE - disable WDT during suspend.
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@ -135,6 +151,9 @@ static void rk3288_slp_mode_set_resume(void)
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regmap_write(sgrf_regmap, RK3288_SGRF_SOC_CON0,
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rk3288_sgrf_soc_con0 | SGRF_PCLK_WDT_GATE_WRITE
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| SGRF_FAST_BOOT_EN_WRITE);
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regmap_write(grf_regmap, RK3288_GRF_SOC_CON0, rk3288_grf_soc_con0 |
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GRF_FORCE_JTAG_WRITE);
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}
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static int rockchip_lpmode_enter(unsigned long arg)
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@ -193,6 +212,13 @@ static int rk3288_suspend_init(struct device_node *np)
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return PTR_ERR(pmu_regmap);
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}
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grf_regmap = syscon_regmap_lookup_by_compatible(
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"rockchip,rk3288-grf");
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if (IS_ERR(grf_regmap)) {
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pr_err("%s: could not find grf regmap\n", __func__);
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return PTR_ERR(pmu_regmap);
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}
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sram_np = of_find_compatible_node(NULL, NULL,
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"rockchip,rk3288-pmu-sram");
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if (!sram_np) {
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@ -48,6 +48,10 @@ static inline void rockchip_suspend_init(void)
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#define RK3288_PMU_WAKEUP_RST_CLR_CNT 0x44
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#define RK3288_PMU_PWRMODE_CON1 0x90
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#define RK3288_GRF_SOC_CON0 0x244
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#define GRF_FORCE_JTAG BIT(12)
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#define GRF_FORCE_JTAG_WRITE BIT(28)
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#define RK3288_SGRF_SOC_CON0 (0x0000)
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#define RK3288_SGRF_FAST_BOOT_ADDR (0x0120)
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#define SGRF_PCLK_WDT_GATE BIT(6)
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